KR100488936B1 - LCD - Google Patents

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KR100488936B1
KR100488936B1 KR1019970076762A KR19970076762A KR100488936B1 KR 100488936 B1 KR100488936 B1 KR 100488936B1 KR 1019970076762 A KR1019970076762 A KR 1019970076762A KR 19970076762 A KR19970076762 A KR 19970076762A KR 100488936 B1 KR100488936 B1 KR 100488936B1
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South Korea
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data line
liquid crystal
crystal display
light blocking
blocking layer
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KR1019970076762A
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Korean (ko)
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KR19990056751A (en
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손정석
곽상엽
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비오이 하이디스 테크놀로지 주식회사
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Priority to KR1019970076762A priority Critical patent/KR100488936B1/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Abstract

본 발명은 데이터 라인의 저항을 감소시킬 수 있는 액정 표시 소자를 제공한다.The present invention provides a liquid crystal display device capable of reducing the resistance of the data line.

본 발명에 따른 액정 표시 소자는, 차광층을 구비한 스위칭 소자와, 게이트 및 데이터 라인의 신호전극을 구비하고, 차광층은 데이터 라인과 병렬연결된 것을 특징으로 한다. 여기서, 차광층은 데이터 라인의 하부에서 데이터 라인과 평행하게 배열되고, 스위칭 소자는 스태거형 박막 트랜지스터인 것을 특징으로 한다.The liquid crystal display device according to the present invention includes a switching element having a light shielding layer, a signal electrode of a gate and a data line, and the light shielding layer is connected in parallel with the data line. Here, the light blocking layer is arranged in parallel with the data line under the data line, and the switching element is a staggered thin film transistor.

Description

액정 표시 소자Liquid crystal display element

본 발명은 액정 표시 소자에 관한 것으로, 특히 데이터 라인의 저항을 감소시킬 수 있는 액정 표시 소자에 관한 것이다.The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that can reduce the resistance of the data line.

액정 표시 소자(Liquid Crystal Display Device)는, 개별 스위칭 소자인 박막 트랜지스터(Thin film transistor)와 화소전극이 구비된 하부기판과, 컬러필터 가 구비된 상부기판이 소정의 셀갭을 두고 합착되고, 상기 셀갭에 의한 공간에 액정이 봉입된 구조로 되어 있다. 이러한 액정 표시 소자는 화소전극과 대향 전극 사이에서 전계가 형성되고, 이 전계 방향에 따라 구동된다.In the liquid crystal display device, a thin film transistor, which is an individual switching element, a lower substrate having a pixel electrode, and an upper substrate having a color filter are bonded to each other with a predetermined cell gap. It has a structure in which a liquid crystal is enclosed in the space by. In such a liquid crystal display device, an electric field is formed between the pixel electrode and the counter electrode, and is driven along the electric field direction.

상기한 액정 표시 소자의 스위칭 소자로서 사용되는 박막 트랜지스터에는 스태거형과 역스태거형이 있다. 스태거형 박막 트랜지스터는 역스태거형 박막 트랜지스터에 비하여 게이트 배선의 저저항화가 가능하고, 제조 공정시 마스크의 수를 감소시킬 수 있는 장점을 갖는다. 반면, 스태거형 박막 트랜지스터는 광에 기인하는 채널층의 누설 전류를 방지하기 위하여 채널층 하부에 별도의 차광층을 구비하여야 한다.There are a staggered type and an inverted staggered type thin film transistor used as the switching element of the liquid crystal display element described above. The staggered thin film transistor has advantages in that the gate wiring can be reduced in resistance compared to the reverse staggered thin film transistor, and the number of masks can be reduced during the manufacturing process. On the other hand, the staggered thin film transistor should have a separate light shielding layer under the channel layer to prevent leakage current of the channel layer due to light.

도 1은 상기한 스태거형 박막 트랜지스터를 이용한 종래의 액정 표시 소자의 평면도이다.1 is a plan view of a conventional liquid crystal display using the staggered thin film transistor.

도 1에 도시된 바와 같이, 데이터 라인(14a)과 게이트 라인(17)이 매트릭스 형태로 배열되고, 게이트 라인(17)과 데이터 라인(14a)에 의해 형성된 공간에 화소전극(14b)이 배열된다. 이때, 데이터 라인(14a)과 화소전극(14b)은 동일 선상에서 게이트 라인(17)과 나란히 교차하고, 교차된 부분에는 스위칭 소자로서 사용되는 스태거형 박막 트랜지스터(100)가 형성된다. 여기서, 박막 트랜지스터(100)는 채널층(15; 도 2 참조)으로의 광을 차단하기 위한 별도의 차광층(12)을 구비한다. As shown in FIG. 1, the data lines 14a and the gate lines 17 are arranged in a matrix, and the pixel electrodes 14b are arranged in a space formed by the gate lines 17 and the data lines 14a. . At this time, the data line 14a and the pixel electrode 14b intersect with the gate line 17 side by side on the same line, and a staggered thin film transistor 100 used as a switching element is formed at the crossed portion. Here, the thin film transistor 100 includes a separate light blocking layer 12 for blocking light to the channel layer 15 (see FIG. 2).

한편, 도 2는 상기한 종래의 스태거형 박막 트랜지스터(100)의 단면도로서, 도 2를 참조하여 그의 제조방법을 살펴본다.2 is a cross-sectional view of the conventional staggered thin film transistor 100 described above, and looks at the manufacturing method thereof with reference to FIG. 2.

먼저, 투명한 절연 기판(11) 상에 크롬 또는 알루미늄과 같은 불투광성 금속막을 증착하고 제 1 패터닝하여 차광층(12)을 형성한다. 그런 다음, 기판 전면에 절연막(13)을 형성하고, 절연막(13) 상에 투명 도전막인 ITO(Indium Tin Oxide)막을 증착하고 제 2 패터닝하여 데이터 라인(14a)과 화소 전극(14b)을 형성한다. 이때, 도시되지는 않았지만, 소오스/드레인 전극이 데이터 라인(14a) 및 화소 전극(14b)의 형성시 동시에 형성된다. First, a light blocking layer 12 is formed by depositing and first patterning an opaque metal film such as chromium or aluminum on the transparent insulating substrate 11. Then, an insulating film 13 is formed on the entire surface of the substrate, and an indium tin oxide (ITO) film, which is a transparent conductive film, is deposited on the insulating film 13 and patterned to form a data line 14a and a pixel electrode 14b. do. At this time, although not shown, source / drain electrodes are simultaneously formed in forming the data line 14a and the pixel electrode 14b.

그런 다음, 기판 전면에 비정질 실리콘막, 절연막, 게이트 물질막을 순차적으로 증착한 후 제 3 패터닝하여, 채널층(15), 게이트 절연막(16), 및 게이트 라인(17)을 형성한다.Thereafter, an amorphous silicon film, an insulating film, and a gate material film are sequentially deposited on the entire surface of the substrate, and then third patterned to form the channel layer 15, the gate insulating film 16, and the gate line 17.

상기한 스태거형 박막 트랜지스터를 이용한 액정 표시 소자는 3회의 패터닝 공정으로 진행되기 때문에, 공정이 단순화되어 원가절감의 효과를 얻을 수 있다. 그러나, 데이터 라인(14a)과 화소전극(14b)을 한번의 패터닝 공정으로 동시에 형성하기 위하여 ITO막으로 데이터 라인(14a)을 형성하기 때문에, 데이터 라인(14a)의 저항이 다른 금속을 이용할 때보다 상대적으로 커지게 된다. 이에 따라, RC 딜레이에 의한 신호 왜곡 등의 문제가 발생하여, 결국 액정 표시 소자의 특성이 저하된다.Since the liquid crystal display device using the staggered thin film transistor is subjected to three patterning processes, the process can be simplified and cost reduction effect can be obtained. However, since the data line 14a is formed of the ITO film in order to simultaneously form the data line 14a and the pixel electrode 14b in one patterning process, the resistance of the data line 14a is higher than that of using a different metal. It becomes relatively large. As a result, problems such as signal distortion due to RC delay occur, resulting in deterioration of the characteristics of the liquid crystal display element.

따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 데이터 라인의 저항을 감소시켜 RC 딜레이에 의한 신호 왜곡을 방지할 수 있는 액정 표시 소자를 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a liquid crystal display device capable of preventing the signal distortion caused by the RC delay by reducing the resistance of the data line.

상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 액정 표시 소자는, 차광층을 구비한 스위칭 소자와, 게이트 및 데이터 라인의 신호전극을 구비하고, 상기 차광층은 상기 데이터 라인과 병렬연결된 것을 특징으로 한다.In order to achieve the above object of the present invention, the liquid crystal display device according to the present invention includes a switching element having a light shielding layer, a signal electrode of a gate and a data line, and the light shielding layer is connected in parallel with the data line. It is characterized by.

여기서, 상기 차광층은 상기 데이터 라인의 하부에서 상기 데이터 라인과 평행하게 배열되고, 상기 스위칭 소자는 스태거형 박막 트랜지스터인 것을 특징으로 한다.The light blocking layer may be arranged in parallel with the data line under the data line, and the switching element may be a staggered thin film transistor.

상기한 본 발명에 의하면, 차광층과 데이터 라인이 병렬연결됨에 따라, 데이터 라인의 저항이 감소된다.According to the present invention described above, as the light blocking layer and the data line are connected in parallel, the resistance of the data line is reduced.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 3은 본 발명의 실시예에 따른 스태거형 박막 트랜지스터를 이용한 액정 표시 소자를 나타낸 평면도이다.3 is a plan view illustrating a liquid crystal display device using a staggered thin film transistor according to an exemplary embodiment of the present invention.

도 3에 도시된 바와 같이, 데이터 라인(44a)과 게이트 라인(47)이 매트릭스 형태로 배열되고, 게이트 라인(47)과 데이터 라인(44a)에 의해 형성된 공간에 화소전극(44b)이 배열된다. 이때, 데이터 라인(44a)과 화소전극(14b)은 동일 선상에서 게이트 라인(47)과 나란히 교차하여 형성되고, 교차된 부분에는 스위칭 소자로서 사용되는 스태거형 박막 트랜지스터(200)가 형성된다. 박막 트랜지스터(200)는 채널층(45; 도 4 참조)으로의 광을 차단하기 위한 별도의 차광층(42)을 구비하는데, 여기서, 차광층(42)은 데이터 라인(44a)의 하부에서 데이터 라인(44a)과 평행하게 배열된다. 또한, 차광층(42)과 데이터 라인(44a)은 서로 콘택(C)되어 병렬연결되어, 데이터 라인(44a)의 저항을 감소시킨다.As shown in FIG. 3, the data lines 44a and the gate lines 47 are arranged in a matrix form, and the pixel electrodes 44b are arranged in the space formed by the gate lines 47 and the data lines 44a. . At this time, the data line 44a and the pixel electrode 14b cross each other in parallel with the gate line 47 on the same line, and the staggered thin film transistor 200 used as a switching element is formed at the crossed portion. The thin film transistor 200 has a separate light shielding layer 42 for blocking light to the channel layer 45 (see FIG. 4), where the light shielding layer 42 has data at the bottom of the data line 44a. It is arranged parallel to the line 44a. In addition, the light blocking layer 42 and the data line 44a are contacted with each other (C) in parallel to reduce the resistance of the data line 44a.

도 4는 본 발명에 따른 스태거형 박막 트랜지스터의 단면도로서, 도 4를 참조하여 그의 제조방법을 살펴본다.4 is a cross-sectional view of a staggered thin film transistor according to the present invention, with reference to FIG.

먼저, 투명한 절연 기판(41) 상에 크롬 또는 알루미늄과 같은 불투광성 금속막을 약 1,000 내지 3,000Å의 두께로 증착하고 제 1 패터닝하여 차광층(42)을 형성한다. 이때, 차광층(42)은 도 3에 도시된 바와 같이, 이후 형성될 데이터 라인 과 평행하게 배열되도록 패터닝한다.First, an opaque metal film such as chromium or aluminum is deposited on the transparent insulating substrate 41 to a thickness of about 1,000 to 3,000 Å and first patterned to form the light shielding layer 42. In this case, as shown in FIG. 3, the light blocking layer 42 is patterned to be arranged in parallel with a data line to be formed later.

그런 다음, 기판 전면에 절연막(43), 바람직하게 SiO2 막을 약 2,500 내지 3,500Å의 두께로 형성하고, 차광층(42)이 소정 부분 노출되도록 절연막(43)을 제 2 패터닝하여 콘택홀을 형성한다. 상기 콘택홀에 매립되도록 절연막(43) 상에 투명 도전막인 ITO막를 약 500 내지 1,000Å의 두께로 증착하고 제 3 패터닝하여 상기 콘택홀을 통하여 차광층(42)과 콘택하는 데이터 라인(44a)을 형성함과 동시에 화소전극(44b)을 형성한다.Then, an insulating film 43, preferably a SiO 2 film, is formed on the entire surface of the substrate to a thickness of about 2,500 to 3,500 kPa, and the second insulating film 43 is patterned so that the light shielding layer 42 is partially exposed to form a contact hole. do. A data line 44a is deposited on the insulating layer 43 to a thickness of about 500 to 1,000 Å on the insulating layer 43 so as to be filled in the contact hole, and third patterned to contact the light shielding layer 42 through the contact hole. And the pixel electrode 44b are formed.

그리고 나서, 기판 전면에 비정질 실리콘막과, SiN막과 같은 절연막을 순차적으로 증착하고, 상기 절연막 상에 Ta막 또는 MoW막과 같은 게이트 물질막을 약 3,000 내지 4,000Å의 두께로 형성한다. 그 후, 상기 게이트 물질막, 절연막 및, 비정질 실리콘막을 제 4 패터닝하여 데이터 라인(44a) 및 화소 전극(44b)과 소정 부분 오버랩되는 채널층(45), 게이트 절연막(46), 및 게이트 라인(47)을 형성한다.Then, an amorphous silicon film and an insulating film such as a SiN film are sequentially deposited on the entire surface of the substrate, and a gate material film such as a Ta film or a MoW film is formed on the insulating film in a thickness of about 3,000 to 4,000 kPa. Thereafter, the gate material film, the insulating film, and the amorphous silicon film are fourth patterned to partially overlap the data line 44a and the pixel electrode 44b with the channel layer 45, the gate insulating film 46, and the gate line ( 47).

상기한 본 발명에 의하면, 차광층을 데이터 라인의 하부에 데이터 라인과 평행하도록 배열하고 데이터 라인과 차광층을 서로 병렬연결함에 따라, 데이터 라인의 저항이 데이터 라인과 차광층과의 병렬 저항값을 갖게 됨으로써, 데이터 라인의 저항이 감소된다. 따라서, ITO막으로 이루어진 데이터 라인에 의해 발생되는 RC 딜레이에 의한 신호 왜곡이 방지된다.According to the present invention described above, as the light blocking layer is arranged parallel to the data line at the bottom of the data line, and the data line and the light blocking layer are connected in parallel with each other, the resistance of the data line reduces the parallel resistance value between the data line and the light blocking layer. By doing so, the resistance of the data line is reduced. Therefore, signal distortion due to the RC delay generated by the data line made of the ITO film is prevented.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

도 1은 종래의 스태거형 박막 트랜지스터를 이용한 액정 표시 소자의 평면도.1 is a plan view of a liquid crystal display device using a conventional staggered thin film transistor.

도 2는 종래의 스태거형 박막 트랜지스터를 나타낸 단면도.2 is a cross-sectional view showing a conventional staggered thin film transistor.

도 3은 본 발명의 실시예에 따른 스태거형 박막 트랜지스터를 이용한 액정 표시 소자의 평면도.3 is a plan view of a liquid crystal display device using a staggered thin film transistor according to an embodiment of the present invention.

도 4는 본 발명의 실시예에 따른 스태거형 박막 트랜지스터를 나타낸 단면도.4 is a cross-sectional view showing a staggered thin film transistor according to an embodiment of the present invention.

〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]

41 : 절연기판 42 : 차광층41: insulating substrate 42: light shielding layer

43 : 절연막 44a : 데이터 라인43: insulating film 44a: data line

44b : 화소전극 45 : 채널층44b: pixel electrode 45: channel layer

46 : 게이트 절연막 47 : 게이트 라인46: gate insulating film 47: gate line

200 : 스태거형 박막 트랜지스터200: staggered thin film transistor

C : 콘택C: Contact

Claims (4)

차광층을 구비한 스위칭 소자와, 게이트 및 데이터 라인의 신호전극을 구비한 액정 표시 소자에 있어서, In the liquid crystal display device comprising a switching element having a light shielding layer and a signal electrode of a gate and a data line, 상기 차광층은 상기 데이터라인 하부에서 데이터라인과 평행하게 배열되며, 상기 차광층과 데이터라인 사이에는 차광층의 소정부분을 노출시키는 콘택홀이 구비된 절연막이 개재되고, 상기 콘택홀을 통해 차광층의 소정부분과 데이터라인이 서로 콘택되어 병렬연결된 것을 특징으로 하는 액정표시 소자.The light blocking layer is arranged in parallel with the data line below the data line, and an insulating layer having a contact hole exposing a predetermined portion of the light blocking layer is interposed between the light blocking layer and the data line, and the light blocking layer is disposed through the contact hole. And a predetermined portion of the data line and the data line are connected in parallel to each other. 제 1 항에 있어서, 상기 스위칭 소자는 스태거형 박막 트랜지스터인 것을 특징으로 하는 액정 표시 소자.The liquid crystal display of claim 1, wherein the switching element is a staggered thin film transistor. 제 1 항에 있어서, 상기 차광층은 크롬 또는 알루미늄막 중 선택된 하나의 막으로 이루어진 것을 특징으로 하는 액정 표시 소자.The liquid crystal display device of claim 1, wherein the light blocking layer is formed of one of chromium and aluminum films. 제 1 항에 있어서, 상기 데이터 라인은 ITO막으로 이루어진 것을 특징으로 하는 액정 표시 소자.The liquid crystal display of claim 1, wherein the data line is made of an ITO film.
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