CN107680976B - Array substrate, display panel and electronic equipment - Google Patents
Array substrate, display panel and electronic equipment Download PDFInfo
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- CN107680976B CN107680976B CN201711033463.8A CN201711033463A CN107680976B CN 107680976 B CN107680976 B CN 107680976B CN 201711033463 A CN201711033463 A CN 201711033463A CN 107680976 B CN107680976 B CN 107680976B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The invention provides an array substrate, a display panel and electronic equipment, wherein the array substrate comprises a substrate, a thin film transistor and a shading metal layer, and the shading metal layer is positioned on one side of the thin film transistor, which is far away from the substrate; the array substrate also comprises a plurality of auxiliary lines, a plurality of data connecting lines and a driving chip; the auxiliary lines are positioned on one side, away from the substrate, of the data lines, the auxiliary lines correspond to the data lines one to one, first insulating layers are arranged between the auxiliary lines and the data lines corresponding to the auxiliary lines one to one at intervals, and at least two auxiliary line through holes are formed to enable the auxiliary lines to be electrically connected; the extending direction of the data connecting line is consistent with the extending direction of the scanning line, the first end of the data connecting line is electrically connected with the data line through the data connecting line through hole, and the second end of the data connecting line is electrically connected with the driving chip; the auxiliary line and the shading metal layer are arranged on the same layer. The invention can reduce or even eliminate the distortion of data signals and improve the display effect of the display panel and the electronic equipment.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and electronic equipment.
Background
In the tft display technology, the tft is generally controlled by a scan line to be turned on, a data signal transmitted on a data line is transmitted to a pixel electrode of a pixel unit through the tft, and an electric field is generated between the pixel electrode and a common electrode to drive a display function layer to realize display. The display function layer may include an organic light emitting material, a liquid crystal material, an electrophoretic material, or the like.
In the prior art, in order to implement a narrow frame, a common wiring manner of the array substrate is a T-wire manner, for example, data lines extending along a first direction and arranged along a second direction may be electrically connected to a driving chip through data connection lines, and scan lines extending along the second direction and arranged along the first direction may be directly electrically connected to the driving chip.
Disclosure of Invention
The invention provides an array substrate, a display panel and electronic equipment, which aim to reduce or even eliminate data signal distortion and improve the display effect of the display panel and the electronic equipment.
In a first aspect, an embodiment of the present invention provides an array substrate, including a display area and a non-display area located at a periphery of the display area, a plurality of data lines and a plurality of scan lines intersect to form a plurality of pixel units arranged in an array in the display area,
the array substrate comprises a substrate, a thin film transistor and a shading metal layer, wherein the shading metal layer is positioned on one side of the thin film transistor, which is far away from the substrate;
the array substrate further comprises a plurality of auxiliary lines, a plurality of data connecting lines and a driving chip; the auxiliary lines are positioned on one side, far away from the substrate, of the data lines, the auxiliary lines correspond to the data lines one by one, a first insulating layer is arranged between each auxiliary line and the corresponding data line one by one, and at least two auxiliary line through holes are formed to enable the auxiliary lines and the data lines to be electrically connected; the extending direction of the data connecting line is consistent with the extending direction of the scanning line, the first end of the data connecting line is electrically connected with the data line through a data connecting line through hole, and the second end of the data connecting line is electrically connected with the driving chip;
the auxiliary line and the shading metal layer are arranged on the same layer.
In a second aspect, an embodiment of the present invention provides a display panel, including the array substrate of the first aspect.
In a third aspect, an embodiment of the present invention provides an electronic device, including the display panel of the second aspect.
In the array substrate provided by the embodiment of the invention, the shading metal layer is positioned on one side of the thin film transistor, which is far away from the substrate, so that light is prevented from irradiating a semiconductor layer of the thin film transistor, and therefore, the thin film transistor is prevented from generating photocurrent under illumination, and the use stability of the thin film transistor is improved. In the prior art, since a data signal of the narrow-frame array substrate is conducted from the driving chip to a specific pixel unit and needs to pass through the data connecting line and the data line, the data line has certain impedance, so that the transmitted data signal has certain distortion, and the display effect is affected. The array substrate provided by the embodiment of the invention also comprises a plurality of auxiliary lines, wherein the auxiliary lines correspond to the data lines one by one and at least two auxiliary line through holes are formed to electrically connect the auxiliary lines and the data lines, so that the auxiliary lines and the data lines between the two auxiliary line through holes form a parallel structure, and compared with the data lines, the parallel structure has smaller impedance during data signal transmission, thereby reducing or even eliminating data signal distortion. On the other hand, the auxiliary line and the shading metal layer are arranged on the same layer, the auxiliary line can comprise the same material as the shading metal layer, the shading metal layer is made of metal materials, and the metal materials have good conductivity, so that data signal distortion can be reduced or even eliminated well.
Drawings
Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention;
FIG. 2 is an enlarged view of the area S1 in FIG. 1;
FIG. 3 is a schematic view of a cross-sectional view along the direction AA' in FIG. 2;
FIG. 4 is a schematic cross-sectional view of the area S2 in FIG. 1;
fig. 5 is a schematic working diagram of an array substrate according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of the area S3 in FIG. 1;
FIG. 7 is a schematic cross-sectional view of the area S3 in FIG. 1;
fig. 8 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view taken along the direction BB' in FIG. 8;
fig. 10 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
FIG. 11 is a schematic cross-sectional view taken along the direction CC' of FIG. 10;
fig. 12 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 13 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 14 is a schematic top view illustrating an array substrate according to another embodiment of the present invention;
fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 16 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic top view of an array substrate according to an embodiment of the present invention, fig. 2 is an enlarged schematic structure of an area S1 in fig. 1, fig. 3 is a schematic cross-sectional structure along an AA' direction in fig. 2, fig. 4 is a schematic cross-sectional structure of an area S2 in fig. 1, and as shown in fig. 1, fig. 2, fig. 3, and fig. 4, the array substrate includes a display area 110 and a non-display area 120 located at a periphery of the display area 110, a plurality of data lines 11 extend along a first direction and are arranged along a second direction, a plurality of scan lines 12 extend along the second direction and are arranged along the first direction, and the plurality of data lines 11 and the plurality of scan lines 12 intersect a plurality of pixel units 13 arranged in an array in the display area 110, where the first direction intersects the second direction. The array substrate comprises a substrate 10, a thin film transistor 30 and a shading metal layer 40, wherein the shading metal layer 40 is positioned on one side of the thin film transistor 30, which is far away from the substrate 10. The thin film transistor 30 includes a gate electrode 31, a semiconductor layer 32, a source electrode 33, and a drain electrode 34, and it is understood that the source electrode 33 and the drain electrode 34 may be used interchangeably, the gate electrode 31 is formed of the same material and at the same layer as the scan line 12, and the source electrode 33 and the drain electrode 34 are formed of the same material and at the same layer as the data line 11. In the embodiment of the invention, the display is realized by controlling the two thin film transistors 30 connected in series, and the two thin film transistors 30 connected in series can reduce leakage current and prompt the display quality. The array substrate further includes a plurality of auxiliary lines 70, a plurality of data link lines 14, and a driving chip 20. The auxiliary lines 70 are located on the side of the data lines 11 away from the substrate 10, the auxiliary lines 70 correspond to the data lines 11 one by one, a first insulating layer 61 is arranged between the auxiliary lines 70 and the data lines 11 corresponding to the auxiliary lines one by one, and at least two auxiliary line through holes F are formed to electrically connect the auxiliary lines 70 and the data lines 11. Illustratively in fig. 1, two auxiliary line vias F are disposed corresponding to one data line 11, and the auxiliary line vias F include a first via F1 located in the non-display area 120 and a second via F2 located in the display area 110. At the first via F1, the data line 11 is electrically connected to the auxiliary line 70. Similarly, at the second through hole F2, the data line 11 is also electrically connected to the auxiliary line 70. The driving chip 20 is electrically connected to the scan lines 12 in the array substrate, and the driving chip 20 is electrically connected to the data lines 11 in the array substrate through the data connection lines 14. The extending direction of the data connecting line 14 is the same as the extending direction of the scan line 12, a first end of the data connecting line 14 is electrically connected to the data line 11 through the data connecting line through hole D, and a second end of the data connecting line 14 is electrically connected to the driving chip 20. The auxiliary line 70 and the shading metal layer 40 can be arranged on the same layer, so that the thickness of the whole array substrate can be reduced, and in addition, the auxiliary line 70 and the shading metal layer 40 can be formed by the same material in the same process, so that only one etching process is needed in the manufacturing process, mask plates do not need to be manufactured on the auxiliary line 70 and the shading metal layer 40 respectively, the cost is saved, the number of manufacturing processes is reduced, and the production efficiency is improved.
Fig. 5 is an operation diagram of an array substrate according to an embodiment of the present invention, and for clarity, fig. 5 shows a part of the auxiliary lines 70 (indicated by dashed lines), and the auxiliary lines 70 are spatially separated from the data lines 11 corresponding to the auxiliary lines 70, as shown in fig. 5, and the directions of arrows indicate the transmission directions of data signals. The structure of the array substrate shown in fig. 5 is the same as that shown in fig. 1, but signal lines are omitted for clarity. In the process of driving a specific pixel unit 131 to display a picture by the driving chip 20, the transmission process of the data signal (current or voltage signal) is as follows: the data signal sent by the driving chip 20 is divided into two paths after reaching the data connection line through hole D along the data connection line 14, and one path is directly transmitted to the pixel unit 131 along the data line 11; the other path is first transferred to the auxiliary line 70 at the first via F1 via the data line 11, then transferred from the auxiliary line 70 to the data line 11 at the second via F2, and finally transferred to the pixel unit 131 via the data line 11. It can be seen that the data signal is transmitted to the pixel unit 131 through the two parallel portions, which has a smaller impedance in data signal transmission than the data signal transmitted through the data line 11 only.
The array substrate provided by the embodiment of the invention comprises the shading metal layer, and the shading metal layer is positioned on one side of the thin film transistor, which is far away from the substrate, so that light is prevented from irradiating a semiconductor layer of the thin film transistor, and therefore, the thin film transistor is prevented from generating photocurrent under illumination, and the use stability of the thin film transistor is improved. In the prior art, since a data signal of the narrow-frame array substrate is conducted from the driving chip to a specific pixel unit and needs to pass through the data connecting line and the data line, the data line has certain impedance, so that the transmitted data signal has certain distortion, and the display effect is affected. The array substrate provided by the embodiment of the invention also comprises a plurality of auxiliary lines, wherein the auxiliary lines correspond to the data lines one by one and at least two auxiliary line through holes are formed to electrically connect the auxiliary lines and the data lines, so that the auxiliary lines and the data lines between the two auxiliary line through holes form a parallel structure, and compared with the data lines, the parallel structure has smaller impedance during data signal transmission, thereby reducing or even eliminating data signal distortion. On the other hand, the auxiliary line and the shading metal layer are arranged on the same layer, the auxiliary line can comprise the same material as the shading metal layer, the shading metal layer is made of metal materials, and the metal materials have good conductivity, so that data signal distortion can be reduced or even eliminated well.
Optionally, referring to fig. 3, the array substrate further includes a storage capacitor C, the first plate C1 of the storage capacitor C is disposed on the same layer as the source 33 and the drain 34 of the thin film transistor 30, that is, the first plate C1 of the storage capacitor C is disposed on the same layer as the data line 11, and the second plate C2 of the storage capacitor C is disposed on the same layer as the gate 31 of the thin film transistor 30, that is, the second plate C2 of the storage capacitor C is disposed on the same layer as the scan line 12. The storage capacitor C is mainly used to keep the charged voltage until the next refresh frame, so the larger the capacitance of the storage capacitor C is, the better the capacitance is. The array substrate provided by the embodiment of the invention comprises the auxiliary lines 70 corresponding to the data lines 11 one by one, the auxiliary lines 70 and the data lines 11 form a parallel structure, and the parallel structure has smaller impedance during data signal transmission, so that under the condition of giving an impedance threshold standard, compared with the data lines which only transmit data signals through the data lines in the prior art, the data lines 11 in the array substrate provided by the embodiment of the invention can be arranged with smaller width, so as to reserve more space for the pixel units 13, and therefore, the areas of the first polar plate C1 and the second polar plate C2 of the storage capacitor C can be appropriately increased, so as to increase the capacitance value of the storage capacitor C.
Alternatively, referring to fig. 1 to 4, the auxiliary lines 70 overlap with the vertical projections of the data lines 11 one-to-one corresponding thereto on the substrate base plate 10. At this time, the vertical projection of the auxiliary line via-hole F on the substrate base plate 10 may be provided in the overlapping region where the auxiliary line 70 and the data line 11 are vertically projected on the substrate base plate 10. Further, the auxiliary lines 70 may be arranged to overlap with the vertical projections of the data lines 11 corresponding to one another on the substrate board 10.
Fig. 6 is a schematic cross-sectional view of the area S3 in fig. 1, and referring to fig. 1 and 6, the data line 11 is electrically connected to the data link line 14 through the data link line via D, and optionally, the data link line 14 may be disposed on the same layer as the scan line 12. The data connecting lines 14 and the scanning lines 12 can be formed by the same material in the same process, so that only one etching process is needed in the manufacturing process, no mask plate needs to be manufactured on the data connecting lines 14 and the scanning lines 12 respectively, and the cost is saved.
Fig. 7 is another schematic cross-sectional view of the area S3 in fig. 1, in which, unlike fig. 6, the auxiliary lines and the data lines 11 corresponding to the auxiliary lines are electrically connected at the data link through holes, and referring to fig. 1, 6 and 7, any one of the auxiliary lines 70 and the data line 11 corresponding to the auxiliary line are electrically connected to each other at the data link through hole D, and the data line 11 is electrically connected to the data link 14 through the data link through hole D. The auxiliary line via F includes a data link line via D, and the auxiliary line 70, the data line 11 and the data link line 11 are electrically connected. It is understood that the provision of vias (e.g., auxiliary line vias F, data link line vias D) in the display area 110 may have an effect on the display area 110, for example, the vias may reduce the area of the pixel unit 13 adjacent thereto. In the embodiment of the present invention, by removing the insulating layer (including the first insulating layer 61) between the auxiliary line 70 and the data line 11 at the data link line via hole D and forming a through auxiliary line via hole F, the number of via holes formed is reduced relative to the formation of the auxiliary line via hole F at other positions of the display area 110 of the array substrate, thereby reducing the influence of the via holes on the display area 110.
Optionally, referring to fig. 3, the array substrate further includes a pixel electrode 50 located on a side of the thin film transistor 30 away from the substrate 10, the pixel electrode 50 may be a transparent electrode, which may be made of Indium Tin Oxide (ITO) or the like, and the pixel electrode 50 is electrically connected to the drain electrode 34 of the thin film transistor 30 through a via. The light-shielding metal layer 40 may be stacked on the side of the pixel electrode 50 away from the substrate base plate 10.
Fig. 8 is a schematic top view of another array substrate according to an embodiment of the present invention, and fig. 9 is a schematic cross-sectional structure along a direction BB' in fig. 8, different from fig. 3, in which the auxiliary lines in fig. 9 are made of two materials in the same layer as both the light-shielding metal layer and the pixel electrodes, and in combination with fig. 8 and fig. 9, a plurality of data lines (not shown in fig. 8, the auxiliary lines 70 are disposed in one-to-one correspondence with the data lines and cover the data lines in a top view) extend along a first direction and are arranged along a second direction, a plurality of auxiliary lines 70 extend along the first direction and are arranged along the second direction, a plurality of scan lines 12 extend along the second direction and are arranged along the first direction, and the plurality of auxiliary lines 70 and the plurality of scan lines 12 intersect a plurality of pixel cells 13 arranged in an array in the display area 110, and the first direction intersects the second direction. The pixel unit 13 includes light-shielding metal layers 40 for shielding light from the semiconductor layer 32 of the thin film transistor 30, any two light-shielding metal layers 40 are electrically insulated from each other, and the light-shielding metal layers 40 are electrically insulated from the auxiliary line 70. The auxiliary line 70 includes a first auxiliary line 71 and a second auxiliary line 72 stacked and disposed in contact with each other, the first auxiliary line 71 being formed of the same material as the light-shielding metal layer 40 in the same layer, and the second auxiliary line 72 being formed of the same material as the pixel electrode 50 in the same layer. Since a further conductive layer is added to the auxiliary line 70 on the same layer as the light-shielding metal layer 40, the conductivity of the auxiliary line 70 is enhanced, and thus the impedance during data signal transmission is further reduced. In other embodiments, an insulating layer may be further disposed between the light-shielding metal layer and the pixel electrode, and the relative positions of the light-shielding metal layer and the pixel electrode are not limited in the embodiments of the present invention.
Fig. 10 is a schematic top view of another array substrate according to an embodiment of the present invention, and fig. 11 is a schematic cross-sectional view along a direction CC' in fig. 10, which is different from fig. 3 in that an insulating layer is disposed between the light-shielding metal layer and the pixel electrode in fig. 11, as shown in fig. 10 and fig. 11, the array substrate further includes a pixel electrode 50 disposed on a side of the thin film transistor 30 away from the substrate 10, a second insulating layer 62 is disposed between the pixel electrode 50 and the light-shielding metal layer 40, and the second insulating layer 62 may be made of the same material as the first insulating layer 61 or different material from the first insulating layer 61. The light-shielding metal layers 40 in the plurality of pixel units 13 connected to the data lines 11 are connected to the auxiliary lines 70 in one-to-one correspondence with the data lines 11, that is, a row of light-shielding metal layers 40 in the first direction and one auxiliary line 70 are integrally formed. In another embodiment, when an insulating layer is provided between the light-shielding metal layer and the pixel electrode, the structure shown in fig. 8 may be employed.
Fig. 12 is a schematic top view of another array substrate according to an embodiment of the present invention, and referring to fig. 2, 3 and 12, the auxiliary line via F includes a first via F1, any one of the auxiliary lines 70 is electrically connected to the data line 11 corresponding to the one-to-one auxiliary line via a first via F1 located in the non-display area 120, and any one of the data lines 11 is located between two first vias F1 along the extending direction (the first direction) of the data line 11. Providing the auxiliary line via F (specifically, referred to as a first via F1) to the non-display area 120 reduces the influence of the via on the display area 110. In addition, referring to fig. 5, the auxiliary lines 70 and the portions of the data lines 11 corresponding one to them between the two auxiliary line vias F form a parallel structure, while the portions other than the two auxiliary line vias F do not form a parallel structure, and the corresponding pixel units 13 other than the two auxiliary line vias F can transmit data signals only through the data lines 11. The auxiliary line through holes are arranged in the non-display area, all the pixel units are considered, and when a data signal is transmitted to any one pixel unit, the data signal can be transmitted through a parallel structure formed by the auxiliary lines and the data lines.
Fig. 13 is a schematic top view of an array substrate according to another embodiment of the present invention, and referring to fig. 2, 3 and 13, the auxiliary line via F includes a second via F2 located in the display area 110, and the auxiliary lines 70 are electrically connected to the data lines 11 corresponding to the auxiliary lines one by one through two second vias F2. It is understood that the auxiliary lines 70 and the data lines 11 one-to-one corresponding thereto may be electrically connected through three or more second through holes F2. In the embodiment, all the second through holes F2 are disposed in the display area 110, and the frame of the array substrate is not increased.
Fig. 14 is a schematic top view structure diagram of another array substrate according to an embodiment of the present invention, and referring to fig. 2, 3 and 14, in the extending direction (the first direction) of the data line 11, the number of the pixel units 13 electrically connected to the data line 11 is M1 (fig. 14 exemplarily shows M1 ═ 6), the data line 11 is electrically connected to the driving chip 20 through M2 (fig. 14 exemplarily shows M2 ═ 1) data connection line vias D, the number of the second vias F2 is M3 (fig. 14 exemplarily shows M2 ═ 5), and M1 ═ M2+ M3. The M2 data link vias D and M3 second vias F2 are spaced apart from the scan lines 12. The plurality of through holes (including the second through hole F2 and the data link through hole D) are uniformly distributed throughout the array substrate, so that the through holes positioned in the display area 110 do not generate macroscopic stripes, and the display quality is ensured. Alternatively, at the data link line through-holes D shown in fig. 14, any one of the auxiliary lines 70 and the data lines 11 one-to-one corresponding thereto may be electrically connected to each other, i.e., three of the auxiliary lines 70, the data lines 11, and the data link lines 11 may be electrically connected.
An embodiment of the present invention provides a display panel, which includes the array substrate in the foregoing embodiments, and the display panel provided in the embodiment of the present invention may be a liquid crystal display panel, an organic light emitting display panel, or an electrophoretic display panel.
In order to clarify the relationship between the display panel and the array substrate, the embodiment of the present invention is briefly introduced by taking an electrophoretic display panel as an example, and fig. 15 is a schematic structural diagram of a display panel provided by the embodiment of the present invention, as shown in fig. 15, the array substrate 100 in the display panel 400 may be an array substrate provided by any of the above embodiments, and the display panel 400 further includes an opposite substrate 200 disposed opposite to the array substrate 100, and electrophoretic particles 300 disposed between the array substrate 100 and the opposite substrate 200. The electrophoretic particles 300 may include white electrophoretic particles 301 and black electrophoretic particles 302, the white electrophoretic particles 301 have a good light reflection characteristic, the black electrophoretic particles 302 have a good light absorption characteristic, and the white electrophoretic particles 301 and the black electrophoretic particles 302 may move under the action of an electric field, so that image display may be achieved by controlling the electric field in different pixels.
An embodiment of the present invention provides an electronic device, fig. 16 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, and as shown in fig. 16, an electronic device 500 according to an embodiment of the present invention includes a display panel 400 according to any embodiment of the present invention, which may be a mobile phone, a computer, a television, an intelligent wearable device, and the like, and this is not particularly limited in the embodiment of the present invention.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (11)
1. An array substrate comprises a display area and a non-display area positioned at the periphery of the display area, wherein a plurality of data lines and a plurality of scanning lines cross a plurality of pixel units arranged in an array in the display area,
the array substrate comprises a substrate, a thin film transistor and a shading metal layer, wherein the shading metal layer is positioned on one side of the thin film transistor, which is far away from the substrate;
the array substrate further comprises a plurality of auxiliary lines, a plurality of data connecting lines and a driving chip; the auxiliary lines are positioned on one side, far away from the substrate, of the data lines, the auxiliary lines correspond to the data lines one by one, a first insulating layer is arranged between each auxiliary line and the corresponding data line one by one, at least two auxiliary line through holes are formed to enable the auxiliary lines and the data lines to be electrically connected, and one auxiliary line is overlapped with a plurality of scanning lines; the extending direction of the data connecting line is consistent with the extending direction of the scanning line, the first end of the data connecting line is electrically connected with the data line through a data connecting line through hole, and the second end of the data connecting line is electrically connected with the driving chip;
the auxiliary line and the shading metal layer are arranged on the same layer;
the array substrate further comprises a pixel electrode positioned on one side of the thin film transistor, which is far away from the substrate, and the shading metal layer is superposed on one side of the pixel electrode, which is far away from the substrate;
the auxiliary lines comprise a first auxiliary line and a second auxiliary line which are stacked and arranged in a contact mode, the first auxiliary line and the light-shielding metal layer are made of the same material in the same layer, and the second auxiliary line and the pixel electrode are made of the same material in the same layer.
2. The array substrate of claim 1, wherein the auxiliary line vias include first vias, and any one of the auxiliary lines and the data line corresponding to the one of the auxiliary lines are electrically connected through the first via in the non-display region; any one data line is located between the two first through holes along the extending direction of the data line.
3. The array substrate of claim 1, wherein any of the auxiliary lines and the data lines corresponding thereto one-to-one are electrically connected to each other at the data link line via holes, the auxiliary line via holes including the data link line via holes.
4. The array substrate of claim 1, wherein the data connection lines are disposed on a same layer as the scan lines.
5. The array substrate of claim 1, wherein the at least two auxiliary line vias are located in the display area;
the auxiliary line through holes comprise second through holes, and the auxiliary lines are electrically connected with the data lines in one-to-one correspondence to the auxiliary lines at the second through holes.
6. The array substrate of claim 5, wherein the number of the pixel units electrically connected to the data lines is M1, the data lines are electrically connected to the driving chip through M2 data connection line vias, the number of the second vias is M3, and M1 is M2+ M3;
m2 data link line through holes and M3 second through holes are distributed at intervals from the scan lines.
7. The array substrate of claim 1, wherein the auxiliary lines and the data lines corresponding thereto one by one overlap in a vertical projection of the substrate.
8. The array substrate of claim 1, further comprising a storage capacitor, wherein a first plate of the storage capacitor is disposed on the same layer as the data line, and a second plate of the storage capacitor is disposed on the same layer as the scan line.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. The display panel according to claim 9, further comprising a counter substrate disposed opposite to the array substrate, and electrophoretic particles between the array substrate and the counter substrate.
11. An electronic device characterized by comprising the display panel according to claim 9 or 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711033463.8A CN107680976B (en) | 2017-10-30 | 2017-10-30 | Array substrate, display panel and electronic equipment |
Applications Claiming Priority (1)
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| CN108873552B (en) * | 2018-06-29 | 2021-10-29 | 上海天马微电子有限公司 | Electronic paper display substrate, display panel and display device |
| CN111243476A (en) * | 2018-11-28 | 2020-06-05 | 中华映管股份有限公司 | Display device |
| US20220367602A1 (en) * | 2020-03-25 | 2022-11-17 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display panel and display device |
| CN111258132A (en) * | 2020-03-31 | 2020-06-09 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| CN111554194A (en) * | 2020-05-25 | 2020-08-18 | Tcl华星光电技术有限公司 | Display panel and display device |
| CN112068368B (en) * | 2020-09-01 | 2021-05-07 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof and display panel |
| CN112255852A (en) * | 2020-10-23 | 2021-01-22 | 深圳市华星光电半导体显示技术有限公司 | Display device and light-emitting panel |
| CN112992933A (en) * | 2021-02-08 | 2021-06-18 | Tcl华星光电技术有限公司 | Drive substrate, display module and display device |
| CN113066799B (en) * | 2021-03-16 | 2022-08-19 | 泉芯集成电路制造(济南)有限公司 | Semiconductor device and method for manufacturing the same |
| CN113514972B (en) * | 2021-04-01 | 2023-10-17 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114220834B (en) * | 2021-12-09 | 2023-07-04 | 武汉华星光电半导体显示技术有限公司 | Display panel |
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| CN102135691B (en) * | 2010-09-17 | 2012-05-23 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and liquid crystal display |
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| KR19990056751A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Liquid crystal display element |
| KR101277221B1 (en) * | 2006-12-22 | 2013-06-24 | 엘지디스플레이 주식회사 | Liquid crystal display device and method of fabricating the same |
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