JP2007158004A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure of a semiconductor device and a manufacturing method wherein, when transistors are formed on a SOI wafer, influences of a charge damage to a gate oxide film of the tarnsistors can be reduced, also, an area for an antennal effect measure is not required to be ensured specially, and a restriction on a layout is small. <P>SOLUTION: The semiconductor device comprises the transistors formed on the SOI substrate, a wiring connected to a terminal for potential fixation of the transistors, and a dummy gate formed on the SOI substrate and not functioning as a normal transistor. The dummy gate has the gate oxide film and a gate electrode layer, which adopts a structure connected to the wiring. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having an SOI (Silicon On Insulator) structure. More particularly, the present invention relates to a structure and a manufacturing method for reducing damage to a gate oxide film of a transistor caused by charge injection during the process.

  In recent years, a technique called SOI has been used in semiconductor devices in order to realize low power consumption and high-speed operability. An IC (integrated circuit) using SOI technology is manufactured from an SOI wafer. The SOI wafer has a structure in which a semiconductor layer serving as an element formation region and a substrate are separated by a thick silicon oxide film (buried oxide film) which is a first insulating film. In the case where a transistor is formed in a semiconductor layer of an SOI wafer, silicon serving as a channel region and a diffusion region is completely insulated from the substrate by a silicon oxide film.

  In recent silicon (Si) processes, the plasma power tends to increase in order to obtain a uniform plasma condition as the wafer diameter increases. As the device elements become finer and faster, the gate oxide film tends to become thinner and the wiring tends to be longer. The amount of charge injected into the wafer during the process further increases due to the increase in the plasma power of the etching and CVD equipment. When these charges are injected into the gate oxide film of the transistor via the wiring or gate, it causes factors such as deterioration of the gate oxide film and fluctuation of characteristics. The effect on the device due to the charge during the plasma process is called PID (Plasma Induced Damage). As the gate oxide film becomes thinner, the electric field due to PID increases, and charges are more easily injected into the gate oxide film. Further, it is known that when the wiring connected to the gate becomes long, charges are collected due to the antenna effect to accelerate the PID.

  FIG. 1 shows the antenna effect. In FIG. 1, reference numeral 10 is a substrate, 12 is a gate oxide film, 14 is a gate electrode, 16 is a conductive material embedded in a contact hole, 18 is a wiring, and 20 is an interlayer insulating film. The antenna effect means that charges injected into a wafer during the process are collected by wiring 18 as shown in FIG.

  In recent miniaturized devices, the length of the wiring connected to the gate is limited (antenna standard setting) as a countermeasure against PID, or when the wiring length exceeds the standard, a protective element for avoiding PID is connected. It corresponds.

In the invention disclosed in Japanese Patent Laid-Open No. 2003-31677, in a semiconductor device using a bulk wafer, a dummy pattern used for planarization is connected to a wiring to prevent element destruction due to an antenna effect.
JP 2003-31677 A

  The transistor formed on the SOI substrate is completely insulated from the Si support substrate by the buried oxide film. For this reason, in order to form a substrate diode for protection against charge injection via wiring, an extra process such as forming a PN junction under the buried oxide film and connecting with a contact occurs. Furthermore, it is necessary to consider the charge from the source and drain, which need not be considered in the bulk wafer. The charge injected from the source and drain accumulates in the body because there is no place for diffusion. As the charge in the body increases, the potential rises and electric field stress is applied to the thinnest gate oxide film, causing damage to the gate oxide film. Thus, when a transistor is formed on an SOI wafer, it is necessary to consider damage caused by charges injected from the source / drain as well as the gate.

In the invention disclosed in Japanese Patent Laid-Open No. 2003-133559, in a semiconductor device using an SOI substrate, an impurity diffusion layer connected to a wiring (source / drain: “/” is used to mean “or”). To prevent element destruction due to the antenna effect.
JP 2003-133559 A

  In any of the inventions disclosed in Japanese Patent Laid-Open Nos. 2003-31677 and 2003-133559, it is necessary to secure an area for countermeasures against the antenna effect in either case. The size itself increases.

  The present invention has been made in view of the above situation. When a transistor is formed on an SOI wafer, the influence of charge damage to the gate oxide film of the transistor can be reduced. An object is to provide a manufacturing method.

Another object of the present invention is to provide a structure and a manufacturing method of a semiconductor device which do not require a special area for antenna effect countermeasures and have few layout restrictions.

  In order to achieve the above object, a semiconductor device according to a first aspect of the present invention includes: a transistor formed on an SOI substrate; a wiring connected to a potential-fixed terminal of the transistor; And a dummy gate that does not function as a normal transistor. The dummy gate has a gate oxide film and a gate electrode layer, and the electrode layer is connected to the wiring.

  A method of manufacturing a semiconductor device according to a second aspect of the present invention includes: forming a gate oxide film at a plurality of locations on an SOI substrate; forming a gate electrode on each of the plurality of gate oxide films; Forming a source / drain region only in a region to be used as a transistor among the regions in which the gate oxide film and the gate electrode are formed, thereby distinguishing between a transistor gate and a dummy gate that does not function as a transistor; Forming a dummy gate contact region connected to the gate electrode of the dummy gate and a transistor contact region connected to a potential-fixed terminal of the transistor; and the dummy gate contact region and the transistor The dummy gate contact region and the A register contact region and a step of forming a wiring layer connected in common.

  According to the present invention, the influence of the charge damage to the gate oxide film of the SOI transistor is reduced by increasing the total area of the gate oxide film electrically connected through the wiring.

  Since the dummy gate can be formed by a process common to the gate of the transistor formed over the SOI substrate, the process is not complicated and the number of processes is not increased.

Since the dummy gate can be formed directly below the wiring along the wiring, it is less subject to chip layout restrictions. Usually, since a transistor is not formed under wiring such as a power supply or a ground, an increase in chip size can be avoided by arranging and forming a dummy gate using the space.

  Hereinafter, the best mode for carrying out the present invention will be described in detail using embodiments. FIG. 2 is a plan view showing the layout of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 4 is a plan view showing the structure of the semiconductor device according to the first embodiment. A semiconductor device (chip) 100 according to the present embodiment includes a plurality of circuit blocks 102 having a large number of transistors and performing various functions; a power supply wiring 104 and a ground wiring 106 arranged so as to surround the circuit block 102. And. Note that the power supply wiring and the ground wiring are not necessarily arranged near the outer periphery of the chip or so as to surround the circuit block.

  The power supply wiring 104 and the ground wiring 106 are connected to a power supply terminal (Vdd) 108 and a ground terminal (GND) 110, respectively. Dummy gates 114 and 116 having a gate oxide film are formed below (lower layer) the power supply wiring 104 for supplying power and the ground wiring 106 fixed to the ground potential. The dummy gates 114 and 116 are arranged along the power supply wiring 104 and the ground wiring 106, respectively. The dummy gates 114 and 116 can be partially formed under the wiring in addition to the case where the dummy gates 114 and 116 are formed over the entire area of the power supply wiring 104 and the ground wiring 106 in consideration of the circuit layout and the like.

  The widths of the dummy gates 114 and 116 are preferably larger than the widths of the power supply wiring 104 and the ground wiring 106 and the gate widths of the transistors Tr1 and Tr2. This is to increase the total area of the gate oxide film.

  As shown in FIG. 3, the dummy gate 114 and the power supply wiring 104 are connected via a contact 134a. Similarly, the dummy gate 116 and the ground wiring 106 are connected via a contact 134d. The transistor Tr1 used in the circuit has a source or a drain connected to the power supply wiring 104 through a contact 134b. Similarly, the source or drain of the transistor Tr2 is connected to the ground wiring 106 through the contact 134c. Since the potential during the circuit operation of the ground wiring 106 and the power supply wiring 104 does not change, the potential of the dummy gates 114 and 116 does not change due to the circuit operation.

  In general, since no transistor is disposed under the ground wiring 106 or the power supply wiring 104, the chip area does not increase due to the addition of dummy gates (114, 116). In other words, in this embodiment, there is no influence on circuit operation or area penalty due to the addition of the dummy gate. Since the dummy gates 114 and 116 are formed under the ground wiring 106 and the power supply wiring 104 and are connected via the contacts 134a and 134d, the transistor Tr2 connected to the ground wiring 106 and the transistor Tr1 connected to the power supply wiring 104 are connected. Can reduce the charge damage. That is, in this embodiment, dummy gates 114 and 116 having gate oxide films 114 a and 116 a are formed and connected under the ground wiring 106 and the power supply wiring 104 to be injected from the ground wiring 106 and the power supply wiring 104. The total area of the gate oxide film that is damaged by the charge can be increased, and the charge damage to the transistors Tr1 and Tr2 can be reduced.

When the semiconductor device shown in FIG. 3 is manufactured, first, an SOI (Silicon on Insulator) substrate including an Si support substrate 124, an oxide film buried layer (SiO ₂ layer) 126, and an Si layer 128 is prepared. Next, the active region and the insulating region are separated using a known element isolation method (STI method, LOCOS method, or the like). Next, gate insulating films (114a, 116a, Tr1a, Tr2a) are formed on the Si layer 128 by, for example, thermal oxidation. Next, a poly-Si film (not shown) for a gate electrode is formed on the gate insulating films (114a, 116a, Tr1a, Tr2a), and a gate pattern (resist pattern) is formed by lithography. Thereafter, using the gate pattern as a mask, the Poly-Si layer is removed by etching, and gate electrodes (114b, 116b, Tr1b, Tr2b) are formed. Next, impurity implantation and thermal diffusion are performed in the diffusion region of the Si layer 128 in the formation region of the transistors Tr1 and Tr2, thereby forming sources and drains (not shown), thereby completing the SOI transistors Tr1 and Tr2. Here, since the dummy gates 114 and 116 do not function as transistors, it is not necessary to form an impurity diffusion region.

  Thereafter, an interlayer insulating film 120 is deposited on the element isolation layer (not shown), the Si layer 128, and the gate electrodes (114b, 116b, Tr1b, Tr2b) by, for example, the CVD method. After the interlayer insulating film 120 is deposited, a resist (not shown) is applied on the interlayer insulating film 120, and contact holes are formed by, for example, a known dry etching method. The contact hole is formed at a position connecting the wiring 104, the dummy gate 114, and the transistor Tr1, and connecting the wiring 106, the dummy gate 116, and the transistor Tr2.

  Subsequently, a conductive material such as tungsten (W) is grown in the contact hole to form contacts (contact regions) 134a, 134b, 134c, and 134d. Excess conductive material such as tungsten (W) is removed by etch back or the like. Next, a metal film made of Al or an Al alloy is deposited on the interlayer insulating film 120 and the contacts 134a, 134b, 134c, and 134d by, for example, a sputtering method, and the metal film is patterned by a photolithographic technique, thereby The power supply wiring 104 and the ground wiring 106 are formed as one wiring layer. It is also possible to form second, third,... Wiring layers on the power supply wiring 104 and the ground wiring 106 through an interlayer insulating film.

  The amount of charge injected through the wiring increases as the wiring becomes longer due to the antenna effect. On the other hand, the larger the area of the gate oxide film, the more the charge is dispersed and the smaller the charge damage. For this reason, as in this embodiment, the dummy gates 114 and 116 are connected to increase the total gate oxide film area connected to the wirings 104 and 106, thereby reducing charge damage to the transistors Tr1 and Tr2 used in the circuit. be able to. In terms of circuit operation, an increase in the gate oxide film area results in an increase in parasitic capacitance. However, if the potential is fixed, the circuit operation is not affected. As in this embodiment, by connecting the dummy gates 114 and 116 via the wiring connected to the terminal whose potential is fixed by the circuit operation, the circuit operation to the transistors Tr1 and Tr2 formed on the SOI substrate is performed. The impact can be avoided.

  FIG. 5 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention. FIG. 6 is a plan view showing the structure of the semiconductor device according to the second embodiment. In this embodiment, dummy gates 214 and 216 having a gate oxide film are connected to wirings 204 and 206 connected to a terminal for fixing a potential among terminals of transistors Tr1 and Tr2 used as a circuit. The transistor Tr 1 whose gate potential is fixed in terms of circuit operation is connected to the dummy gate 214 via the wiring 204. In addition, the transistor Tr <b> 2 whose source or drain potential is fixed is connected to the dummy gate 216 through the wiring 206. Similar to the first embodiment described above, the dummy gates 214 and 216 only need to be provided with gate oxide films, and a structure such as a source or drain transistor is not necessary. Also, it is preferable to make the gate area of the dummy gate as large as possible.

  As shown in FIG. 5, the dummy gate 214 and the wiring 204 are connected via a contact 234a. Similarly, the dummy gate 216 and the wiring 206 are connected via a contact 234d. In the transistor Tr1 used in the circuit, the gate electrode Tr1b is connected to the wiring 204 through the contact 234b. On the other hand, the source or drain of the transistor Tr2 is connected to the wiring 206 through the contact 234c. Since the dummy gates 214 and 216 are connected to the fixed potential terminals of the transistors Tr1 and Tr2 through the wirings 204 and 206, the potentials of the dummy gates 214 and 216 are not changed by the circuit operation.

When the semiconductor device shown in FIG. 5 is manufactured, first, an SOI (Silicon on Insulator) substrate including an Si support substrate 224, an oxide film buried layer (SiO ₂ layer) 226, and an Si layer 228 is prepared. Next, the active region and the insulating region are separated using a known element isolation method (STI method, LOCOS method, or the like). Next, gate insulating films (214a, 216a, Tr1a, Tr2a) are formed on the Si layer 228 by, eg, thermal oxidation treatment. Next, a poly-Si film (not shown) for gate electrodes is formed on the gate insulating films (214a, 216a, Tr1a, Tr2a), and a gate pattern (resist pattern) is formed by lithography. Thereafter, using the gate pattern as a mask, the Poly-Si layer is removed by etching, and gate electrodes (214b, 216b, Tr1b, Tr2b) are formed. Next, impurity implantation and thermal diffusion are performed in the diffusion region of the Si layer 228 in the formation region of the transistors Tr1 and Tr2, thereby forming sources and drains (not shown) to complete the SOI transistors Tr1 and Tr2. Since the dummy gates 214 and 216 do not function as transistors, it is not necessary to form an impurity diffusion region.

  Thereafter, an interlayer insulating film 220 is deposited on the element isolation layer (not shown), the Si layer 228, and the gate electrodes (214b, 216b, Tr1b, Tr2b) by, for example, the CVD method. After the interlayer insulating film 220 is deposited, a resist (not shown) is applied on the interlayer insulating film 220, and contact holes (not shown) are formed by, for example, a known dry etching method. The contact hole is formed at a position connecting the wiring 204, the dummy gate 214, and the transistor Tr1, and connecting the wiring 206, the dummy gate 216, and the transistor Tr2.

  Subsequently, a conductive material such as tungsten (W) is grown in the contact hole to form contacts (contact regions) 234a, 234b, 234c, and 234d. Excess conductive material such as tungsten (W) is removed by etch back or the like. A metal film made of Al or an Al alloy is deposited on the interlayer insulating film 220 and the contacts 234a, 234b, 234c, and 234d by, for example, a sputtering method, and the metal film is patterned by a photolithography technique to thereby form the first wiring layer. As shown in FIG. It is also possible to form second, third,... Wiring layers on the wirings 204 and 206 via an interlayer insulating film.

  The amount of charge injected through the wiring increases as the wiring becomes longer due to the antenna effect. On the other hand, the larger the area of the gate oxide film, the more the charge is dispersed and the smaller the charge damage. As in the case of the first embodiment, the dummy gates 214 and 216 are connected to increase the total gate oxide film area connected to the wirings 204 and 206, thereby reducing charge damage to the transistors Tr1 and Tr2 used in the circuit. be able to. In terms of circuit operation, an increase in the gate oxide film area results in an increase in parasitic capacitance. However, if the potential is fixed, the circuit operation is not affected. As in this embodiment, the dummy gates 214 and 216 are connected to the transistors Tr1 and Tr2 formed on the SOI substrate by connecting the dummy gates 214 and 216 via the wirings 204 and 206 connected to the terminals whose potentials are fixed by the circuit operation. The influence of circuit operation can be avoided.

The present invention has been described with reference to the first and second embodiments. However, the present invention is not limited to these embodiments, and is appropriately designed within the scope of the technical idea described in the claims. It can be changed. In addition to the SOI wafer, any structure having a thin conductive layer sandwiched between insulators can be applied to a wafer having another structure. For example, an SOS (Silicon On Sapphire) wafer in which a Si layer is formed on a sapphire substrate can be expected to have the same or similar effect. Furthermore, the present invention can be applied to a structure in which the buried oxide film of the SOI wafer is removed.

FIG. 1 is a schematic cross-sectional view for explaining an antenna effect generated on an SOI substrate. FIG. 2 is a plan view showing the layout of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 4 is a plan view showing the structure of the semiconductor device according to the first embodiment. FIG. 5 is a sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention. FIG. 6 is a plan view showing the structure of the semiconductor device according to the second embodiment.

Explanation of symbols

100 semiconductor chip 102 circuit block 104 power supply wiring 106 ground wiring 114, 116, 214, 216 dummy gates 134a, 134b, 134c, 134d contacts 204, 206 wiring Tr1, Tr2 transistors

Claims (15)

A transistor formed on an SOI substrate;
A wiring connected to a terminal to which a potential is fixed among the terminals of the transistor;
A dummy gate formed on the SOI substrate and not functioning as a normal transistor;
The dummy gate has a gate oxide film and a gate electrode layer, and the electrode layer is connected to the wiring.   The semiconductor device according to claim 1, wherein the dummy gate is formed by a process common to a gate of a transistor formed on the SOI substrate.   The semiconductor device according to claim 1, wherein the terminal to which the potential is fixed is a gate electrode of the transistor.   The semiconductor device according to claim 1, wherein the terminal to which the potential is fixed is a source / drain electrode.   The semiconductor device according to claim 1, wherein the wiring is a power supply wiring.   The semiconductor device according to claim 1, wherein the wiring is a ground wiring.   The semiconductor device according to claim 1, wherein the wiring is a power supply wiring and a ground wiring.   8. The semiconductor device according to claim 1, wherein the dummy gate is disposed along the wiring under the wiring. In a method for manufacturing a semiconductor device formed on an SOI substrate,
Forming a gate oxide film at a plurality of locations on the SOI substrate;
Forming a gate electrode on each of the plurality of gate oxide films;
A step of forming a source / drain region only in a region used as a transistor of the region where the gate oxide film and the gate electrode are formed, thereby distinguishing between a transistor gate and a dummy gate that does not function as a transistor;
Forming a dummy gate contact region connected to the gate electrode of the dummy gate and a transistor contact region connected to a terminal at which the potential of the transistor is fixed;
Forming a wiring layer disposed on the dummy gate contact region and the transistor contact region and connecting the dummy gate contact region and the transistor contact region in common. A method for manufacturing a semiconductor device.   10. The manufacturing method according to claim 9, wherein the potential-fixed terminal of the transistor is a gate electrode of the transistor.   10. The manufacturing method according to claim 9, wherein the potential-fixed terminal of the transistor is a source / drain electrode of the transistor.   The manufacturing method according to claim 9, wherein the wiring is a power supply wiring.   The manufacturing method according to claim 9, wherein the wiring is a ground wiring.   The manufacturing method according to claim 9, wherein the wiring is a power supply wiring and a ground wiring.   15. The manufacturing method according to claim 9, wherein the dummy gate is disposed along the wiring under the wiring.

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