JP2005340461A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems such as operational instability caused by manufacturing variations, reduction of noise resistance and reduction of latch-up resistance. <P>SOLUTION: A basic cell 20 of the present semiconductor integrated circuit device is comprised of an n-type diffusion 30 for PMOS back gate, gate electrodes 31, 33, p-type transistor 32, n-type transistor 34 and p-type diffusion 35 for substrate. A plurality of such basic cells 20 are arrayed in directions of rows and columns, and a gate array is comprised of contact holes 22 and single-layer metals 23 so as to surround the periphery of a buffer circuit 21 with the basic cells 20. At the same time, an N well of the PMOS of the buffer circuit 21 and the basic cells 20 disposed in the shape of gate array surrounding the buffer circuit 21 is connected to a power supply potential, and a substrate of NMOS is connected to a ground potential similarly by the contact holes 22 and the single-layer metals 23. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to an embedded array type semiconductor integrated circuit device.

  As a semiconductor device layout development method, a soft macro layout unit composed of standard cells, a memory or an IO cell, and a hard macro layout unit such as a CPU are divided into blocks, and the blocks are connected to develop an LSI chip. There is a hierarchical layout development technique. FIG. 6 is an explanatory diagram showing an example of a hierarchical layout in the prior art. In the hierarchical layout as shown in FIG. 6, the hard macroblocks 1a, 1b, 1c, and 1d (I / O cells) and the soft macroblock 2 are connected by wiring, the timing of the signal line 4 is verified, and the timing is satisfied. A buffer circuit 3 is inserted for a path that does not exist, but this buffer circuit 3 is usually arranged in the soft macroblock 2.

  On the other hand, in order to avoid the influence of noise of other signals or to avoid complicated wiring, for example, a buffer circuit 3 for connecting the IO cell 1d and the hard macroblock 1c is provided as shown in FIG. There is a case where it is desired to arbitrarily place it outside the soft macroblock. Thus, an optimal buffer circuit insertion method for a critical path has been disclosed (see, for example, Patent Document 1).

  FIG. 7 is an explanatory diagram showing an example of a buffer circuit insertion method disclosed in the above-described prior art. In the buffer circuit insertion method shown in FIG. 7, for example, when the IO cell 1d and the hard macroblock 1c are connected, the delay parameter between 1d and 1c and the delay amount due to the wiring (wiring length L) between 1d and 1c And the wiring is divided into L and L-L1 so that the delay amount is optimum, and the buffer circuit 3 is inserted.

  However, in this method, as shown in FIG. 8, when the IO cell 1d and the hard macro block 1f are connected by the insertion buffer 3a, the insertion buffer 3a may be placed on a wide field in isolation. In this case, fluctuations in circuit characteristics due to layout-dependent manufacturing variations, reliability degradation due to noise, and the like are likely to occur.

  One of the causes of manufacturing variation is the loading effect. The loading effect is a phenomenon in which the finished width of the pattern varies depending on the density of the pattern. Description will be made by taking the transistors M1, M2, and M3 of FIG. 9 as an example. In FIG. 9, the well layer and the injection layer are not shown. Here, the layout dimensions of the gate lengths of the transistors M1, M2, and M3 are equally L. As shown in FIG. 9A, light diffraction occurs between the polysilicon gate of the transistor M1 and the polysilicon gate of the transistor M2, and between the polysilicon gate of the transistor M2 and the polysilicon gate of the transistor M3. As a result of the light diffraction, the resist applied on the top of the polysilicon gate to pattern the polysilicon gate becomes thinner than the layout dimension. This state is shown in FIG. In FIG. 9B, for the sake of explanation, the resist and the polysilicon gate are illustrated in different sizes, but finally the polysilicon gate has the same size as the resist.

  As shown in FIG. 9B, when the difference between the layout dimension and the finished dimension is a, the gate polysilicon of the transistor M2 receives light diffraction of both the transistor M1 and the gate polysilicon of the transistor M2. The gate length is L-2a. On the other hand, the transistor M1 receives the light diffraction of only the transistor M2, and the transistor M3 receives the light diffraction of only the transistor M2, so that the gate length is La. As a result, the gate polysilicon, which was the same at the time of layout, becomes a different size when finished, causing variations in characteristics.

  In order to solve the problem of manufacturing variations on these layouts, dummy patterns are inserted. FIG. 9C shows an example in which a dummy pattern is inserted. By inserting a dummy pattern around the transistor as shown in FIG. 9C, it becomes possible to make the diffraction of light uniform and make the finished dimensions of the gate polysilicon of the transistors M1, M2, and M3 the same.

  Inserting the dummy pattern also has the purpose of flattening the wafer surface. An example will be described with reference to FIG.

  In FIG. 10, illustration of a well layer, a diffusion layer, and the like is omitted. When the wafer surface is polished when the polysilicon gate 1 and the polysilicon gate 2 are spaced apart as shown in FIG. 10A, the thickness of the oxide film is set to D1 as a target for the thickness of the oxide film. In spite of the above, in a wide range, the portion where polysilicon does not exist is overpolished, and the oxide film thickness may become D2. Therefore, as shown in FIG. 10B, a dummy pattern is inserted in a region where the polysilicon gate does not exist in a wide range, and the over-polishing can be prevented to flatten the surface of the oxide film. 9 and 10 show the loading effect and planarization in polysilicon, the same can be said for metal wiring.

  As described above, a dummy pattern is inserted to prevent the loading effect and planarize the oxide film surface. When the dummy pattern is inserted in the periphery of the buffer circuit 3a that is arranged so as to be isolated on a wide field as shown in FIG. 8, manufacturing variations depending on the layout can be avoided. Has the disadvantage of being weak. In particular, in the case of FIG. 8, if an isolated buffer circuit 3a is arranged near the IO cell, operation is unstable due to noise entering the PAD from outside the LSI, reliability due to ESD (Electric Surge Device), latch-up, etc. It is easy to cause decline.

  Noise, ESD, and latch-up will be described with reference to FIG.

  First, the influence of noise will be described with reference to FIG.

  FIG. 11A is a diagram showing a state in which the dummy pattern 6 is installed between the signal line 7 and the signal line 8 and is insulated by an oxide film. In this case, the signal line 7 and the dummy pattern (dummy metal) 6 are connected by capacitive coupling, and the signal line 8 and the dummy metal 6 are coupled by capacitive coupling. At this time, since the dummy metal 6 is not connected to any signal line, power supply line, or ground line, when a large noise is applied to the signal line 7, the voltage of the capacitor 9 and the capacitor 10 fluctuates and the signal line 8 is moved. It will interfere as noise.

  Next, ESD will be described with reference to FIG. FIG. 11B shows a state where the noise source 11 is connected to the buffer circuit 12 and the buffer circuit 13 is not connected to the noise source 11 and the circuit 12. The noise source 11 corresponds to the PAD 5 shown in FIG. In such a state, when the noise level is high, the buffer circuit 12 is easily destroyed. However, the buffer circuit 13 that is insulated by the oxide film may also be destroyed depending on the magnitude and layout of the noise. This is because the insulating film cannot completely block noise, and the weak material portion of the circuit portion is destroyed.

  Next, latch-up will be described with reference to FIG. FIG. 11C shows a cross-sectional view of the CMOS process, and FIG. 11D shows an equivalent circuit thereof. As shown in the figure, in the CMOS process, there are structural parasitic elements, parasitic bipolar transistors Q1, Q2 and parasitic resistances R1, R2 in addition to the MOS transistors. Parasitic resistance R1 is a resistance component of the N well, and R2 is a resistance component of the P substrate.

  Here, when a large current flows through the N well, a voltage drop occurs in R1, and Q1 is turned on. When Q1 is turned on, a current also flows through R2 and Q2 is turned on, so that a thyristor is formed between the power supply grounds, so that a large current flows and the device is destroyed. Similarly, when a large current flows through the P substrate, a voltage drop occurs in R2, and Q2 is turned on. When Q2 is turned on, a current also flows through R1, and Q1 is turned on, so that a thyristor is formed between the power supply grounds, and a large current flows, leading to destruction of the device. In this way, latch-up occurs. The cause of current flowing through R1 and R2 is mainly noise flowing into the substrate.

  As a solution to the problem shown in FIG. 11A, there is a method of fixing the potential by connecting the dummy pattern 6 to a power source or a ground potential. Thereby, the signal line 8 is not affected by noise because the voltage of the capacitor 10 does not depend on the signal line 7. In this way, the signal line can be shielded by the dummy pattern. In FIG. 11B, by arranging dummy patterns around the buffer circuit 13, capacitive coupling is formed between the dummy patterns, and noise can be absorbed by these capacitors.

  As a countermeasure against the occurrence of latch-up shown in FIG. 11C, the resistance values of the parasitic resistances R1 and R2 can be lowered. For this purpose, in order to stabilize the local voltage of the N well and the P substrate, the area of the N diffusion on the N well connected to the power source and the area of the P diffusion on the P substrate connected to the ground potential are respectively set. The layout needs to be wide enough. In addition, some devices are structurally latch-up free and are listed as a latch-up countermeasure.

  One of the devices having a latch-up free structure is a deep N well structure of an NMOS transistor. FIG. 12 shows the structure of the deep N well. When the deep N well is used for the NMOS transistor as shown in FIG. 12, the NMOS transistor uses the P well as the substrate and is surrounded by the N well and the deep N well, so that a thyristor is not formed between the power supply grounds. For this reason, it becomes latch-up free.

  As a solution for removing the influence of noise shown in FIGS. 11A and 11B, there is a technique for reducing noise by making the dummy pattern 6 conductive to any one of a power supply potential, a ground potential, and another signal line potential. Yes (see Patent Document 2). FIG. 13 shows a conventional example of a dummy pattern insertion method disclosed in Patent Document 2.

In the conventional example shown in FIG. 13, dummy patterns 14 and 15 of polysilicon or metal layer are arbitrarily arranged in the vicinity of the signal wiring 18, and the dummy patterns 14 and 15 are connected to the power source, ground, Alternatively, the noise of the signal wiring 18 is reduced by connecting to another signal line potential and shielding the signal wiring 18. By adopting this conventional example around the buffer circuit 3a shown in FIG. 8, it becomes possible to stabilize the signal operation regardless of the buffer insertion location.
JP-A-9-17875 JP 2001-35853 A

  However, even if the conventional example shown in FIG. 13 is adopted in the periphery of the buffer circuit 3a shown in FIG. 8, the P substrate potential and the N well potential cannot be stabilized. Therefore, the latch-up shown in FIG. There is a disadvantage that the tolerance cannot be increased.

  Further, the conventional buffer circuit insertion method has the following problems. Depending on the position of the buffer circuit insertion, there may be a variation in circuit characteristics due to manufacturing variations and noise, resulting in reduced reliability.

  SUMMARY OF THE INVENTION In view of the above problems, the present invention has an object to provide a semiconductor integrated circuit device that realizes a configuration resistant to noise while taking measures against manufacturing variations when it is desired to arrange a buffer circuit on a wide field. It is said.

  The semiconductor integrated circuit device according to the present invention has the following features in order to solve the above-described problems.

  A semiconductor integrated circuit device according to the present invention includes a gate array in which a plurality of basic cells each having an N-channel MOS transistor and a P-channel MOS transistor are arranged in a row direction and a column direction, and each of the gate arrays includes the basic cell. The cell is composed of a cell constituting a base logic and a dummy cell, the cell constituting the logic is the buffer circuit, and the dummy cell is arranged around the buffer circuit.

  The semiconductor integrated circuit device according to the present invention is characterized in that a metal layer connected to a power supply potential and a ground potential is formed on the P-type MOS transistor and the N-type MOS transistor of the dummy cell.

  The semiconductor integrated circuit device according to the present invention is the same size as the basic cell and is constituted by P diffusion for connecting the P substrate to the ground potential and N diffusion for connecting the N well to the power supply potential. The guard ring cell is arranged around the buffer circuit.

  The semiconductor integrated circuit device according to the present invention is characterized in that a deep N well is formed in an N channel type MOS transistor included in the gate array.

  According to the present invention, it is possible to arrange a dummy cell constituting a gate array around the buffer circuit to eliminate manufacturing variation and to realize a stable operation of the buffer circuit.

  By implementing the gate array having the above configuration, the buffer circuit becomes unstable due to noise and the reliability is lowered, thereby realizing a highly reliable buffer circuit with noise countermeasures. Can do.

  According to the present invention, since the metal on the dummy cell can provide a shielding effect on the metal wiring of the buffer circuit, noise can be further reduced.

  Therefore, it is possible to effectively reduce the manufacturing variation due to the loading effect of the metal wiring of the buffer circuit and to reduce the noise due to the shielding effect against the metal wiring of the buffer circuit.

  According to the present invention, since the deep N well structure is formed around the buffer circuit, the dummy cell, the contact hole, and the metal wiring layer in this way, the P well which is the substrate of the NMOS transistor is separated from the P substrate. It becomes completely latch-up free and high reliability can be realized.

  Embodiments of a semiconductor integrated circuit device according to the present invention will be described below with reference to the accompanying drawings.

  In the figure, the same reference numerals indicate the same items.

(First embodiment)
FIG. 1A is a layout diagram of a gate array including a buffer circuit inserted when connecting a macroblock and another macroblock in the semiconductor integrated circuit device according to the first embodiment of the present invention. (B) is an equivalent circuit diagram corresponding to (a).

  The gate array includes a dummy cell 20, a buffer circuit 21, a contact hole 22, and a first layer metal 23 described below.

  Here, the dummy cell 20 and the buffer circuit 21 are composed of cells having a basic structure having an N-channel MOS transistor and a P-channel MOS transistor, and the cell having this basic structure is hereinafter referred to as a basic cell 19.

  The configuration of the wiring layer, the interlayer connection hole, the basic cell arrangement, and the like shown in FIG.

  The configuration of the gate array using the basic cell will be described below.

  FIG. 2A is an explanatory diagram illustrating a basic cell of the gate array. FIG. 2B is an equivalent circuit diagram of FIG. As shown in FIG. 2, the basic cell 19 includes a PMOS back gate N-type diffusion 30, gate electrodes 31 and 33, a P-type transistor 32, an N-type transistor 34, and a substrate P-type diffusion 35. As shown in FIG. 1, a plurality of basic cells 19 are arranged in the row direction and the column direction, and an array is configured so that the periphery of the buffer circuit 21 is surrounded by the basic cells 20 by the contact holes 22 and the first layer metal 23. In the array configured as described above, the contact hole 22 and the first layer metal 23 set the buffer N and the PMOS N well of the dummy 20 using the basic cells arranged in an array surrounding the buffer circuit 21 to the power supply potential. The NMOS substrate is connected to the ground potential.

  With the above-described configuration, a plurality of dummy cells 20 that are polysilicon gates having the same dimensions as the buffer circuit 21 are arranged so as to surround the buffer circuit 21, so that the buffer circuit 21 has no manufacturing variation due to the loading effect. Further, by connecting the substrates of the PMOS and NMOS of the dummy cell 20 to the power supply and the ground, the substrate potential around the buffer circuit 21 becomes more stable, and noise countermeasures mixed through the substrate, in particular, latch-up resistance is increased. Can do.

  Therefore, in FIG. 11, since polysilicon or a wiring layer is used as a dummy pattern, the substrate potential of PMOS and NMOS transistors cannot be sufficiently stabilized. On the other hand, the configuration shown in FIG. By using the basic cell 19 of the gate array as the dummy cell 20 and arranging a dummy pattern, it is possible to eliminate manufacturing variations and realize stable operation.

  Further, the configuration shown in FIG. 1 overcomes the disadvantage that the operation of the buffer circuit 3 as shown in FIG. 6 becomes unstable due to noise even if the buffer circuit 3 is inserted, and the reliability is lowered. High reliability by countermeasures can be realized.

(Second Embodiment)
FIG. 3 is a configuration diagram in which metal wiring is connected to the transistor of the dummy cell shown in FIG. 1 and connected to a power source and a ground line.

  In this embodiment, metal wiring is provided on the transistor of the dummy cell 20, and the PMOS N well is connected to the power supply potential and the NMOS substrate is connected to the ground potential.

  According to the configuration of the present embodiment, manufacturing variations due to the loading effect of the metal wiring of the buffer circuit 21 can be reduced as described in the first embodiment.

  Furthermore, since the metal on the dummy cell 20 can provide a shielding effect on the metal wiring of the buffer circuit 21, noise can be further reduced.

  11 is the same as the method of reducing noise by connecting the dummy metal shown in FIG. 11 to the power source and the ground line (see Patent Document 2), but the layout configuration method is different. In FIG. 10, the dummy metal is different in that it is not connected to the substrate.

  Therefore, in the present embodiment, it is possible to effectively reduce the manufacturing variation due to the loading effect of the metal wiring of the buffer circuit 21 and the noise due to the shielding effect against the metal wiring of the buffer circuit 21.

(Third embodiment)
FIG. 4A is a configuration diagram showing a configuration in which guard ring cells are arranged on the outer periphery of a gate array configured by the buffer circuit and dummy cells arranged in the second embodiment shown in FIG. Guard ring cells 1, 2 and 3 in FIG. 4A are guard ring cells 41, 41a and guard rings shown in FIG. 4B, guard ring cells 40, 40a and (c), respectively. This corresponds to the cells 42 and 42a.

  Also, 40, 41 and 42 and 40a, 41a and 42a shown in FIGS. 4B, 4C and 4D are respectively connected and arranged as shown in FIG.

  FIG. 4E is a configuration diagram showing a configuration in which the buffer circuit and the dummy cell are surrounded by guard ring cells.

  The guard ring cells 40, 41 and 42 and 40a, 41a and 42a in FIGS. 4B, 4C and 4D are P diffusion or N diffusion. In the case of N diffusion, an N well is formed in the periphery and connected to the power supply potential by a contact hole and a first layer metal. In the case of P diffusion, the contact hole and the first layer metal are similarly connected to the ground. In FIG. 4, the injection layer, the contact hole, and the metal layer are not shown.

  In the present embodiment, as described in the above-described embodiments, it is possible to effectively reduce the manufacturing variation due to the loading effect of the metal wiring of the buffer circuit 20 and to reduce the noise due to the shielding effect on the metal wiring of the buffer circuit 21. Can be done.

  Particularly, by arranging the guard ring cell so as to surround the buffer circuit 21 and the dummy cell 20, the substrate potential of the buffer circuit 21 and the buffer circuit 21 is stabilized, and noise from other circuit blocks such as an IO buffer and a macro is reduced. It becomes possible to do.

(Fourth embodiment)
FIG. 5 is a configuration diagram in which a deep N well is added in the third embodiment. Note that. In FIG. 5, contact holes and metal wiring layers are not shown.

  In this embodiment, a deep N well is formed around the buffer circuit 21, the dummy cell 20, the contact hole, and the metal wiring layer. This embodiment also has the same effect as described in the above embodiment. In particular, when a deep N-well structure is formed around the buffer circuit 21, the dummy cell 20, the contact hole, and the metal wiring layer in this way, the layout size increases by an amount depending on the design rule, but this is a substrate for an NMOS transistor. Since the P well is separated from the P substrate, it becomes completely latch-up free and high reliability can be realized.

  The semiconductor integrated circuit device according to the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

FIG. 3A is a layout diagram of a gate array of a buffer circuit in the semiconductor integrated circuit device according to the first embodiment of the present invention. (B) is an equivalent circuit diagram corresponding to (a). (A) is a figure explaining the basic cell of a gate array. (B) is an equivalent circuit diagram of a basic cell. FIG. 2 is a configuration diagram in which metal wiring is connected to a transistor of a basic cell also used as a dummy cell shown in FIG. 1 and connected to a power supply and a ground line. (A) is the block diagram which showed the structure which arrange | positions a guard ring cell in the outer periphery of the gate array which comprised the buffer circuit and the basic cell. (B) is a diagram corresponding to the guard ring cell 1. (C) is a diagram corresponding to the guard ring cell 2. (D) is a diagram corresponding to the guard ring cell 3. (E) is a block diagram which consists of a buffer circuit, a basic cell, and a guard ring cell. It is the block diagram which added the deep N well in 3rd Embodiment. It is explanatory drawing which shows an example of the hierarchical layout in a prior art. It is explanatory drawing which shows the example of the buffer insertion method currently disclosed by the prior art. The figure explaining an example of the layout which inserts a buffer between blocks. (A) is a block diagram of transistors M1, M2 and M3 for explaining the loading effect. FIG. 5B is a configuration diagram of transistors M1, M2, and M3 for explaining that the dimensions of the polysilicon gate differ due to the loading effect. (C) is a configuration diagram in which a planarization failure due to insertion of a dummy silicon gate is eliminated. (A) is a block diagram explaining the planarization defect by grinding | polishing. (B) is a configuration diagram in which a planarization failure due to insertion of a dummy silicon gate is eliminated. (A) is a figure which shows the state which installed the dummy pattern between the signal lines and was insulated with the oxide film. (C) is a cross-sectional view of a CMOS process including a parasitic transistor configuration. (D) is an equivalent circuit thereof. FIG. 6 is a dummy pattern layout diagram illustrating noise propagation, ESD, and latch-up. It is a block diagram explaining a deep N well structure.

Explanation of symbols

1a, 1b, 1c, 1d, 1e, 1f Hard macroblock 2 Soft macroblock 3, 21 Buffer circuit 3a Insertion buffer circuit 4 Signal wiring 5 PAD
6 Dummy metal 7, 8 Signal line 9, 10 Capacitance 11 Noise source 12, 13 Circuit 14, 15 Dummy pattern 16, 17 Connection 18 Signal wiring 19 Basic cell 20 Dummy cell 22 Contact hole 23 1 layer metal 30 N for PMOS back gate Type diffusion 31, 33 Gate electrode 32 P type transistor 34 N type transistor 35 P type diffusion 40 for substrate Guard ring cell 1
41 Guard ring cell 2
42 Guard ring cell 3

Claims (4)

A semiconductor integrated circuit device that performs connection between macroblocks by a buffer circuit on a semiconductor substrate,
A gate array in which a plurality of basic cells each having an N-channel MOS transistor and a P-channel MOS transistor are arranged in a row direction and a column direction;
Each of the gate arrays is composed of a cell and a dummy cell constituting a logic based on the basic cell, the cell constituting the logic is the buffer circuit, and the dummy cell is arranged around the buffer circuit. A semiconductor integrated circuit device.   2. The semiconductor integrated circuit device according to claim 1, wherein a metal layer connected to a power supply potential and a ground potential is formed on the P-type MOS transistor and the N-type MOS transistor of the dummy cell.   Guard ring cells each having the same size as the basic cell and configured by P diffusion for connecting the P substrate to the ground potential and N diffusion for connecting the N well to the power supply potential are provided in the buffer circuit and the buffer cell. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is arranged around a dummy cell. 4. The semiconductor integrated circuit device according to claim 1, wherein a deep N well is formed around an N channel type MOS transistor included in the gate array.

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