JP5511370B2 - Semiconductor device - Google Patents

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JP5511370B2
JP5511370B2 JP2009298742A JP2009298742A JP5511370B2 JP 5511370 B2 JP5511370 B2 JP 5511370B2 JP 2009298742 A JP2009298742 A JP 2009298742A JP 2009298742 A JP2009298742 A JP 2009298742A JP 5511370 B2 JP5511370 B2 JP 5511370B2
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博昭 鷹巣
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セイコーインスツル株式会社
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本発明は、素子分離構造にシャロートレンチ分離を有する半導体装置における、ESD保護素子関する。 The present invention, in a semiconductor device having a shallow trench isolation in the element isolation structure, for ESD protection element Seki.

MOS型トランジスタを有する半導体装置では、外部接続用のPADからの静電気による内部回路の破壊を防止するためのESD保護素子として、N型MOSトランジスタのゲート電位をグランド(Vss)に固定してオフ状態として設置する、いわゆるオフトランジスタが知られている。 In a semiconductor device having a MOS transistor as an ESD protection element for preventing breakdown of an internal circuit due to static electricity from the PAD for external connection, the off state by fixing the gate potential of the N-type MOS transistor to the ground (Vss) It is installed as a, so-called off-transistor is known.

オフトランジスタは、他ロジック回路などの内部回路を構成するMOS型トランジスタと異なり、一時に多量の静電気による電流を流しきる必要があるため、数百ミクロンレベルの大きなトランジスタ幅(W幅)にて設定されることが多い。 Off transistor, unlike a MOS transistor constituting an internal circuit such as other logic circuits, for temporary need as possible to flow a current due to a large amount of static electricity, set in large transistor width of several hundred microns level (W Width) it is often.

オフトランジスタのゲート電位はVssに固定され、オフ状態になっているものの、内部回路のN型MOSトランジスタと同様に1v以下の閾値を有するために、ある程度のサブスレッショルド電流が生じてしまう。 The gate potential of the off-transistor is fixed to Vss, but are turned off state, in order to have a N-type MOS transistor similarly to 1v following thresholds of the internal circuit, there arises a certain amount of sub-threshold current. 上述のように、オフトランジスタのW幅が大きいために動作待機時のオフリーク電流も大きくなり、オフトランジスタを搭載するIC全体の動作待機時の消費電流が増大してしまうという問題点があった。 As described above, the off-leak current during standby for W width off the transistor is greater increases, there is a problem that current consumption during standby of the entire IC mounting the off transistor is increased.

特にシャロートレンチ分離を素子分離構造に用いる半導体装置の場合、その構造自体や製造方法に由来してシャロートレンチ近接の領域で結晶欠陥層などのリーク電流を発生し易い領域を有するという問題点があり、オフトランジスタのオフリーク電流はさらに大きな問題点となる。 Especially in the case of a semiconductor device using a shallow trench isolation in the isolation structure, there is a problem of having a prone region generates a leakage current, such as a crystal defect layer at the area of ​​the shallow trench proximate derived from the structure itself and manufacturing methods , leak current of the off-transistor becomes more serious problem.

保護素子のリーク電流を低減するための改善策として、電源(Vdd)とグランド(Vss)の間に完全にオフするように複数のトランジスタを配置する例も提案されている(例えば、特許文献1参照。)。 As remedial measures for reducing the leakage current of the protection element, examples of completely placing a plurality of transistors to turn off during the power (Vdd) and ground (Vss) has been proposed (e.g., Patent Document 1 reference.).

特開2002−231886号公報 JP 2002-231886 JP

しかしながら、オフトランジスタのオフリーク電流を小さく抑えるためにW幅を小さくすると、十分な保護機能を果たせなくなってしまい。 However, reducing the width W in order to reduce the off-leakage current of the off transistor, it becomes not fulfill sufficient protection. また改善例のように電源(Vdd)とグランド(Vss)の間に完全にオフするように複数のトランジスタを配置する半導体装置においては、複数のトランジスタを有するため占有面積が大きく増大し、半導体装置のコストアップに繋がるなどの問題点があった。 In the semiconductor device arranging a plurality of transistors as completely off between power as improved example (Vdd) and ground (Vss), the area occupied by a large increase to have a plurality of transistors, the semiconductor device there was problems such as increase in cost of.

また、オフトランジスタを内部回路要素素子の保護素子として用いる場合には、諸パラメータの調整が複雑で、望ましい保護特性を得る設定を行うことが難しかった。 In the case of using the off-transistor as a protective element in the circuitry element, a complicated adjustment of parameters, it is difficult to set to obtain a desired protective properties.

上記問題点を解決するために、本発明は半導体装置を以下のように構成した。 In order to solve the above problems, the present invention has a semiconductor device as follows.

素子分離にシャロートレンチ構造を有するESD保護素子を有する半導体装置において、前記ESD保護素子は、中央に外部接続端子からの信号を受けるN型の領域が配置され、前記外部接続端子からの信号を受けるN型の領域の側面ならびに底面を囲むようにP型の領域が配置され、前記P型の領域の側面および底面を囲むように埋め込みN型の領域が配置され、 In a semiconductor device having ESD protection device having a shallow trench structure in the isolation, the ESD protection device includes a central N-type region which receives a signal from the external connection terminal is disposed, receiving the signal from the external connection terminal P-type region so as to surround the side surfaces and bottom surface of the N-type region is disposed buried N-type region so as to surround the sides and bottom of the P-type region is disposed,
前記埋め込みN型の領域の周囲にP型の基板端子領域が配置され、前記P型の基板端子領域の周囲にトレンチ分離領域が配置された半導体装置とした。 Wherein it is arranged P-type substrate terminal region around the buried N-type region, and a semiconductor device trench isolation region is disposed around the P-type substrate terminal region.

また、前記ESD保護素子の前記外部接続端子からの信号を受けるN型の領域と接する前記P型の領域は、前記外部接続端子からの信号を受けるN型の領域に前記半導体装置の電源電圧より高い電圧が印加された際に、前記外部接続端子からの信号を受けるN型の領域と、前記埋め込みN型の領域とがパンチスルーして導通する濃度および幅で形成されている半導体装置とした。 Further, the P-type region in which the contact with the N-type region which receives a signal from the external connection terminals of the ESD protection element, than the power supply voltage of the semiconductor device in the region of the N type which receives a signal from the external connection terminal when a high voltage is applied, the external connection of the N type which receives a signal from the terminal areas, wherein the buried N-type region is a semiconductor device which is formed by a concentration and width which conduct in punch-through .

また、前記埋め込みN型の領域のN型の不純物濃度は、前記P型の領域のP型の不純物濃度より高い半導体装置とした。 Further, N-type impurity concentration of the buried N-type region has a P-type semiconductor device with high than the impurity concentration of the P-type region.

また、前記P型の領域と、前記埋め込みN型の領域とは、共通の基板電位に固定されている半導体装置とした。 Further, said P-type region, and the buried N-type region, whereby a semiconductor device was fixed to the common substrate potential.

また、前記外部接続端子からの信号を受けるN型の領域、および前記P型の領域、および前記埋め込みN型の領域、および前記P型の基板端子領域は、同心円状に配置されている半導体装置とした。 The region of the N type which receives a signal from the external connection terminal, and the P-type region, and the buried N-type region, and the substrate terminal region of the P type semiconductor device which is arranged concentrically and the.

以上説明手段によって、オフリーク電流を小さく抑えつつ十分なESD保護機能を持たせたESD保護素子を占有面積を小さくしつつ簡便な方法で形成することができる。 Above the description means, it is possible to form the ESD protection device to have a sufficient ESD protection while keeping small off-leak current in a simple manner while reducing the occupied area.

本発明による半導体装置の、ESD保護素子の第1の実施例を示す模式的断面図である。 Of the semiconductor device according to the present invention, it is a schematic sectional view showing a first embodiment of the ESD protection device. 本発明による半導体装置の、ESD保護素子の第1の実施例を示す模式的平面図である。 Of the semiconductor device according to the present invention, it is a schematic plan view showing a first embodiment of the ESD protection device.

以下に本発明を実施するための形態について図面を参照して説明する。 It will be described with reference to the accompanying drawings embodiments of the present invention below.

図1は、本発明による半導体装置の、ESD保護素子の第1の実施例を示す模式的断面図である。 1, the semiconductor device according to the present invention, is a schematic sectional view showing a first embodiment of the ESD protection device.

P型のシリコン基板101上に埋め込みN型の領域202が形成され、埋め込みN型の領域202の内部側には、P型の領域801が形成されている。 P-type N-type region 202 buried in the silicon substrate 101 is formed of, on the inner side of the buried N-type region 202, P-type region 801 is formed. さらにP型の領域801の内部側には、外部接続端子からの信号を受けるN型の領域901が形成されている。 Furthermore the inner side of the P-type region 801, N-type region 901 which receives the signal from the external connection terminals are formed.

ここで、外部接続端子からの信号を受けるN型の領域901と接するP型の領域801は、外部接続端子からの信号を受けるN型の領域901に半導体装置の電源電圧以上の電圧が印加された際に、外部接続端子からの信号を受けるN型の領域901と、埋め込みN型の領域202とがパンチスルーして導通する幅および濃度で設けられている。 Here, P-type region 801 in contact with the N-type region 901 which receives the signal from the external connection terminal, a power supply voltage or more of the semiconductor device is applied to the N-type region 901 which receives the signal from the external connection terminal when the, the N-type region 901 which receives the signal from the external connection terminal, a buried N-type region 202 is provided with a width and concentration rendered conductive in punch-through.

また、埋め込みN型の領域202のN型の不純物濃度は、P型の領域801のP型の不純物濃度より高くなるように設定されている。 Further, N-type impurity concentration of the buried N-type region 202 is set to be higher than the impurity concentration of the P-type P-type region 801.

さらに、P型の領域801と、埋め込みN型の領域202とは、濃いP型の不純物濃度領域からなる基板端子領域201と同一の電位になるように電気的に接続固定されており、P型のシリコン基板101と同一の電位となっている。 Further, a P-type region 801, and the buried N-type region 202 is electrically connected and fixed to be the same potential as the substrate terminal region 201 formed of dark P-type impurity concentration region of, P-type It has the same potential as the silicon substrate 101.

また、基板端子領域201の周囲にはトレンチ分離領域301が形成され、他の素子との電気的な素子分離を行っているが、本発明の半導体装置のESD保護素子においては、トレンチ分離領域301は、基板端子領域201にのみ接する構造を取り、P型とN型の接合部には接することがない。 Also, around the substrate terminal region 201 is formed a trench isolation region 301, is performed electrical isolation from other elements in the ESD protection element of the semiconductor device of the present invention, the trench isolation region 301 takes a structure in contact only the substrate terminal region 201, has never in contact with the junction of the P-type and N-type.

トレンチ分離領域301の近傍には、結晶欠陥層などのリーク電流を発生し易い領域を有するという問題点があったが、本発明の半導体装置のESD保護素子においては、トレンチ分離領域301の近傍は、基板端子領域201のみであり、P型とN型の接合部などは配置されていないためリーク電流を発生することが無い。 In the vicinity of the trench isolation region 301, but has a problem of having a prone region generates a leakage current, such as a crystal defect layer in the ESD protection element of the semiconductor device of the present invention, the vicinity of the trench isolation region 301 , only the substrate terminal region 201, it is no such P-type and N-type junction generates a leakage current because it is not located.

P型の領域801におけるP型の不純物濃度と、P型の領域801の幅を適宜組み合わせて設定することにより、所望の印加電圧で外部接続端子からの信号を受けるN型の領域901と、埋め込みN型の領域202とを外部接続端子からの信号を受けるN型の領域901の側面および底面で同時にパンチスルーさせることが可能である。 And the impurity concentration of the P-type in P-type region 801, by setting appropriately combined width of the P-type region 801, an N-type region 901 which receives the signal from the external connection terminal at a desired applied voltage, embedded it is possible to punch through simultaneously and N-type region 202 at the side surface and the bottom surface of the N-type region 901 which receives the signal from the external connection terminal.

P型の領域801の幅をこのように設定することにより、通常の半導体装置の動作状態で電源電圧以下の電圧の信号が外部端子に印加されている状態では、外部接続端子からの信号を受けるN型の領域901と埋め込みN型の領域202とは逆導電型のP型の領域801で分離された状態となるため、ESD保護素子の埋め込みN型の領域202には外部端子に印加された信号(電圧)は伝達されず、ESD保護素子のオフリーク電流の発生を防止することができる。 By setting in this way the width of the P-type region 801, with the signal of the power supply voltage following voltage is applied to the external terminal in the operating state of the conventional semiconductor device, receiving a signal from the external connection terminal since the state of being separated by a P-type region 801 of the opposite conductivity type is N-type region 202 buried N-type region 901, the region 202 of the embedded N-type ESD protection element is applied to the external terminal signal (voltage) is not transmitted, it is possible to prevent the generation of off leak current of the ESD protection device.

一方、外部接続端子に大きな電圧(例えば静電気パルス)が印加された場合には、外部接続端子からの信号を受けるN型の領域901とESD保護素子の埋め込みN型の領域202とが外部接続端子からの信号を受けるN型の領域901の側面および底面で一気にパンチスルーして導通し、ESD保護素子として動作し、効率よく大きな静電気パルス電流を逃がすことができる。 On the other hand, when a large voltage to the external connection terminal (e.g., static electricity pulse) is applied, the external connection buried N-type region 202 and the external connection terminal of the N-type region 901 and the ESD protection device which receives a signal from the terminal signal is turned on in a stretch punch through the side and bottom of the N-type region 901 which receives the from, operate as an ESD protection element can be efficiently released to a large electrostatic pulse current.
これらの動作により、内部回路要素に対する保護機能がしっかりと発揮される。 By these operations, protection against internal circuit elements are firmly exhibited.

図2は、本発明による半導体装置の、ESD保護素子の第1の実施例を示す模式的平面図である。 2, the semiconductor device according to the present invention, is a schematic plan view showing a first embodiment of the ESD protection device.

中央から、外部接続端子からの信号を受けるN型の領域901、次に外部接続端子からの信号を受けるN型の領域801の周囲にP型の領域801、さらにP型の領域801の周囲に埋め込みN型の領域202、そして埋め込みN型の領域202の周囲にP型の基板端子領域201が同心円状に配置されている。 From the center, N-type region 901 which receives the signal from the external connection terminal, a P-type region 801 around the N-type region 801 next receives a signal from the external connection terminal, further around the P-type region 801 P-type substrate terminal region 201 around the buried N-type region 202 and the buried N-type region 202, are arranged concentrically. さらに、P型の基板端子領域201の外周は、トレンチ分離領域301で囲まれている。 Further, the outer periphery of the P-type substrate terminal region 201 is surrounded by a trench isolation region 301.

図2に示すような、同心円状の配置である保護素子は、角部や、局所的に偏った構造が無いため、外部からサージが印加されたさいにも偏った局所的な場所での動作が無く、素子全体に平均して動作することができ、大きな電流を効率よく、高い耐性をもって処理することが可能である。 As shown in FIG. 2, the protection element is a concentric arrangement, or corners, since there is no locally biased construction, operation at local places biased to again a surge from outside is applied without, can operate on average entire device, a large current efficiently, it is possible to treat with a high resistance.

図1および図2の実施例においては、簡便のため1つのESD保護素子を示しているが、多数の保護素子を設置しても構わない。 In the embodiment of FIG. 1 and FIG. 2 shows one of the ESD protection device for convenience, may be provided a number of protective elements.

101 P型のシリコン基板201 基板端子領域202 埋め込みN型の領域301 トレンチ分離領域801 P型の領域901 外部接続端子からの信号を受けるN型の領域 101 P-type N-type region where the silicon substrate 201 receives a signal from the area 901 external connection terminal region 301 trench isolation region 801 P-type substrate terminal region 202 buried N-type

Claims (4)

  1. 素子分離にシャロートレンチ構造を用いたESD保護素子を有する半導体装置であって、 A semiconductor device having ESD protection device using a shallow trench structure in the isolation,
    前記ESD保護素子は、P型シリコン基板の表面に設けられており、 The ESD protection element is provided on the surface of the P-type silicon substrate,
    中央に配置された外部接続端子からの信号を受けるN型の領域と、 And the N-type region which receives a signal from the external connection terminal arranged in the center,
    前記外部接続端子からの信号を受けるN型の領域の側面ならびに底面を囲むように配置されたP型の領域と、 And side as well as arranged P-type so as to surround the bottom surface area of ​​the region of the N type which receives a signal from the external connection terminal,
    前記P型の領域の側面および底面を囲むように配置された埋め込みN型の領域と、 And the N-type buried region is disposed so as to surround the sides and bottom of the P-type region,
    前記埋め込みN型の領域の周囲に配置されたP型の基板端子領域と、 And the P-type substrate terminal region disposed around the buried N-type region,
    前記P型の基板端子領域の周囲に配置されたトレンチ分離領域と、 A trench isolation region disposed around the P-type substrate terminal region,
    を有することを特徴とする半導体装置であって、 A semiconductor device characterized by having,
    前記ESD保護素子の前記外部接続端子からの信号を受けるN型の領域と接する前記P型の領域は、前記外部接続端子からの信号を受けるN型の領域に前記半導体装置の電源電圧より高い電圧が印加された際に、前記外部接続端子からの信号を受けるN型の領域と、前記埋め込みN型の領域とがパンチスルーして導通する濃度および幅で形成されている半導体装置。 Wherein said P-type region in which the contact with the N-type region which receives a signal from the external connection terminals of the ESD protection device, the power supply voltage higher than the voltage of the N-type the semiconductor device in the region of receiving signals from the external connection terminal There when applied, the external connection and the N-type region which receives the signal from the terminal, the buried N-type region and the semiconductor device is formed by a concentration and width which conduct in punch-through.
  2. 前記埋め込みN型の領域のN型の不純物濃度は、前記P型の領域のP型の不純物濃度より高い請求項1記載の半導体装置。 The buried N-type impurity concentration of the N-type region, said P-type region of the P-type semiconductor device of high claim 1 than the impurity concentration of.
  3. 前記P型の領域と、前記埋め込みN型の領域とは、共通の基板電位に固定されている請求項1記載の半導体装置。 The P-type and the region, and the buried N-type region, the semiconductor device according to claim 1, characterized in that fixed to a common substrate potential.
  4. 前記外部接続端子からの信号を受けるN型の領域、および前記P型の領域、および前記埋め込みN型の領域、および前記P型の基板端子領域は、同心円状に配置されている請求項1記載の半導体装置。 Region of the N type which receives a signal from the external connection terminal, and the P-type region, and the buried N-type region, and the substrate terminal region of the P-type, according to claim 1, characterized in that arranged concentrically semiconductor device.
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JP2010129893A (en) * 2008-11-28 2010-06-10 Sony Corp Semiconductor integrated circuit

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