JP5511370B2 - Semiconductor device - Google Patents

Description

  The present invention relates to an ESD protection element in a semiconductor device having a shallow trench isolation in an element isolation structure.

  In a semiconductor device having a MOS transistor, the gate potential of the N-type MOS transistor is fixed to the ground (Vss) as an ESD protection element for preventing destruction of the internal circuit due to static electricity from the external connection PAD. A so-called off-transistor installed as is known.

  The off-transistor, unlike the MOS transistors that make up internal circuits such as other logic circuits, needs to pass a large amount of static electricity at a time, so it is set with a large transistor width (W width) of several hundred microns. Often done.

  Although the gate potential of the off transistor is fixed to Vss and is in the off state, it has a threshold value of 1 v or less as with the N-type MOS transistor in the internal circuit, so that a certain amount of subthreshold current is generated. As described above, since the off-transistor has a large W width, the off-leakage current during operation standby increases, and there is a problem in that the current consumption during operation standby of the entire IC including the off-transistor increases.

  In particular, in the case of a semiconductor device using shallow trench isolation for an element isolation structure, there is a problem that a region that is prone to leak current, such as a crystal defect layer, is generated in the vicinity of the shallow trench due to the structure itself and the manufacturing method. The off-leakage current of the off-transistor becomes a further problem.

  As an improvement measure for reducing the leakage current of the protection element, an example in which a plurality of transistors are arranged so as to be completely turned off between a power supply (Vdd) and a ground (Vss) has been proposed (for example, Patent Document 1). reference.).

JP 2002-231886 A

  However, if the W width is reduced in order to keep the off-leakage current of the off transistor small, a sufficient protection function cannot be achieved. Further, in the semiconductor device in which a plurality of transistors are arranged so as to be completely turned off between the power supply (Vdd) and the ground (Vss) as in the improved example, the occupation area is greatly increased because the plurality of transistors are provided. There were problems such as leading to higher costs.

  Further, when an off transistor is used as a protection element for an internal circuit element, adjustment of various parameters is complicated, and it is difficult to perform setting for obtaining desired protection characteristics.

  In order to solve the above problems, the present invention is configured as follows.

In a semiconductor device having an ESD protection element having a shallow trench structure for element isolation, the ESD protection element has an N-type region for receiving a signal from an external connection terminal at the center, and receives a signal from the external connection terminal A P-type region is disposed so as to surround a side surface and a bottom surface of the N-type region, and an embedded N-type region is disposed so as to surround a side surface and a bottom surface of the P-type region;
A P-type substrate terminal region is arranged around the buried N-type region, and a trench isolation region is arranged around the P-type substrate terminal region.

  In addition, the P-type region that is in contact with the N-type region that receives a signal from the external connection terminal of the ESD protection element has an N-type region that receives a signal from the external connection terminal by a power supply voltage of the semiconductor device. The semiconductor device is formed with a concentration and a width in which an N-type region that receives a signal from the external connection terminal and the buried N-type region are punched through when a high voltage is applied. .

  Further, the semiconductor device is configured such that the N-type impurity concentration in the buried N-type region is higher than the P-type impurity concentration in the P-type region.

  The P-type region and the buried N-type region are a semiconductor device fixed at a common substrate potential.

  A semiconductor device in which an N-type region that receives a signal from the external connection terminal, the P-type region, the embedded N-type region, and the P-type substrate terminal region are arranged concentrically. It was.

  By the means described above, an ESD protection element having a sufficient ESD protection function while suppressing off-leakage current can be formed by a simple method while reducing the occupied area.

It is a typical sectional view showing the 1st example of an ESD protection element of a semiconductor device by the present invention. 1 is a schematic plan view showing a first embodiment of an ESD protection element of a semiconductor device according to the present invention.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated with reference to drawings.

  FIG. 1 is a schematic sectional view showing a first embodiment of an ESD protection element of a semiconductor device according to the present invention.

  A buried N-type region 202 is formed on the P-type silicon substrate 101, and a P-type region 801 is formed inside the buried N-type region 202. Further, an N-type region 901 that receives a signal from the external connection terminal is formed inside the P-type region 801.

  Here, in the P-type region 801 that is in contact with the N-type region 901 that receives a signal from the external connection terminal, a voltage higher than the power supply voltage of the semiconductor device is applied to the N-type region 901 that receives the signal from the external connection terminal. In this case, the N-type region 901 that receives a signal from the external connection terminal and the buried N-type region 202 are provided with a width and concentration that allow punch-through and conduction.

  Further, the N-type impurity concentration of the buried N-type region 202 is set to be higher than the P-type impurity concentration of the P-type region 801.

  Further, the P-type region 801 and the buried N-type region 202 are electrically connected and fixed so as to have the same potential as that of the substrate terminal region 201 formed of a dense P-type impurity concentration region. The same potential as that of the silicon substrate 101 of FIG.

  In addition, a trench isolation region 301 is formed around the substrate terminal region 201 to perform electrical element isolation from other elements. In the ESD protection element of the semiconductor device of the present invention, the trench isolation region 301 is provided. Takes a structure that contacts only the substrate terminal region 201 and does not contact the P-type and N-type joints.

  In the vicinity of the trench isolation region 301, there is a problem that a region such as a crystal defect layer is likely to generate a leakage current. However, in the ESD protection element of the semiconductor device of the present invention, the vicinity of the trench isolation region 301 is Since only the substrate terminal region 201 is provided and no P-type and N-type junctions are disposed, no leakage current is generated.

  By appropriately combining the P-type impurity concentration in the P-type region 801 and the width of the P-type region 801, an N-type region 901 that receives a signal from the external connection terminal at a desired applied voltage, and an embedded region The N-type region 202 can be punched through at the same time on the side and bottom surfaces of the N-type region 901 that receives a signal from the external connection terminal.

  By setting the width of the P-type region 801 in this manner, the signal from the external connection terminal is received in a state where a signal having a voltage equal to or lower than the power supply voltage is applied to the external terminal in the normal semiconductor device operation state. Since the N-type region 901 and the buried N-type region 202 are separated from each other by the reverse conductivity type P-type region 801, the buried N-type region 202 of the ESD protection element is applied to an external terminal. A signal (voltage) is not transmitted, and the occurrence of off-leakage current of the ESD protection element can be prevented.

On the other hand, when a large voltage (for example, electrostatic pulse) is applied to the external connection terminal, the N type region 901 that receives a signal from the external connection terminal and the embedded N type region 202 of the ESD protection element are connected to the external connection terminal. The N-type region 901 that receives a signal from the N-type region 901 punches through and conducts at once, operates as an ESD protection element, and can efficiently release a large electrostatic pulse current.
By these operations, the protection function for the internal circuit elements is firmly exhibited.

  FIG. 2 is a schematic plan view showing a first embodiment of the ESD protection element of the semiconductor device according to the present invention.

  From the center, an N-type region 901 that receives a signal from the external connection terminal, then a P-type region 801 around the N-type region 801 that receives a signal from the external connection terminal, and further around the P-type region 801 A buried N-type region 202 and a P-type substrate terminal region 201 are arranged concentrically around the buried N-type region 202. Further, the outer periphery of the P-type substrate terminal region 201 is surrounded by a trench isolation region 301.

  As shown in FIG. 2, the protective element having a concentric arrangement does not have a corner portion or a locally biased structure, and therefore operates in a localized location even when a surge is applied from the outside. Therefore, it is possible to operate on the whole element on average, and a large current can be processed efficiently and with high tolerance.

  In the embodiment of FIGS. 1 and 2, one ESD protection element is shown for the sake of simplicity, but a number of protection elements may be installed.

101 P-type silicon substrate 201 Substrate terminal region 202 Embedded N-type region 301 Trench isolation region 801 P-type region 901 N-type region for receiving signals from external connection terminals

Claims (4)

A semiconductor device having an ESD protection element using a shallow trench structure for element isolation,
The ESD protection element is provided on the surface of a P-type silicon substrate,
An N-type region for receiving a signal from an external connection terminal disposed in the center;
A P-type region disposed so as to surround a side surface and a bottom surface of an N-type region that receives a signal from the external connection terminal;
An embedded N-type region disposed so as to surround a side surface and a bottom surface of the P-type region;
A P-type substrate terminal region disposed around the embedded N-type region;
A trench isolation region disposed around the P-type substrate terminal region;
A semiconductor device comprising :
The P-type region that is in contact with the N-type region that receives a signal from the external connection terminal of the ESD protection element has a voltage higher than the power supply voltage of the semiconductor device in the N-type region that receives the signal from the external connection terminal. The semiconductor device is formed with a concentration and a width such that an N-type region that receives a signal from the external connection terminal and the embedded N-type region punch through and become conductive when a voltage is applied.   The semiconductor device according to claim 1, wherein an N-type impurity concentration in the buried N-type region is higher than a P-type impurity concentration in the P-type region.   The semiconductor device according to claim 1, wherein the P-type region and the buried N-type region are fixed to a common substrate potential.   2. The N-type region that receives a signal from the external connection terminal, the P-type region, the embedded N-type region, and the P-type substrate terminal region are arranged concentrically. Semiconductor device.

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