TWI536534B - Electrostatic discharge protection device - Google Patents

Description

Electrostatic discharge protection element

The present invention relates to an electrostatic discharge (ESD) protection element, and more particularly to an electrostatic discharge protection element that provides a conduction path of an electrostatic discharge current in a vertical direction.

The occurrence of electrostatic discharge (ESD) is not conducive to the performance reliability of semiconductor products, especially for CMOS transistors with dimensions toward miniaturization. In the production technology of deep-submicron CMOS transistors, as the gate thickness becomes thinner, the breakdown voltage also becomes smaller. Therefore, an effective electrostatic discharge protection circuit must be provided at each input terminal to avoid An overstress voltage is applied to the gate to destroy the internal circuit. Generally, the tolerance requirement for the ESD protection circuit is usually greater than 2000 volts (volt, V) in the human-body-model (HBM), and in the mechanical model (MM). Usually needs to be greater than 200V.

Conventionally, a method of avoiding electrostatic breakdown caused by electrostatic pulses is to use a metal oxide semiconductor field effect transistor (MOSFET) as an electrostatic discharge protection circuit element. Please refer to FIG. 1 , which illustrates a schematic diagram of an electrostatic discharge protection circuit for protecting an internal circuit. As shown in FIG. 1, the ESD protection circuit 10 is connected to an output/input pad 12 and an internal circuit 14, and the output/input pad 12 is It is used as a transmission medium for the electronic signals of the internal circuit 14 and its outside. When an electrostatic current signal 11 is introduced from the output/input pad 12, the ESD protection circuit 10 can protect the internal circuit 14 from burning due to excessive electrostatic current. In general, the ESD protection circuit 10 includes at least one P-type metal-oxide semiconductor (PMOS) transistor 16 and an N-type metal-oxide semiconductor (NMOS) device. a crystal 18 in which a drain D of the PMOS transistor 16 and a drain D of the NMOS transistor 18 are connected to each other and connected to the internal circuit 14 and the output/input pad 12 by a wire 20, and the PMOS transistor The source S of 16 is simultaneously connected to the gate G of the PMOS transistor 16 and a power input terminal VDD, and the source S of the NMOS transistor 18 is simultaneously connected to the gate G of the NMOS transistor 18. And a ground terminal VSS. In addition, a first parasitic diode 22 is formed at the PMOS transistor 16, and a second parasitic diode 24 is also formed at the NMOS transistor 18.

When static electricity is generated by the static electricity discharge protection circuit 10 through the power input terminal VDD, the output/input pad 12, and the ground terminal VSS, the generated electrostatic current is turned on by the first parasitic diode 22 . The second parasitic diode 24 is turned on, the snapback breakdown phenomenon generated by the PMOS transistor 16 or the snapback phenomenon generated by the NMOS transistor 18 is quickly guided. For example, when an external object with static electricity contacts the power input terminal VDD and the output/input pad 12 at the same time so that the potential of the output/input pad 12 is higher than the potential of the power input terminal VDD, the first parasitic diode 22 is turned on. To quickly direct the static electricity; for example, when an external object with static electricity contacts the output/input pad 12 and the ground terminal VSS at the same time, the output/input pad 12 is electrically charged. When the bit is higher than the ground potential VSS, the NMOS transistor 18 will suddenly collapse and quickly direct the static electricity.

Since the depth of the inversion layer of the surface channel of the NMOS transistor 18 is extremely shallow, when a large electrostatic discharge current is used, a typical example is 1.33 ampere (Amp) (in the state of human body discharge mode 2 kV), flowing through When the surface channel of the NMOS transistor 18 is used, the NMOS transistor 18 is often burned, so that the ESD protection circuit 10 cannot function normally. Even if the component size of the NMOS transistor 18 is increased, such a situation cannot be effectively prevented. Therefore, how to improve the structure of the electrostatic discharge protection component in the electrostatic discharge protection circuit is an object to be improved by the related art.

One of the objects of the present invention is to provide an electrostatic discharge (ESD) protection element to improve the tolerance of the electrostatic discharge protection element.

A preferred embodiment of the present invention provides an electrostatic discharge protection element. The ESD protection component includes a first conductivity type semiconductor substrate, a first conductivity type well, a second conductivity type buried layer, and a second conductivity type well. The first conductive type well is disposed in the first conductive type semiconductor substrate, and the second conductive type buried layer is disposed in the first conductive type semiconductor substrate below the first conductive type well. The second conductive type well divides the first conductive type well into a first well area and a second well area, and the second conductive type well contacts the second conductive type buried layer, so that the second conductive type buried layer and the second conductive type The two conductive wells are commonly used to isolate the first well zone from the second well zone.

The invention provides that the second well region is below the drain doping region, so that the electrostatic discharge current can be electrically connected in the vertical direction via the drain doping region, the second well region and the second conductive type buried layer, that is, The path of the electrostatic discharge current can be increased to prevent the electrostatic discharge current from being directly discharged in the horizontal direction through the channel region to the source doping region, thereby preventing the electrostatic discharge protection component from being damaged due to excessive heat caused by the electrostatic discharge current, so as to improve the electrostatic discharge. The tolerance of the protective element. In addition, in the present invention, the second well region is formed by separating the original first conductivity type well by the second conductivity type well, so that it is not necessary to use an additional mask to form the second well region, which also contributes to saving production. cost.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

The invention provides an electrostatic discharge (ESD) protection component which can be disposed between the signal input/output terminal and the internal circuit for guiding the electrostatic discharge current to protect the internal circuit. Please refer to Figure 2. 2 is a schematic view of an electrostatic discharge protection component in accordance with a preferred embodiment of the present invention. As shown in FIG. 2 , the ESD protection device 100 includes a first conductive semiconductor substrate 102 , a second conductive buried layer 104 , at least one first conductive well 106 , at least one second conductive well 108 , A gate structure 110, an isolation structure 112, a first doped region 114, a second doped region 116, and a third doped region 118. The first conductivity type is one of the N type or the P type, and the second conductivity type is the other of the P type or the N type. In this embodiment, the first conductivity type is a P type, The second conductivity type is N-type, but is not limited thereto. The first conductive semiconductor substrate 102 may comprise a substrate composed of a gallium arsenide, a blanket insulating (SOI) layer, an epitaxial layer, a germanium layer or other semiconductor substrate material. The second conductive type buried layer 104 is disposed in the first conductive type semiconductor substrate 102 for isolation, for example, preventing current signals from being transmitted downward to the first conductive type semiconductor substrate 102 to cause leakage.

The first conductive type well 106 is disposed in the first conductive type semiconductor substrate 102, wherein the first conductive type well 106 is located on the second conductive type buried layer 104 and is adjacent to the second conductive type buried layer 104, that is, The second conductive type buried layer 104 is disposed in the first conductive type semiconductor substrate 102 below the first conductive type well 106.

The second conductive well 108 can divide the first conductive well 106 into a second well region 122 and at least one first well region 120. In the present embodiment, one of the second conductive wells 108 has a depth substantially equal to one of the first conductive wells 106, and one of the first well regions 120 has a dopant concentration and a type substantially equal to the second well region. 122 one of the dopant concentration, type. The second conductive well 108 can divide the first conductive well 106 into a plurality of sub well regions having the same depth, that is, one depth of each sub well region, that is, the depth of the first well region 120 and the second The depth of the well region 122 is substantially equal to the depth of the first conductivity type well 106. It is noted that the second conductivity type well 108 is located between the first well region 120 and the second well region 122, and the second conductivity type buried layer 104 is located directly below the second well region 122 and extends laterally to the portion. Below the second conductivity type well 108, the second conductivity type buried layer 104 simultaneously completely contacts the second well region 122 and a portion of the second conductivity type well 108, that is, the second conductivity type buried layer 104. Adjacent to the second well area 122 and the same The second conductive type well 108 is disposed, and the second conductive type buried layer 104 is limited to not adjacent to the first well region 120 to avoid affecting the breakdown voltage of the electrostatic discharge protection element 100 itself. In the present embodiment, the second conductive well 108 is an annular well region to surround the second well region 122. The cross-sectional width of one of the second well regions 122 is substantially smaller than that of the second conductive buried layer 104. Width, and the second well region 122 is completely above the second conductive type buried layer 104, not directly contacting the first conductive type semiconductor substrate 102, and therefore, a portion of the first conductive type well 106 surrounded by the second conductive type well 108, That is, the second well region 122 may be co-coated with the second conductive type buried layer 104 and the second conductive type well 108, whereby the second conductive type buried layer 104 and the second conductive type well 108 may be common It is used to isolate the first well region 120 from the second well region 122.

The gate structure 110 can include a gate dielectric layer 124, a gate electrode 126, and a sidewall spacer 128 disposed on the first conductive semiconductor substrate 102, and the gate structure 110 is not completely overlapped with the second conductive type buried Layer 104. The material of the gate structure 110 is well known to those skilled in the art, and may include conductors such as polysilicon, metallization or metal, and thus will not be described herein. A first doping region 114 having a second conductivity type is disposed in the first well region 120, and a second doping region 116 having a second conductivity type is disposed in the second well region 122, that is, the first doping region The region 114 and the second doping region 116 are respectively located on both sides of the gate structure 110. The isolation structure 112 is composed of a dielectric material, and may include a field oxide layer or a shallow trench isolation (STI), etc., disposed between the gate structure 110 and the second doping region 116. In the example, the isolation structure 112 preferably surrounds the second doped region 116. The isolation structure 112 may cover the boundary between the first well region 120 and the second conductive well 108, and the isolation structure 112 may increase the first doping region 114. The spacing from the second doped region 116 helps to moderate the high voltage between the first doped region 114 and the second doped region 116. In addition, the gate structure 110 partially overlaps the isolation structure 112 and is located on the isolation structure 112. Therefore, the gate structure 110 does not directly contact the second conductive well 108, the second well region 122, and the second doping region 116. In this embodiment, the first doping region 114 includes a source, the second doping region 116 includes a drain, the gate structure 110 includes a gate, and the isolation structure 110 includes a field oxide layer to jointly form a semiconductor. The component 129 is, for example, a high voltage NMOS transistor, but is not limited thereto.

The third doping region 118 is disposed in the first well region 120 of the first conductive well 106 and is located on a side of the gate structure 110 relative to the second doping region 116, that is, when the second doping region 116 is located on one side of the gate structure 110, and the third doping region 118 and the first doping region 114 are both located on the other side of the gate structure 110. In addition, the third doped region 118 has the same first conductivity type as the first conductive well 106 and can be used to regulate the potential of the first conductive well 106.

Please refer to Figures 3 to 6. 3 to 6 are schematic views showing a method of fabricating an electrostatic discharge protection element according to a preferred embodiment of the present invention. The method of forming the electrostatic discharge protection element may include the following steps. As shown in FIG. 3, first, a first conductive type semiconductor substrate 102 is provided, and an ion implantation process is performed to form a second conductive type buried layer 104 in the first conductive type semiconductor substrate 102. In this embodiment, the first conductivity type is a P type, and the second conductivity type is an N type, but is not limited thereto. The first conductive semiconductor substrate 102 may comprise, for example, a P-type substrate composed of gallium arsenide, a germanium-clad insulating layer, an epitaxial layer, a germanium layer or other semiconductor substrate material, and the second conductive type buried layer 104 may be Including one N type buried layer. Then, an epitaxial layer (not shown) may be further formed to thicken the first conductive semiconductor substrate 102, for example, a selective epitaxial growth (SEG) process to form an epitaxial layer on the second conductive Above the buried layer 104. Subsequently, an ion implantation process is performed to form the first conductive well 106 in the epitaxial layer, that is, the first conductive type semiconductor in which the first conductive well 106 is formed on the second conductive buried layer 104. In the substrate 102, the first conductivity type well 106 includes a P-type well.

Then, as shown in FIG. 4, an ion implantation process is performed to form at least one second conductivity type well 108 in the first conductivity type well 106 to separate the first conductivity type well 106 into at least one first well region. 120 and second well zone 122. The number of first conductive wells 106 and the number of second conductive wells 108, that is, the number of first well regions 120 formed and the number of second well regions 122 formed, are not limited thereto. In the present embodiment, the second conductive well 108 includes an annular well region, wherein the second conductive well 108 surrounds the second well region 122, and the depth of the second conductive well 108 is preferably substantially equal to the first The depth of the conductive well 106 is directly in contact with the second conductive type buried layer 104, for example, forming an N-type well (second conductive type well 108) in the P-type well (first conductive type well 106) to make the P-type well Divided into a first P-type well area (first well area 120) and a second P-type well area (second well area 122), that is, without additional patterned masks, simultaneously A plurality of sub-well zones are formed, and the N-type well, the first P-type well zone and the second P-type well zone have the same depth. It should be noted that the position and the occupied area of the second conductive well 108 may affect the distribution of the first well region 120 and the second well region 122. When the cross-sectional width W1 of the second conductive well 108 increases, the first The distance between the well area 120 and the second well area 122 is also followed. The effect of increasing the second conductive well 108 to isolate the first well region 120 from the second well region 122 is better. However, under the condition that the size of the subsequently formed electrostatic discharge protection element and the area occupied by the first well region 120 are fixed, the increase in the cross-sectional width W1 will reduce the area of the second well region 122 and reduce the subsequent formation of static electricity. The ability of the protective element; conversely, when the cross-sectional width W1 of the second conductive well 108 is reduced, that is, the occupied area of the second conductive well 108 is reduced, the distance between the first well region 120 and the second well region 122 is also The reduction will be detrimental to the isolation effect of the first well region 120 and the second well region 122. However, under the condition that the size of the subsequently formed electrostatic discharge protection element and the area occupied by the first well region 120 are fixed, the reduction of the cross-sectional width W1 will increase the area of the second well region 122, which may increase the electrostatic protection formed subsequently. The ability of the component. The second conductive well 108 is preferably located between the subsequently formed gate structure and the subsequently formed second doped region. When the cross-sectional width W1 of the second conductive well 108 is less than a certain value, the electrostatic discharge may be caused. The current directly passes through the second conductive well 108 in the horizontal direction, and cannot form a conduction path that passes through the second well region 122 in the vertical direction to release the electrostatic discharge current, wherein the constant value and the subsequently formed electrostatic discharge protection element Structure related. The position and area occupied by the second conductive well 108 can be adjusted according to process requirements.

Next, as shown in FIG. 5, at least one isolation structure 112 is formed, and the gate structure 110 is formed on the first conductive type semiconductor substrate 102, and the gate structure 110 partially overlaps the isolation structure 112. The isolation structure 112 is comprised of a dielectric material, including a field oxide layer or shallow trench isolation. The isolation structure 112 preferably covers the boundary between the first well region 120 and the second conductive well 108 and the junction between the second well region 122 and the second conductive well 108, but is not limited thereto. The gate structure 110 can include a gate dielectric layer 124 and a gate electrode The pole 126 and the side wall 128. The process of isolation structure 112 and gate structure 110 is well known to those skilled in the art and will not be described herein.

As shown in FIG. 6, an ion implantation process is performed using the gate structure 110, the isolation structure 112, and a patterned photoresist (not shown) as a mask to form a first doping having a second conductivity type. The region 114 is in the first well region 120 and the second doping region 116 having the second conductivity type is in the second well region 122, wherein the first doping region 114 and the second doping region 116 are respectively located in the gate structure 110 The two sides of the second well region 122 are preferably located between the second doped region 116 and the second conductive well 108 to isolate the second doped region 116 and the second conductive well having the same conductivity type. 108. In addition, a lightly doped region (not shown) may also be selectively formed in the first well region 120 between the gate dielectric layer 124 and the first doped region 114. In addition, in the present embodiment, the second conductive type buried layer 104, the second conductive type well 108, the first doping region 114, and the second doping region 116 having the same conductivity type have a doping concentration from rich to The first doping region 114 and the second doping region 116 (the doping concentration of the first doping region 114 is substantially equal to the doping concentration of the second doping region 116), and the second conductivity type is buried. Layer 104, and second conductivity type well 108. The first well region 120 and the second well region 122 are separated by the first conductive well 106. Therefore, the doping concentration and the dopant type of the first well region 120 are substantially equal to the second well region 122. Mixed concentration and dopant type. An ion implantation process is further performed to form a third doping region 118 having a first conductivity type in the first well region 120, and the third doping region 118 is located in the gate structure 110 opposite to the second doping region. One side of 116, wherein the doping concentration of the third doping region 118 is preferably substantially greater than the doping concentration of the first conductive well 106. The order in which the first doping region 114, the second doping region 116, and the third doping region 118 are formed is not described Limited. So far, the structure of the electrostatic discharge protection element 100 is completed.

Next, a conduction path of the electrostatic discharge current in the electrostatic discharge protection element 100 will be described. Referring to FIG. 2 again, in the embodiment, the first doping region 114, the third doping region 118, and the gate structure 110 are electrically connected to a first power supply node 130, and the second doping region 116 is A second power supply node 132 is electrically connected, wherein the first power supply node 130 includes a low voltage power supply node, and the second power supply node 132 includes a high voltage power supply node. When the second power supply node 132 provides a high voltage signal to turn on the semiconductor device 129 when an electrostatic discharge event occurs, an electrostatic discharge current will flow from the second doped region (ie, the drain) 116. At this time, the isolation structure 112 can be Preventing the electrostatic discharge current from flowing directly through the gate dielectric layer 124 to the gate electrode 126 causes the semiconductor device 129 to fail. In addition, it is noted that the second well region 122 of the present invention simultaneously abuts the second doped region 116 and The second conductive type buried layer 104, wherein the second well region 122 is completely above the second conductive type buried layer 104, and is surrounded by the second conductive type well 108. Therefore, the second well region 122 is disposed to enable electrostatic discharge The current flows along one of the vertical path R1 in the second well region 122, one of the second conductive type buried layer 104 and one of the first conductive type semiconductor substrates 102, and one along the side wall R3 of the second conductive well 108. To the gate structure 110 to alleviate the electrostatic discharge current, and then the electrostatic discharge current is again led through the first doped region (ie, the source) 114 through a path R4 of the channel region below the gate structure 110. Briefly, the path of the ESD current conduction of the present invention comprises a drain-second well region-second conductivity type buried layer-first well region-channel region-source, and the electrostatic discharge protection component of the prior art The arrangement of the second well region 122 of the present invention increases the electrostatic discharge current in the vertical direction compared to the path having only the horizontal conduction (ie, the drain-first conductivity type well-channel region-source). The conduction path of the direction prevents the electrostatic discharge current from being directly transmitted through the channel region (path R4) in the horizontal direction through the first conductive well 106, so that the electrostatic discharge protection device 100 can be effectively prevented from being damaged due to excessive heat caused by the electrostatic discharge current. In order to greatly increase the tolerance of the electrostatic discharge protection element 100, for example, a second breakdown current (It2).

Other preferred embodiments of the present invention will be described hereinafter, and in order to facilitate the comparison of the various embodiments and to simplify the description, the same elements are denoted by the same reference numerals in the following embodiments, and mainly for the embodiments. Explain the difference, and no longer repeat the repetitive part. Please refer to Figure 7. FIG. 7 is a schematic view showing an electrostatic discharge protection element according to another preferred embodiment of the present invention. As shown in FIG. 7, the ESD protection component 134 includes a first conductive semiconductor substrate 102, a second conductive buried layer 104, a first conductive well 106, at least a second conductive well 136, and a gate structure 110. The isolation structure 112, the first doping region 114, the second doping region 116, and the at least one third doping region 118. The first doped region 114 , the third doped region 118 , and the gate structure 110 are electrically connected to the first power source node 130 , and the second doped region 116 is electrically connected to the second power source node 132 . It should be noted that, compared with the foregoing embodiment, the second conductive type well 136 is further extended downward, so that part of the second conductive type well 136 is located in the second conductive type buried layer 104, that is, the second One of the conductive wells 136 has a depth substantially greater than the depth of the first conductive well 106. In addition, the number of the third doping regions 118 is not limited to one, and the arrangement of the plurality of third doping regions 118 helps to more precisely regulate the potential of the first conductive well 106, especially the first well region 120. In this embodiment, in addition to the arrangement of the second conductive type well 136 and the number of the third doped regions 118 are different from those of the foregoing embodiment, the materials of the respective elements and the phases of the respective elements are different. The manner of releasing the position and the electrostatic discharge current is similar to that of the above embodiment, and therefore will not be described again. In other embodiments, the center line of the second doping region 116 may also be used as an axis of symmetry. In the second doping region 116 opposite to one side of the formed structure, the same gate structure 110 is additionally disposed, first. The doped region 114 and the third doped region 118 are formed to form an electrostatic discharge protection element having a symmetrical structure.

In summary, the present invention enables the electrostatic discharge current to be electrically conducted in the vertical direction via the drain-doped region, the second well region, and the second conductive buried layer by disposing the second well region below the drain-doped region. That is to say, the path of the electrostatic discharge current can be increased to prevent the electrostatic discharge current from being directly discharged in the horizontal direction through the channel region to the source doping region, thereby preventing the electrostatic discharge protection component from being damaged due to excessive heat caused by the electrostatic discharge current. To improve the tolerance of the ESD protection component. In addition, in the present invention, the second well region is formed by separating the original first conductivity type well by the second conductivity type well, so that it is not necessary to use an additional mask to form the second well region, which also contributes to saving. Cost of production.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧Electrostatic discharge protection circuit

12‧‧‧Output/Input Pad

14‧‧‧Internal circuits

16‧‧‧ PMOS transistor

18‧‧‧ NMOS transistor

20‧‧‧ wire

22‧‧‧First parasitic diode

24‧‧‧Second parasitic diode

100‧‧‧Electrostatic discharge protection components

102‧‧‧First Conductive Semiconductor Substrate

104‧‧‧Second conductive buried layer

106‧‧‧First Conductive Well

108‧‧‧Second conductive well

110‧‧‧ gate structure

112‧‧‧Isolation structure

114‧‧‧First doped area

116‧‧‧Second doped area

118‧‧‧ Third doped area

120‧‧‧First Well Area

122‧‧‧Second well area

124‧‧‧ gate dielectric layer

126‧‧‧gate electrode

128‧‧‧ Sidewall

129‧‧‧Semiconductor components

130‧‧‧First power node

132‧‧‧second power node

134‧‧‧Electrostatic discharge protection components

136‧‧‧Second Conductive Well

D‧‧‧汲

G‧‧‧ gate

S‧‧‧ source

VDD‧‧‧ power input

VSS‧‧‧ grounding terminal

R1, R2, R3, R4‧‧ path

FIG. 1 is a schematic view showing a conventional electrostatic discharge protection circuit for protecting an internal circuit.

2 is a schematic view of an electrostatic discharge protection component in accordance with a preferred embodiment of the present invention.

3 to 6 are schematic views showing a method of fabricating an electrostatic discharge protection element according to a preferred embodiment of the present invention.

FIG. 7 is a schematic view showing an electrostatic discharge protection element according to another preferred embodiment of the present invention.

100‧‧‧Electrostatic discharge protection components

102‧‧‧First Conductive Semiconductor Substrate

104‧‧‧Second conductive buried layer

106‧‧‧First Conductive Well

108‧‧‧Second conductive well

110‧‧‧ gate structure

112‧‧‧Isolation structure

114‧‧‧First doped area

116‧‧‧Second doped area

118‧‧‧ Third doped area

120‧‧‧First Well Area

122‧‧‧Second well area

124‧‧‧ gate dielectric layer

126‧‧‧gate electrode

128‧‧‧ Sidewall

129‧‧‧Semiconductor components

130‧‧‧First power node

132‧‧‧second power node

R1, R2, R3, R4‧‧ path

Claims (14)

An electrostatic discharge (ESD) protection component includes: a first conductivity type well disposed in a first conductivity type semiconductor substrate; and a second conductivity type buried layer disposed under the first conductivity type well a first conductive type semiconductor substrate; and a second conductive type well separating the first conductive type well into a first well area and a second well area, wherein the first well area is not in contact with the second conductive type buried And the second conductive type well and the second well area are directly in contact with the second conductive type buried layer, so that the second conductive type buried layer and the second conductive type well are used together to isolate the first A well area and the second well area. The electrostatic discharge protection component of claim 1, wherein one of the second conductivity type wells has a depth substantially equal to a depth of the first conductivity type well. The electrostatic discharge protection component of claim 1, wherein one of the second conductive wells has a depth substantially greater than a depth of the first conductive well. The electrostatic discharge protection device of claim 1, wherein a depth of one of the first well regions and a depth of one of the second well regions are substantially equal to a depth of one of the first conductive wells. The electrostatic discharge protection element of claim 1, wherein the second conductive type buried layer is adjacent to the second conductive type well. The electrostatic discharge protection element of claim 1, wherein a cross-sectional width of one of the second well regions is substantially smaller than a cross-sectional width of the second conductive type buried layer. The electrostatic discharge protection component of claim 6, wherein the second well region is completely above the second conductivity type buried layer. The electrostatic discharge protection device of claim 1, wherein the first conductivity type is a P type and the second conductivity type is an N type. The electrostatic discharge protection device of claim 1, wherein the second conductive well comprises an annular well region, and the second conductive well surrounds the second well region. The electrostatic discharge protection device of claim 1, further comprising a gate structure disposed on the first conductive type semiconductor substrate, and the gate structure and the second conductive type buried layer are not completely overlapped with each other. The electrostatic discharge protection device of claim 10, further comprising: a first doped region having a second conductivity type disposed in the first well region; and a second doped region having a second conductivity type disposed on In the second well region, wherein the first doped region and the second doped region are respectively located on two sides of the gate structure; and a third doped region having a first conductivity type is disposed in the first well In the region, the third doped region is located on the other side of the gate structure relative to the second doped region. The electrostatic discharge protection device of claim 11, wherein the second well region is located between the second doped region and the second conductive well. The ESD protection device of claim 11, wherein the first doped region, the third doped region, and the gate structure are electrically connected to a first power supply node. The ESD protection device of claim 11, wherein the second doped region is electrically connected to a second power supply node.