TWI744187B - Semiconductor circuit and manufacturing method for the same - Google Patents

Abstract

A semiconductor circuit and a manufacturing method for the same are provided. The semiconductor circuit includes an electrostatic discharge protection circuit. The electrostatic discharge protection circuit includes an N-type region, a P-type well, a first P-type element and a first N-type element. The P-type well is in the N-type region. The first P-type element is in the N-type region. The N-type region is continuously connected between the P-type well and the first P-type element. The first N-type element is in the P-type well.

Description

Semiconductor circuit and manufacturing method thereof

The invention relates to a semiconductor circuit and a manufacturing method thereof.

Electrostatic discharge (ESD) includes a sudden current, electrical short circuit, or dielectric breakdown between two charged objects caused by contact. An electrostatic discharge event can occur in a very short period of time, for example, about a few nanoseconds, and a very large current will be generated during the electrostatic discharge event. When an electrostatic discharge event occurs in a semiconductor circuit, such a high current of several amperes may irreversibly damage the internal circuit. In order to protect the internal circuit from damage caused by electrostatic discharge events, an electrostatic discharge protection circuit can be provided to discharge electrostatic current.

Generally, some tests are performed on semiconductor integrated circuits. For example, in a latch-up test, a positive voltage, a positive current, and a negative current are applied to the conductive pad of the semiconductor circuit. The negative current test is to provide a negative voltage to the conductive pad, thereby drawing current from the ground terminal of the semiconductor circuit. However, the external negative voltage from the conductive pad may affect the internal circuit of the semiconductor circuit and cause malfunction.

The electrostatic discharge protection circuit will occupy additional layout area, which will hinder the increase in transistor density. Therefore, it is expected that the area of the electrostatic discharge protection circuit can be reduced.

The invention relates to a semiconductor circuit and a manufacturing method thereof.

According to one aspect of the present invention, a semiconductor circuit is provided, which includes an electrostatic discharge protection circuit. The electrostatic discharge protection circuit includes an N-type area, a P-type well, a first P-type element and a first N-type element. The P-type well is in the N-type zone. The first P-type element is in the N-type region. The N-type region is continuously connected between the P-type well and the first P-type element. The first N-type element is in the P-type well.

According to another aspect of the present invention, a method for manufacturing a semiconductor circuit is provided, which includes the following steps. An N-type region is formed. Form a P-type well. The P-type well is in the N-type zone. A first P-type element is formed in the N-type region. The first N-type element is formed in the P-type well. The semiconductor circuit includes an electrostatic discharge protection circuit. The electrostatic discharge protection circuit includes an N-type area, a P-type well, a first P-type element and a first N-type element. The N-type region is continuously connected between the P-type well and the first P-type element.

In order to have a better understanding of the above and other aspects of the present invention, the following specific examples are given in conjunction with the accompanying drawings to describe in detail as follows:

102, 1102, 2102, 3102: Electrostatic discharge protection circuit

116: first diode

118: The second diode

203: P-type area

204: P-type well

208: The first P-type element

210: The second P-type element

238: Third P-type element

244: First P-type source/drain

246: second P-type source/drain

306: N-type area

312: The first N-type element

314: Second N-type element

332: First N-type source/drain

334: Second N-type source/drain

348: N-type well

350: The third N-type element

426: internal circuit

452: signal output terminal

528: N-type transistor

536,636: Gate structure

540, 640: Gate dielectric layer

542,642: Gate electrode layer

554,656: signal end

630: P-type transistor

1322: The first N-type well

1324: The second N-type well

1522: The first N-type block

1524: The second N-type block

DQ: Conductive pad

VCCQ, VDD: signal input terminal

VSS, VSSQ: ground terminal

NPN1, PNP1, NPN2: Parasitic bipolar junction transistor

FIG. 1A illustrates an electrostatic discharge protection circuit of a semiconductor circuit and a manufacturing method thereof according to an embodiment.

Figure 1B shows the equivalent circuit of the electrostatic discharge protection circuit.

FIG. 2 shows an electrostatic discharge protection circuit of a semiconductor circuit and a manufacturing method thereof according to another embodiment.

FIG. 3 shows a semiconductor circuit according to an embodiment.

Fig. 4 shows a semiconductor circuit of a comparative example.

Figure 5 shows a semiconductor circuit of another comparative example.

Some examples are described below. It should be noted that this disclosure does not show all possible embodiments, and other implementation aspects not mentioned in this disclosure may also be applicable. Furthermore, the size ratios in the drawings are not drawn in proportion to the actual products. Therefore, the contents of the description and illustrations are only used to describe the embodiments, rather than to limit the scope of protection of this disclosure. In addition, the descriptions in the embodiments, such as detailed structure, process steps, material applications, etc., are for illustrative purposes only, and are not intended to limit the scope of protection of the present disclosure. The respective details of the steps and structures of the embodiments can be changed and modified according to the needs of the actual application process without departing from the spirit and scope of the present disclosure. In the following description, the same/similar symbols represent the same/similar elements.

Please refer to FIG. 1A, which illustrates an electrostatic discharge protection circuit 102 of a semiconductor circuit and a manufacturing method thereof according to an embodiment. The P-type well 204 is in the N-type zone 306. The N-type region 306 includes a first N-type well (NW) 1322 and a second N-type well (NWD) 1324 that are electrically connected. The second N-type well 1324 may be adjacent to the first N-type well 1322. The concentration of the N-type dopant of the first N-type well 1322 may be higher than that of the second N-type well 1324 The concentration of N-type dopants. In the upper view, the second N-type well 1324 may have a closed annular profile (not shown). The second N-type well 1324 is on the sidewall of the P-type well 204. The sidewall of the P-type well 204 may be surrounded by the second N-type well 1324. The P-type well 204 can be formed by an implantation process. The profile of the P-type well 204 can be defined by the first N-type well 1322 and the second N-type well 1324. The first N-type well 1322 below the P-type well 204 may abut all lower surfaces of the second N-type well 1324. In an embodiment, the N-type region 306 is continuously connected between the P-type well 204 and the first P-type element 208. The first P-type element 208 is in the second N-type well 1324. The second P-type element 210 is in the P-type well 204. The P-type dopant concentration of the first P-type element 208 and the second P-type element 210 may be higher than the P-type dopant concentration of the P-type well 204. The first P-type element 208 and the second P-type element 210 may be elements heavily doped with P-type impurities (P+). The first N-type element 312 is in the P-type well 204. The second N-type element 314 is in the second N-type well 1324. The N-type dopant concentration of the first N-type element 312 and the second N-type element 314 may be higher than that of the first N-type well 1322, and may be greater than the N-type impurity concentration of the second N-type well 1324 concentration. The first N-type element 312 and the second N-type element 314 may be heavily doped N-type impurities (N+) elements. The first P-type element 208 and the first N-type element 312 are electrically connected to the conductive pad DQ (for example, an I/O pad). The second N-type element 314 is electrically connected to the signal input terminal VCCQ. The second P-type element 210 is electrically connected to the ground terminal VSSQ.

In an embodiment, the N-type components and P-type components of the ESD protection circuit 102 may be components formed by doping impurities through a planting process. For example, the first N-type well 1322 may be doped with N-type through a planting process (or a first planting process) Impurities are formed in a P-type region 203 (such as a P-type substrate or a P-well) exposed by the opening of a mask layer (or a first mask layer, not shown). The second N-type well 1324 can be doped with N-type impurities to the P exposed by the opening of the other mask layer (or the second mask layer, not shown) by another implantation process (or a second implantation process). The type region 203 is formed. The first P-type device 208 can be formed by doping P-type impurities into the second N-type well 1324 by an implantation process. The second P-type device 210 can be formed by doping P-type impurities into the P-type well 204 by an implantation process. The first P-type element 208 and the second P-type element 210 may be formed at the same time. The first N-type element 312 can be formed by doping N-type impurities into the P-type well 204 by an implantation process. The second N-type element 314 can be formed by doping N-type impurities into the second N-type well 1324 by an implantation process. The first N-type element 312 and the second N-type element 314 can be formed at the same time. But this disclosure is not limited to this. In an embodiment, the manufacturing method of the semiconductor circuit may include an annealing process to diffuse impurities.

FIG. 1B shows the equivalent circuit of the electrostatic discharge protection circuit 102. As shown in FIG.

Referring to FIGS. 1A and 1B, the electrostatic discharge protection circuit 102 includes diodes, such as a first diode 116 and a second diode 118. The N-type semiconductor of the first diode 116 may include an N-type region 306 and a second N-type element 314. The P-type semiconductor of the first diode 116 may include a first P-type element 208. The N-type semiconductor of the second diode 118 may include the first N-type element 312. The P-type semiconductor of the second diode 118 may include a P-type well 204 and a second P-type element 210. The first diode 116 is electrically connected between the signal input terminal VCCQ and the conductive pad DQ. The second diode 118 is electrically connected between the ground terminal VSSQ and the conductive pad DQ. The conductive pad DQ is electrically connected to the first P-type element 208 (anode) of the first diode 116 and the second diode 118 between the first N-type element 312 (cathode).

Please refer to FIG. 2, which illustrates an electrostatic discharge protection circuit 1102 of a semiconductor circuit and a manufacturing method thereof according to another embodiment. The difference between the embodiment shown in Fig. 2 and the embodiment shown in Fig. 1A is explained as follows. The first N-type well 1322 below the P-type well 204 abuts part of the lower surface of the second N-type well 1324. The equivalent circuit of the electrostatic discharge protection circuit 1102 may be similar to the equivalent circuit shown in FIG. 1B.

In an embodiment, the electrostatic discharge protection circuit can be used to protect the internal circuit of the semiconductor circuit to prevent the internal circuit from being damaged by electrostatic discharge.

FIG. 3 shows a semiconductor circuit according to an embodiment. The semiconductor circuit may include an electrostatic discharge protection circuit 102 and an internal circuit 426. The internal circuit 426 may include transistors, such as an N-type transistor 528 and a P-type transistor 630. The internal circuit 426 may include a complementary metal oxide semi-transistor CMOS. The complementary metal oxide semi-transistor CMOS may include an N-type transistor 528 (such as NMOS) and a P-type transistor 630 (such as PMOS).

The N-type transistor 528 may include a first N-type source/drain 332, a second N-type source/drain 334, a P-type region 203, and a gate structure 536. The first N-type source/drain electrode 332 and the second N-type source/drain electrode 334 can be formed in the P-type region 203 by a planting process. The first N-type source/drain 332 and the second N-type source/drain 334 may be source/drain heavily doped with N-type impurities. One of the first N-type source/drain 332 and the second N-type source/drain 334 is a source. The other of the first N-type source/drain 332 and the second N-type source/drain 334 is a drain. The third P-type element 238 may be formed in the P-type region 203. The concentration of the P-type dopant of the third P-type element 238 may be higher than that of the P-type region 203 Qualitative concentration. The third P-type element 238 may be an element heavily doped with P-type impurities (P+). The gate structure 536 may include a gate dielectric layer 540 and a gate electrode layer 542. The gate dielectric layer 540 may be formed on the P-type region 203 between the first N-type source/drain 332 and the second N-type source/drain 334. The gate electrode layer 542 is formed on the gate dielectric layer 540.

The P-type transistor 630 may include a first P-type source/drain electrode 244, a second P-type source/drain electrode 246, a gate structure 636, and an N-type well 348. The first P-type source/drain electrode 244 and the second P-type source/drain electrode 246 can be formed in the N-type well 348 by an implantation process. The first P-type source/drain 244 and the second P-type source/drain 246 may be source/drain heavily doped with P-type impurities. One of the first P-type source/drain 244 and the second P-type source/drain 246 is a source. The other of the first P-type source/drain 244 and the second P-type source/drain 246 is a drain. The third N-type element 350 may be formed in the N-type well 348. The concentration of the N-type dopant of the third N-type element 350 may be higher than the concentration of the N-type dopant of the N-type well 348. The third N-type element 350 may be a heavily doped N-type impurity (N+) element. The gate structure 636 may include a gate dielectric layer 640 and a gate electrode layer 642. The gate dielectric layer 640 may be formed on the N-type well 348 between the first P-type source/drain electrode 244 and the second P-type source/drain electrode 246. The gate electrode layer 642 is formed on the gate dielectric layer 640.

The N-type region 306 of the ESD protection circuit 102 and the N-type well 348 of the P-type transistor 630 of the internal circuit 426 can be separated from each other by the P-type region 203.

The first N-type source/drain 332 and the third P-type element 238 of the N-type transistor 528 can be electrically connected to the ground terminal VSS. The first P-type source/drain 244 and the third N-type element 350 of the P-type transistor 630 can be electrically connected to the signal input terminal VDD. The second N-type source/drain 334 of the N-type transistor 528 and the second of the P-type transistor 630 The P-type source/drain electrode 246 may be electrically connected to the signal output terminal 452. The gate structure 536 of the N-type transistor 528 can be electrically connected to the signal terminal 554. The gate structure 636 of the P-type transistor 630 can be electrically connected to the signal terminal 656.

In one embodiment, the signal input terminal VDD of the internal circuit 426 and the signal input terminal VCCQ of the electrostatic discharge protection circuit 102 are a common signal input terminal. The ground terminal VSS of the internal circuit 426 and the ground terminal VSSQ of the electrostatic discharge protection circuit 102 are a common ground terminal. But this disclosure is not limited to this.

In the latch-up test, a negative voltage is applied to the conductive pad DQ to perform a negative current test, which draws current from the ground terminal VSSQ and causes the parasitic bipolar junction transistor NPN1 to turn on. The parasitic bipolar junction transistor NPN1 can be formed by the first N-type element 312, the P-type well 204 and the N-type region 306. The parasitic bipolar junction transistor NPN1 in the ESD protection circuit 102 is independent of the internal circuit 426, and therefore will not cause a latch-up effect on the internal circuit 426.

In another embodiment, the electrostatic discharge protection circuit 102 of the semiconductor circuit can be replaced by the electrostatic discharge protection circuit 1102 shown in FIG. 2. In the latch-up test, a negative voltage is applied to the conductive pad DQ to perform a negative current test, which draws current from the ground terminal VSSQ and causes the parasitic bipolar junction transistor NPN1 to turn on. The parasitic bipolar junction transistor NPN1 can be formed by the first N-type element 312, the P-type well 204 and the N-type region 306. The parasitic bipolar junction transistor NPN1 in the ESD protection circuit 1102 is independent of the internal circuit 426, so it will not cause a latch-up effect on the internal circuit 426.

Figure 4 shows a comparative example of a semiconductor circuit, which is similar to that shown in Figure 3 The differences between the semiconductor circuits of the illustrated embodiment are explained as follows. The electrostatic discharge protection circuit 2102 has a first N-type block 1522 and a second N-type block 1524. The P-type well 204 and the second N-type element 314 are in the first N-type block 1522. The first P-type element 208 and the second N-type element 314 are in the second N-type block 1524. The first N-type block 1522 and the second N-type block 1524 are separated from each other by the P-type region 203. The P-type region 203 used to separate the first N-type block 1522 and the second N-type block 1524 needs to occupy an additional layout area. Therefore, compared with the comparative example in FIG. 4, the semiconductor circuit of the embodiment in FIG. 3 can occupy a smaller layout area. Compared with the ESD protection circuit 2102 in FIG. 4, the ESD protection circuit 102 in FIGS. 1A and 3, and the ESD protection circuit 1102 in FIG. 2 can occupy a smaller layout area.

Fig. 5 shows a semiconductor circuit of another comparative example. The difference between the semiconductor circuit of the embodiment shown in Fig. 3 is that the first N-type element 312 and the second P-type element of the electrostatic discharge protection circuit 3102 210 is formed in the P-type region 203. In the latch-up test, a negative voltage is applied to the conductive pad DQ to perform a negative current test, which draws current from the ground terminal VSSQ and causes the parasitic bipolar junction transistor NPN1 to turn on. The parasitic bipolar junction transistor NPN1 causes the parasitic bipolar junction transistor PNP1 and the parasitic bipolar junction transistor NPN2 in the internal circuit 426 to open, forming a latch. The parasitic bipolar junction transistor NPN1 can be formed by the first N-type element 312, the P-type region 203 and the N-type well 348. The parasitic bipolar junction transistor PNP1 can be formed by the first P-type source/drain electrode 244, the N-type well 348 and the P-type region 203. The parasitic bipolar junction transistor NPN2 can be used by the N-type well 348 and the P-type region 203 It is formed with the first N-type source/drain electrode 332.

In summary, although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to those defined by the attached patent application scope.

102: Electrostatic discharge protection circuit

203: P-type area

204: P-type well

208: The first P-type element

210: The second P-type element

306: N-type area

312: The first N-type element

314: Second N-type element

1322: The first N-type well

1324: The second N-type well

DQ: Conductive pad

VCCQ: signal input terminal

VSSQ: ground terminal

Claims (8)

A semiconductor circuit includes an electrostatic discharge protection circuit, wherein the electrostatic discharge protection circuit includes: an N-type region; a P-type well in the N-type region; a first P-type element in the N-type region, The N-type region is continuously connected between the P-type well and the first P-type element; a first N-type element in the P-type well, wherein the P-type well has only one PN junction in it, The PN junction is formed by the P-type well and the first N-type element, the electrostatic discharge protection circuit includes a first diode and a second diode, and the first diode includes the N-type region And the first P-type element, the second diode includes the P-type well and the first N-type element; a conductive pad electrically connected to the first P-type element and the first N-type element; The signal input terminal is electrically connected to the N-type area; and a ground terminal is electrically connected to the P-type well. The semiconductor circuit according to claim 1, wherein the outline of the P-type well is defined by the N-type region. The semiconductor circuit according to claim 1, wherein the N-type region includes: a first N-type well; and a second N-type well electrically connected to the first N-type well. The semiconductor circuit according to claim 3, wherein the second N-type well is on the sidewall of the P-type well. The semiconductor circuit of the semiconductor circuit according to claim 3, wherein the first N-type well is below the P-type well. The semiconductor circuit according to claim 3, wherein the concentration of the N-type dopant of the first N-type well is higher than the concentration of the N-type dopant of the second N-type well. The semiconductor circuit according to claim 3, further comprising a P-type region, wherein the first N-type well and the second N-type well are in the P-type region. A method of manufacturing a semiconductor circuit includes: forming an N-type region; forming a P-type well, wherein the P-type well is in the N-type region; forming a first P-type element in the N-type region; and forming a The first N-type element is in the P-type well, wherein the P-type well has only one PN junction in it, and the one PN junction is formed by the P-type well and the first N-type element; forming a conductive pad; forming A signal input terminal; and a ground terminal is formed, wherein the semiconductor circuit includes an electrostatic discharge protection circuit, the electrostatic discharge protection circuit includes the N-type region, the P-type well, the first P-type element and the first N-type Element, the N-type region is continuously connected between the P-type well and the first P-type element, the electrostatic discharge protection circuit includes a first diode and a second diode, and the first diode includes The N-type region and the first P-type element, the second diode includes the P-type well and the first N-type element, and the conductive pad is electrically connected to the first P-type element And the first N-type element, the signal input terminal is electrically connected to the N-type area, and the ground terminal is electrically connected to the P-type well.

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