TW201431070A - Transistor structure for electrostatic discharge protection - Google Patents

Abstract

The present invention discloses a transistor structure for electrostatic discharge protection. The structure includes a substrate, a doped well, a first doped region, a second doped region and a third doped region. The doped well is disposed in the substrate and has a first conductive type. The first doped region is disposed in the substrate, encompassed by the doped well and has the first conductive type. The second doped region is disposed in the substrate, encompassed by the doped well and has a second conductive type. The third doped region is disposed in the substrate, encompassed by the doped well and has the second conductive type. A gap is disposed between the first doped region and the second doped region.

Description

Plasma structure with electrostatic discharge protection

The present invention relates to a transistor, and more particularly to a transistor structure having an electrostatic protection effect.

As the size of semiconductor integrated circuit devices continues to shrink, in the submicron complementary metal oxide semiconductor (CMOS) technology, shallow junction depth, thinner gate The thickness of the gate oxide is added to the process of light doped drain (LDD), shallow trench isolation (STI), and self-aligned silicide. Has become a standard process. However, the above process makes the integrated circuit product more susceptible to electrostatic discharge (ESD) damage, so the protection circuit design of the electrostatic discharge must be added to the chip to protect the integrated component circuit.

Please refer to FIG. 1 , which is a schematic diagram of a circuit having an electrostatic discharge protection component. In general, the internal circuit 104 can perform various functions by inputting the signal of the pad 100. However, if a special situation occurs, such as the input pad 100 is in contact with the human body to generate an electrostatic discharge current, an excessive current may damage the internal circuit. 104. Therefore, the prior art also provides an ESD protection component 102. When an ESD current is generated, the ESD protection component 102 can be properly turned on to pass the ESD current to the ground terminal Vss.

However, the existing electrostatic protection component 102 often has a problem that the triggering voltage is too high, that is, a certain degree of electrostatic current can be driven, which causes the reaction time of the electrostatic protection component 102 to be too long, which greatly reduces the practicality thereof. Sex.

In order to solve the aforementioned problems, the present invention thus provides a transistor structure having an electrostatic discharge protection effect, which can have a low starting voltage.

According to an embodiment of the present invention, the present invention has a dielectric structure having an electrostatic discharge protection effect, comprising a substrate, a doping well, a first doping region, a second doping region, and a third doping region. The doping well is disposed in the substrate and has a first conductivity type. The first doped region is disposed in the substrate and surrounded by the doped well and has a first conductivity type. The second doped region is disposed in the substrate and surrounded by the doped well and has a second conductivity type. The third doped region is disposed in the substrate and surrounded by the doped well and has the second conductivity type. There is a spacing between the first doped region and the second doped region.

The invention provides a crystal structure which can have electrostatic protection effect, which has a parasitic diode structure, so that the starting voltage of the static electricity protection can be effectively reduced to improve the sensitivity of the static electricity protection.

100‧‧‧ input pad

102‧‧‧Electrostatic protective components

104‧‧‧Internal circuits

300‧‧‧Base

302‧‧‧Doped well

304‧‧‧First doped area

304a‧‧‧ first doped area

306‧‧‧Second doped area

308‧‧‧ Third doped area

310‧‧‧Four doped area

312‧‧‧ gate

314‧‧‧Isolation structure

314a‧‧‧Isolation structure

316‧‧‧ Parasitic diode

318‧‧‧High potential source

320‧‧‧Low potential source

322‧‧‧Gate grounded N-type oxy-oxygen crystal

324‧‧‧Bipolar transistor

FIG. 1 is a schematic diagram of a circuit having an electrostatic discharge protection component.

2, 3, and 4 are schematic views showing a structure of a transistor having an electrostatic discharge protection effect according to a first embodiment of the present invention.

FIG. 5 is a schematic view showing the electrostatic protection effect of the transistor structure of the present invention.

FIG. 6 , FIG. 7 and FIG. 8 are schematic views showing a structure of a transistor having an electrostatic discharge protection effect according to a second embodiment of the present invention.

FIG. 9 is a schematic view showing a structure of a transistor having an electrostatic discharge protection effect according to still another embodiment of the present invention.

The present invention will be further understood by those of ordinary skill in the art to which this invention pertains. The constitution of the present invention and the effects to be achieved will be described.

Please refer to FIG. 2, FIG. 3 and FIG. 4, which are schematic diagrams showing a structure of a transistor having an electrostatic discharge protection effect according to a first embodiment of the present invention, wherein FIG. 3 is aA along the second figure. 'The schematic diagram of the tangent line, and the fourth figure is the equivalent circuit diagram of the crystal structure of the electrostatic discharge protection in the second figure and the third figure. As shown in FIG. 2 and FIG. 3, the structure of the transistor having the electrostatic discharge protection effect of the present invention comprises a substrate 300, a doping well 302, a first doping region 304, and a second doping region 306. A third doped region 308 and a fourth doped region 310. The substrate 300 is, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate or a silicon-on-insulator (SOI) substrate, but not This is limited to this. The doping well 302 is disposed in the substrate 300 and has a first conductivity type, such as a P-type. The doping well 302 preferably completely surrounds the first doping region 304, the second doping region 306, the third doping region 308, and the fourth doping region 310, that is, the first doping region 304, the second The doped region 306, the third doped region 308, and the fourth doped region 310 are preferably not in direct contact with the substrate 300.

The first doped region 304 preferably has a first conductivity type, such as a P type; the second doped region 306 preferably has a second conductivity type, such as an N type; and the third doped region 308 preferably has a second conductivity type. For example, the N-type; the fourth doped region 310 preferably has a first conductivity type, such as a P-type. In one embodiment, the doping concentration of the first doping region 304 and the fourth doping region 310 are the same, and the concentration is greater than the concentration of the doping well 302. In another embodiment, the doping concentration of the second doping region 306 and the third doping region 308 are the same.

As seen from the top view of FIG. 2, the first doped region 304 is completely surrounded by the second doped region 306, but there is a spacing L between the first doped region 304 and the second doped region 306. That is, between the first doped region 304 and the second doped region 308 is a doping well 302 having a width L, and the first doped region 304 and the second doped region 306 are not in direct contact. In addition, a gate 312 is formed over the doping well 302 between the second doping region 306 and the third doping region 308, such as a gate structure of polysilicon or metal to bond the second doping region 306 with the third doping region 306. Miscellaneous area 308 separate. An isolation structure 314 is disposed on the periphery of the third doping region 308, which surrounds the first doping region 304, the second doping region 306, and the third doping region 308. The fourth doped region 310 is located outside of the isolation structure 314, which surrounds the isolation structure 314. As shown in FIG. 3, the high potential source 318 is electrically connected to the second doping region 306, and the low potential source 320 is electrically connected to the gate 312, the third doping region 308, and the fourth doping region 310. As such, the doping well 302, the second doping region 306, the gate 312, and the third doping region 308 form a "gate grounded NMOS (ggNMOS) 322", wherein The second doped region 306 is used as a drain, the third doped region 308 is used as a source, and the doping well 302 is used as a body. In one embodiment, the doped regions are electrically connected to the high potential source 318 or the low potential source 320, for example, through a contact plug or the like. It should be noted that the first doped region 304 of the present invention is a floating structure that is not connected to other external signal output/input terminals, for example, and is not connected to other contact plugs. As such, the first doped region 304, the second doped region 306, and the doping well 302 therebetween form a "parasitic diode 316" structure. Referring to the equivalent circuit diagram of FIG. 4, when the high potential source 318 generates an electrostatic discharge current with a large current amount, the current turns on the gate grounded N-type gold oxide transistor 322 and passes through the second doping. The region 306 and the third doped region 308 eventually flow into the low potential source 320, such as a ground terminal, to prevent the electrostatic discharge current from damaging the main circuit. Since the present invention additionally configures a first doping region 304 to form a parasitic diode 316 with the second doping region 306, such a configuration can effectively reduce the startup voltage of the gate-grounded N-type MOS transistor 322 (triggering). Voltage) to increase the sensitivity of its electrostatic protection.

Please refer to FIG. 5, which is a schematic diagram of the protection electrostatic effect of the transistor structure of the present invention, wherein the horizontal axis is voltage (unit: volt), and the vertical axis is current (unit: ampere), and the solid triangle line indicates no setting. The structure of the floating first doped region 304 is floated, while the line of the open diamond indicates the structure in which the floating first doped region 304 is disposed. It can be clearly seen from Fig. 5 that the starting voltage of the structure in which the first doping region 304 is provided is about 8.3 volts, which is significantly smaller than the starting voltage (about 13.2 volts) in which the first doping region 304 is not provided, which proves Have Setting the first doping region 304 can obtain a more sensitive electrostatic protection effect. In another embodiment of the present invention, by further adjusting the size of the gap L between the first doping region 304 and the second doping region 306, the magnitude of the starting voltage can be adjusted, and can even be reduced to 1 to 8 volts. between.

In addition, another feature of the present embodiment is that the first doped region 304 can be compatible with processes compatible with existing fabricated MOS transistors without the need to form additional reticle. For example, the first doping region 304 may have the same conductivity type as the fourth doping region 310, for example, a P-type, and the doping concentrations of the two are the same, and are formed by the same ion implantation process. If the doping region with different dopant concentrations is additionally formed to achieve a higher cost of lowering the startup voltage, the present invention can be completely compatible with the current process without an additional mask, and the manufacturing cost can be saved.

Please refer to FIG. 6 , FIG. 7 and FIG. 8 , which are schematic diagrams showing a structure of a crystal having electrostatic protection effect according to another embodiment of the present invention, wherein FIG. 7 is a sixth diagram along BB′. A schematic diagram of a tangent line, and Fig. 8 is an equivalent circuit diagram of a transistor having electrostatic protection in Figs. 6 and 7. The structure of this embodiment is substantially similar to that of the previous embodiment, except that the foregoing embodiment is an electrostatic protection element applied to a gate-grounded N-type metal oxide transistor, and the present embodiment is applied to a bipolar transistor ( Bipolar transistor, BJT). In detail, the second doped region 306 and the third doped region 308 of the embodiment have an isolation structure 314a so that there is no direct contact between the second doped region 306 and the third doped region 308. In one embodiment, isolation structure 314a and isolation structure 314 are formed in the same steps as the process. As shown in FIG. 7 and FIG. 8, in the present embodiment, the second doping region 306, the third doping region 308, and the doping well 302 form a bipolar transistor 324, wherein the second doping region 306 is used as a collector, the third doped region 308 is used as an emitter, and the doping well 302 is used as a base. Similarly, the bipolar transistor 324 can act as an electrostatic protection circuit and, in conjunction with the floating first doped region 304, can reduce the startup voltage of the bipolar transistor 324.

Please refer to FIG. 9 , which illustrates electrostatic protection in another embodiment of the present invention. Schematic diagram of the efficacy of the crystal structure. As shown in FIG. 9, the first doping region 304 of the present embodiment may include a plurality of sub-doped regions 304a, each of which is separated and independently doped with a well 302 and The two doped regions 306 are surrounded by and have a spacing L from the second doped region 306. The first doped region 304a of the present embodiment can also provide a good electrostatic protection effect, in connection with the first embodiment, which is connected to each other and presents a strip-shaped first doped region 304. It should be noted that the sub-first doped region 304a shown in FIG. 9 is exemplified by a gate-grounded N-type MOS transistor 322 (as shown in FIG. 2), and those of ordinary skill in the art should be able to understand that The sub-first doped region 304a in this embodiment is also applicable to a structure having a bipolar transistor 324 (as shown in FIG. 6).

In summary, the present invention provides a transistor structure capable of having an electrostatic protection effect, which has a parasitic diode structure, thereby effectively reducing the startup voltage of the static electricity protection to improve the sensitivity of the static electricity protection. It should be understood that the first conductivity type and the second conductivity type of the foregoing only represent different conductivity types, while in other embodiments, they may be interchanged, for example, the first conductivity type may be an N type, and the second type. The conductivity type may be a P type.

300‧‧‧Base

302‧‧‧Doped well

304‧‧‧First doped area

306‧‧‧Second doped area

308‧‧‧ Third doped area

310‧‧‧Four doped area

312‧‧‧ gate

314‧‧‧Isolation structure

316‧‧‧ Parasitic diode

318‧‧‧High voltage source

320‧‧‧Low voltage source

322‧‧‧Gate grounded N-type oxy-oxygen crystal

Claims (20)

A transistor structure having an electrostatic discharge protection effect, comprising: a substrate; a doping well disposed in the substrate, wherein the doping well has a first conductivity type; a first doping region is disposed in the substrate Surrounded by the doping well, wherein the first doped region has the first conductivity type; a second doped region is disposed in the substrate and surrounded by the doping well, wherein the second doped region has a first a second conductivity type having a spacing between the first doped region and the second doped region; and a third doped region disposed in the substrate and surrounded by the doping well, wherein the third doped region There is this second conductivity type. A transistor structure having electrostatic discharge protection effect as described in claim 1 of the patent application, wherein The first doped region is floating. The transistor structure having the electrostatic discharge protection effect as described in claim 1, wherein the first doped region and the second doped region form a parasitic diode. The transistor structure having the electrostatic discharge protection effect as described in claim 1, wherein the second doping region is connected to a signal input end. The transistor structure having the electrostatic discharge protection effect as described in claim 1, wherein the third doping region is at a low potential. The transistor structure having the electrostatic discharge protection effect according to claim 1, further comprising a gate disposed on the substrate and disposed between the second doped region and the third doped region. A transistor structure having electrostatic discharge protection effect as described in claim 6 wherein the gate is extremely low. The transistor structure having electrostatic discharge protection effect according to claim 6, wherein the gate, the second doping region and the third doping region form a transistor. The transistor of claim 1, further comprising an isolation structure disposed in the substrate and disposed between the second doped region and the third doped region. The transistor structure having electrostatic discharge protection effect according to claim 9, wherein the second doping region, the third doping region and the doping well form a bipolar transistor. The transistor structure having the electrostatic discharge protection effect as described in claim 1, further comprising a fourth doping region disposed in the substrate, wherein the fourth doping region and the third doping region are An isolation structure is separated. The transistor structure having the electrostatic discharge protection effect according to claim 11, wherein the four doped regions have the first conductivity type, and the four doped regions have the same doping as the first doped region. Qualitative concentration. The transistor structure having electrostatic discharge protection effect according to claim 11, wherein the fourth doping region is low. The transistor structure having the electrostatic discharge protection effect as described in claim 1, wherein the first doped region comprises a plurality of sub-first doped regions. The transistor structure having electrostatic discharge protection effect as described in claim 14, wherein the first doped regions are each separately surrounded by the second doped region. The transistor structure having the electrostatic discharge protection effect as described in claim 1, wherein the first doped region is completely surrounded by the second doped region from a top view. The transistor structure having electrostatic discharge protection effect as described in claim 1, wherein the second doping region is directly and completely surrounded by the doping well. The transistor structure having the electrostatic discharge protection effect as described in claim 1, wherein the third doping region is directly and completely surrounded by the doping well. The transistor structure having the electrostatic discharge protection effect according to claim 1, wherein the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type. The transistor structure having the electrostatic discharge protection effect according to claim 1, wherein the first conductivity type is an N-type conductivity type, and the second conductivity type is a P-type conductivity type.