TWI538160B - Electrostatic discharge protection device and applications thereof - Google Patents

Description

Electrostatic discharge protection device and its application

The present invention relates to a semiconductor device and its use, and in particular to an electrostatic discharge (ESD) protection device and application thereof.

Electrostatic discharge is a phenomenon in which an electrostatic charge on a non-conductive surface migrates through a conductive material. Since the electrostatic voltage is usually quite high, electrostatic discharge can easily damage the substrate and other components of an integrated circuit. In order to protect the integrated circuit from electrostatic discharge damage, devices having a function of conducting electrostatic discharge current to the ground are integrated into the integrated circuit. For example, ground gated n-type metal-Oxide-Semiconductor (GGNMOS) transistor units are widely used in protective circuits.

When ESD zapping occurs, a snapback causes the ground gate n-type metal-oxide-semiconductor transistor unit to conduct to conduct a large electrostatic discharge current (ESD current) to its drain structure. The electrostatic discharge current is conducted to the ground between the source structure and the source structure. In order to withstand a sufficiently high electrostatic discharge current, the grounding gate n-type metal-oxide-semiconductor transistor unit often has a large component size, and in the integrated circuit layout, it is generally drawn to include a plurality of finger-shaped transistor units. Multi-finger structure to save the occupied layout area.

Moreover, due to the difference in layout position, the finger-shaped transistor units of the multi-finger structure have different substrate resistances, so that at the instant of electrostatic discharge, only some of the fingers are often used. The transistor unit is turned on first, and because of the secondary snapback phenomenon, the first finger-shaped transistor unit is instantaneously burned by the electrostatic discharge current, so that other finger-shaped transistor units have no chance to start to assist. ESD discharge current (so-called component latch-up effect). Therefore, the electrostatic discharge withstand capability of the ground gate n-type metal-oxide-semiconductor transistor unit is not increased in proportion as the element size increases.

Therefore, how to promote the uniform conduction of the respective finger-shaped transistor units of the grounding gate n-type metal-oxide-semiconductor transistor unit to collectively unload the electrostatic discharge current has become a challenge in electrostatic discharge protection design.

One of the objects of the present invention is to provide an Electrostatic Discharge (ESD) protection device comprising: a substrate, a gate, a drain structure, and a source structure. Wherein, the substrate has a first electrical property. The gate is on the surface of the substrate. The drain structure has a second electrical property, including: a first doped region, a second doped region, and a third doped region. The first doped region is adjacent to the gate and extends from the surface of the substrate into the substrate and has a first doping concentration. The second doped region extends from the surface into the first doped region and is located in the first doped region and has a second doping concentration substantially greater than the first doping concentration. The third doped region is located in the substrate, and below the first doped region, has a third doping concentration substantially greater than the first doping concentration. The source structure is adjacent to the gate and is located in the substrate and has a second electrical property.

In an embodiment of the invention, the electrostatic discharge protection device is adapted to protect a low voltage internal circuit, wherein the third doping concentration is substantially greater than the second doping concentration. In another embodiment of the invention, the electrostatic discharge protection device is adapted to protect a high voltage internal circuit, wherein the third doping concentration is substantially less than or equal to the second doping concentration.

In an embodiment of the invention, the electrostatic discharge protection device is a double-diffused-drain metal-Oxide-Semiconductor Field-Effect-Transistor (DDD MOS FET) ), or a Field-Drift Metal-Oxide-Semiconductor Field-Effect-Transistor (FD MOS FET).

In an embodiment of the invention, the electrostatic discharge protection device includes a first shallow trench isolation layer located in the first doped region and isolating the second doped region from the gate.

In an embodiment of the invention, the source structure includes a fourth doped region and a fifth doped region. Wherein the fourth doped region is adjacent to the gate and extends from the surface of the substrate into the substrate and has a first doping concentration; the fifth doped region extends from the surface into the fourth doped region and has a Two doping concentration.

In an embodiment of the invention, the ESD protection device further includes a second shallow trench isolation layer, located in the fourth doped region, and isolating the fifth doped region from the gate.

In an embodiment of the invention, the third doped region has a third lateral dimension of the vertical gate, and the third lateral dimension is substantially smaller than the first lateral dimension of the first doped region and substantially larger than the second doped region The second lateral dimension.

Another object of the present invention is to provide an electrostatic discharge protection circuit for protecting an internal circuit comprising a gate metal-oxide-semiconductor conductor transistor unit. The gate metal-oxide-semiconductor conductor transistor unit further includes: a substrate, a gate, a gate structure, and a source structure. Wherein the substrate has a first electrical property; the gate is on the surface of the substrate; the drain structure has a second electrical property, and includes: a first doped region adjacent to the gate and extending from the surface into the substrate And having a first doping concentration; a second doping region extending from the surface into the first doping region and having a second doping concentration substantially greater than the first doping concentration; and a third doping region, Located in the substrate, below the first doped region, having a third doping concentration substantially greater than the first doping concentration. The source structure is adjacent to the gate and is located in the substrate and has a second electrical property.

In an embodiment of the invention, the internal circuit is a power circuit or an input/output circuit (I/O circuit).

In an embodiment of the invention, the third doping concentration is substantially greater than the second doping concentration. In another embodiment of the invention, the third doping concentration is substantially less than or equal to the second doping concentration.

In an embodiment of the invention, the gate metal-oxide-semiconductor conductor transistor unit is a double-diffused drain structure metal-oxide-semiconductor field effect transistor or a field drift metal-oxide-semiconductor field Effect transistor.

In an embodiment of the invention, the electrostatic discharge protection device includes a first shallow trench isolation layer located in the first doped region and isolating the second doped region from the gate.

In an embodiment of the invention, the source structure includes a fourth doped region and a fifth doped region. Wherein, the fourth doping region is adjacent to the gate and extends from the surface of the substrate into the substrate and has a first doping concentration; the fifth doping region extends from the surface of the substrate into the fourth doping region. And having a second doping concentration.

In an embodiment of the invention, the ESD protection circuit further includes a second shallow trench isolation layer located in the fourth doped region and isolating the fifth doped region from the gate.

In an embodiment of the invention, the third doped region has a third lateral dimension of the vertical gate. The third lateral dimension is substantially smaller than the first lateral dimension of the first doped region and substantially greater than the second lateral dimension of the second doped region.

In an embodiment of the invention, the metal-oxide-semiconductor transistor unit is a gate-grounded n-type metal-oxide-semiconductor field effect transistor, and the source structure and the gate are grounded, and the gate structure is The VDD power line or input/output pad of the internal circuit is coupled.

In an embodiment of the invention, the metal-oxide-semiconductor unit is a gate VDD P-Type Metal-Oxide-Semiconductor Field-Effect-Transistor (GDPMOS) The field effect transistor has a source structure and a gate coupled to the VDD power line of the internal circuit, and the drain structure is coupled to the VSS power line or the input/output pad of the internal circuit.

According to the above embodiment, the present invention provides an electrostatic discharge protection device comprising a metal-oxide-semiconductor conductor unit. By adding a doping region having a higher doping concentration than the drain drift region below the drain drift region of the metal-oxide-semiconductor conductor unit, and reducing the doping region with a higher doping concentration than the drain region of the drain The second sudden crash caused a chance that the holding voltage was too low. And the N-type metal-oxide-semiconductor transistor is turned on, and only one snapback occurs, thereby increasing the holding voltage higher than the operating voltage thereof, thereby improving the ability of the metal-oxide-semiconductor transistor to block the component. Moreover, the ability of the metal-oxide-semiconductor transistor to withstand electrostatic discharge current can be increased in proportion as the size of the element increases. If it is used in an electrostatic discharge protection device having a plurality of finger-shaped transistor units, the respective finger-shaped transistor units can be uniformly turned on to collectively unload the electrostatic discharge current, thereby achieving the above object.

It is an object of the present invention to provide an electrostatic discharge protection device having a metal-oxide-semiconductor field effect transistor unit to improve the electrostatic discharge withstand capability of the metal-oxide-semiconductor field effect transistor unit. In order to make the above and other objects, features and advantages of the present invention more apparent, the following are a plurality of n-type metal-oxide-semiconductor field effect transistor units or field-spreading n-type metals having a double-diffused drain structure. The ESD protection circuit of the oxide-semiconductor field effect transistor unit, but not limited thereto, is a preferred embodiment and is described in detail with reference to the following drawings: Please refer to FIG. 1A and FIG. 1A is a top plan view of an electrostatic discharge protection device 100 according to a preferred embodiment of the present invention. 1B is a cross-sectional view showing the structure of the ESD protection device 100 taken along line 1B of FIG. 1A.

As shown in FIG. 1A, the ESD protection device 100 is a multi-finger structure having a plurality of finger metal-oxide-semiconductor conductor transistor units. The periphery of the finger metal-oxide-semiconductor conductor structure is surrounded by a guard ring 106. For example, in the present embodiment, the ESD protection device 100 includes a plurality of gate-grounded n-type metal-oxide-semiconductor field effect transistor units 101 and 111. In other embodiments, the ESD protection device 100 may also include a plurality of finger-shaped gate-connected power p-type metal-oxide-semiconductor conductor field effect transistor units.

As shown in FIG. 1B, each of the gate-grounded n-type metal-oxide-semiconductor field effect transistor units (described below for the sake of clarity, only the transistor unit 101 is selected) is formed in the substrate 102. Each includes a gate 103, a drain structure 104, and a source structure 105. In the present embodiment, the substrate 102 is p-type electrically and has a high voltage p-type well (indicated by HVPW). Gate 103 is located on surface 102a of substrate 102. The drain structure 104 includes three n-type doped regions such as a first doping region 104a, a second doping region 104b, and a third doping region 104c.

The first doped region 104a of the drain structure 104 is adjacent to the gate 103 and extends from the substrate surface 102a into the substrate 102 to have a first doping concentration (indicated by N-Drift). The second doped region 104b extends from the substrate surface 102a into the first doped region 104a and is located in the first doped region 104a and has a second doping concentration substantially greater than the first doping concentration N-Drift (indicated by N+). The third doped region 104c is located in the substrate 102, below the first doped region 104a, having a third doping concentration (indicated by N-Well) substantially greater than the first doping concentration N-Drift. In the present embodiment, the second doping concentration N+ is substantially greater than the third doping concentration N-Well, and is suitable for protecting an internal circuit having a high operating voltage. However, in other embodiments, the second doping concentration of the second doping region 104b may be substantially less than or equal to the third doping concentration, and is suitable for protecting an internal circuit having a lower operating voltage.

In addition, the third doping region 104c further has a third lateral dimension D3 of the vertical gate 103; and the third lateral dimension D3 is substantially smaller than the first lateral dimension D1 of the first doping region 104a, and substantially larger than the second doping region. The second lateral dimension D2 of 104b.

The source structure 105 is also an n-type doped region 105a adjacent to the gate 103, which extends from the substrate surface 102a into the substrate 102 and has the same dimensions as the second doped region 104b of the gate structure 104. The second doping concentration N+. The guard ring 106 is composed of a plurality of p-type doped regions (for example, a P+ doped region and a P-Field doped region). In addition, the first doped region 104a further includes a first shallow trench isolation region 107a for isolating the second doped region 104b and the gate 103.

It should be noted that in the present embodiment, the gate-grounded n-type metal-oxide-semiconductor field effect transistor unit 101 belongs to an asymmetric field-scattering metal-oxide-semiconductor field effect transistor. However, in still other embodiments of the present invention, the gate-grounded n-type metal-oxide-semiconductor field effect transistor unit 101 of FIG. 1B may be subjected to a symmetric field-scattering metal-oxide-semiconductor field effect The crystal 201 is replaced.

2 is a cross-sectional view showing the structure of an electrostatic discharge protection device 100 including a symmetric field drift metal-oxide-semiconductor field effect transistor 201, in accordance with another preferred embodiment of the present invention. The structure of the electrostatic discharge protection device 200 is substantially similar to the electrostatic discharge protection device 100 shown in FIG. 1B. The difference between the two is that the symmetric field drift metal-oxide-semiconductor field effect transistor 201 of the ESD protection device 200 has a source structure 205 and a drain structure 104 in addition to the third doping region 104c. Symmetrical, and the asymmetric field drift metal-oxide-semiconductor field effect transistor 101 of the ESD protection device 100 is not.

In the present embodiment, the source structure 205 of the field drift metal-oxide-semiconductor field effect transistor 201 includes an n-type fourth doped region 205a and an n-type fifth doped region 205b. The fourth doped region 205a extends from the substrate surface 102a into the substrate 102 and has the same first doping concentration N-Drift as the first doped region 104a of the gate structure 104; the fifth doped region 205b Extending from the substrate surface 102a into the fourth doped region 205a and having the same second doping concentration N+ as the second doped region 104b of the drain structure 104. The fifth doped region 205b also has a second shallow trench isolation region 107b for isolating the fifth doped region 205b and the gate 103.

Alternatively, a symmetric or asymmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor may be used instead of the gate grounded n-type metal-oxide-semiconductor field effect transistor unit 101. 3 is a cross-sectional view showing the structure of an ESD protection device 300 including an asymmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor 301, in accordance with still another preferred embodiment of the present invention. As shown in FIG. 3, the structure of the ESD protection device 300 is substantially the same as that of the ESD protection device 100 of FIG. 1B except that the asymmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor 301 is The drain structure 304, and the drain structure 104 of the metal-oxide-semiconductor field effect transistor 101, are different.

Like the gate structure 104 of the metal-oxide-semiconductor field effect transistor 101, the drain structure 304 of the asymmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor 301 also includes the first doped region. 304a, the second doped region 304b and the third doped region 304c; and the size and doping concentration of the first doped region 304a, the second doped region 304b, and the third doped region 304c are also substantially similar to those of FIG. 1B. The first doped region 104a, the second doped region 104b, and the third doped region 104c are the same. However, the drain structure 304 does not include shallow trench isolation regions for isolating the second doped region 304b and the gate 103.

Similarly, the symmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor 401 as shown in FIG. 4 can also be used to replace the metal-oxide-semiconductor field effect transistor 101 to form an electrostatic discharge protection device. 400. The drain structure 404 of the symmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor 401 includes a first doped region 404a, a second doped region 404b, and a third doped region 404c; the source structure 405 A fourth doped region 405a and a fifth doped region 405b are included.

Because, when the grounding gate n-type metal-oxide-semiconductor transistor unit used in the ESD protection device, the drain structure only includes one N-type doped in the p-type well of the substrate, and the doping concentration is low. The Drift drift region, as well as a deep doped N+ doped region in the N-Drift drift region. Therefore, when an electrostatic discharge occurs, the first snapback occurs in the N-Drift drift region and the P/N junction of the p-well. Under the influence of the base push-out effect, the second snapback collapses, followed by the junction of the deep doped N+ doped region and the N-Drift drift region, and grounding The final holding voltage of the gate n-type metal-oxide-semiconductor transistor unit is lower than its operating voltage, causing component blocking effect, which in turn causes the electrostatic discharge protection device to fail.

Compared with the above electrostatic discharge protection device, the electrostatic discharge protection devices 100, 200, 300 and 400 provided by the embodiments of the present invention further provide a doping concentration substantially larger than the N-Drift below the n-type drift region. The N-type well of the drift region causes the position where the first snapback occurs to migrate to the P/N junction of the N-well and the p-well. Because the higher concentration N-well is located below the N-Drift drift region, the N-type well can be formed while increasing the doping concentration of the N-Drift drift region and reducing the N+ and N-Drift drift regions of the n-doped region. The difference in doping concentration between the two, so that the second sudden collapse phenomenon does not occur, and the first sudden collapse phenomenon is maintained at the P/N junction of the N-well and the p-type well, and no longer shifts. The junction to the N+ doped region and the N-Drift drift region. Due to the deeper N-type well and the P/N junction of the p-type well, the channel path of the ground gate n-type metal-oxide-semiconductor transistor unit can be extended, and the on-resistance can be improved to make the ground gate n-type metal- The holding voltage of the oxide-semiconductor transistor unit is higher than the operating voltage, which improves its resistance to electrostatic discharge and makes it increase in proportion as the size of the element increases.

The electrostatic discharge protection devices 100, 200, 300, and 400 provided by the above embodiments can be integrated into other integrated circuits, such as power supply circuits or input/output circuits, to protect the integrated circuit from electrostatic discharge damage. Please refer to FIG. 5. FIG. 5 is a circuit diagram of an ESD protection circuit 500 for protecting a liquid crystal display driving wafer according to a preferred embodiment of the present invention. The power supply circuit or the input/output circuit for protecting the liquid crystal display driving chip is protected from electrostatic discharge.

In the present embodiment, the ESD protection circuit 500 includes a plurality of clamping devices 501 and 502 respectively composed of the n-type metal-oxide-semiconductor field effect transistor unit 101 provided by the above embodiments, and a gate. A clamping device 503, 504 of a power p-type metal-oxide-semiconductor field effect transistor unit is connected.

Wherein, the gates and sources of the clamping devices 501 and 502 are coupled to the low voltage power supply VSS and can be connected to the ground level; the connection points of the drain electrodes are respectively coupled to the bonding pads of the input/output circuit or Terminals 507a and 507b. The gates and the sources of the clamping devices 503 and 504 are respectively coupled to the first high voltage power source VDD_LV and the second high voltage power source VDD_HV, and the voltage of the second high voltage power source VDD_HV is greater than the first high voltage power source VDD_LV; Connected to pads 507a and 507b.

Under normal operation, the clamping devices 501, 502, 503504 are in a closed state to avoid affecting the input/output circuitry. When the electrostatic discharge voltage appears in the pads 507a and 507b of the input/output circuit, 501, 502, 503, 504 are turned on, so that the electrostatic discharge current can be conducted to the low-voltage power source VSS, thereby constituting the static electricity of the input/output circuit 508. Discharge protection.

In addition, the clamping devices 505 and 506 can also be coupled to the second high voltage power source VDD_HV, the first high voltage power source VDD_LV and the low voltage power source VSS in a similar manner as the electrostatic discharge protection of the power circuit.

According to the above embodiment, the present invention provides an electrostatic discharge protection device comprising a metal-oxide-semiconductor conductor unit. The second is reduced by adding a doping region having a higher doping concentration than the drain drift region below the drain drift region of the metal-oxide-semiconductor conductor unit and having the same electrical conductivity as the drain drift region. The probability of a sudden crash. Turning on the N-type metal-oxide-semiconductor transistor, only one snapback occurs, and has a holding voltage higher than its operating voltage to enhance the resistance of the metal-oxide-semiconductor transistor to electrostatic discharge current . Moreover, the ability of the metal-oxide-semiconductor transistor to withstand electrostatic discharge current can be increased in proportion as the size of the element increases. If it is used in an electrostatic discharge protection device having a plurality of finger-shaped transistor units, the respective finger-shaped transistor units can be uniformly turned on to collectively unload the electrostatic discharge current, thereby achieving the above object.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100. . . Electrostatic discharge protection device

101. . . Gate grounded n-type metal-oxide-semiconductor field effect transistor unit

102. . . Substrate

102a. . . Substrate surface

103. . . Gate

104. . . Bungee structure

104a. . . First doped region

104b. . . Second doped region

104c. . . Third doped region

105. . . Source structure

105a. . . N-doped region

106. . . Protective ring

107a. . . First shallow trench isolation zone

107b. . . Second shallow trench isolation zone

111. . . Gate grounded n-type metal-oxide-semiconductor field effect transistor unit

200. . . Electrostatic discharge protection device

201. . . Symmetric field drift metal-oxide-semiconductor field effect transistor

205. . . Source structure

205a. . . Fourth doped region

205b. . . Fifth doped region

300. . . Electrostatic discharge protection device

301. . . Asymmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor

304. . . Bungee structure

304a. . . First doped region

304b. . . Second doped region

304c. . . Third doped region

400. . . Electrostatic discharge protection device

401. . . Symmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor

404. . . Bungee structure

404a. . . First doped region

404b. . . Second doped region

404c. . . Third doped region

405. . . Source structure

405a. . . Fourth doped region

405b. . . Fifth doped region

500. . . Electrostatic discharge protection circuit

501. . . Clamping device

502. . . Clamping device

503. . . Clamping device

504. . . Clamping device

505. . . Clamping device

506. . . Clamping device

507a. . . Solder pad

507b. . . Solder pad

1B‧‧‧ tangent

D1‧‧‧ first horizontal dimension

D2‧‧‧ second horizontal dimension

D3‧‧‧ third horizontal size

HVPW‧‧‧High voltage p-type well

N-Drift‧‧‧first doping concentration

N+‧‧‧second doping concentration

N-Well‧‧‧ third doping concentration

P+‧‧‧ doped area

P-Field‧‧‧Doped area

VDD_LV‧‧‧First high voltage power supply

VDD_HV‧‧‧second high voltage power supply

VSS‧‧‧Low-voltage power supply

1A is a top plan view showing the structure of an electrostatic discharge protection device according to a preferred embodiment of the present invention.

1B is a cross-sectional view showing the structure of the ESD protection device taken along line 1B of FIG. 1A.

2 is a cross-sectional view showing the structure of an electrostatic discharge protection device including a symmetric field drift metal-oxide-semiconductor field effect transistor according to another preferred embodiment of the present invention.

3 is a cross-sectional view showing the structure of an ESD protection device including an asymmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor according to another preferred embodiment of the present invention.

4 is a cross-sectional view showing the structure of an electrostatic discharge protection device including a symmetric double-diffused drain structure metal-oxide-semiconductor field effect transistor according to still another preferred embodiment of the present invention.

FIG. 5 is a schematic diagram of an ESD protection circuit for protecting a liquid crystal display driving wafer according to a preferred embodiment of the present invention.

100. . . Electrostatic discharge protection device

101. . . Gate grounded n-type metal-oxide-semiconductor field effect transistor unit

102. . . Substrate

102a. . . Substrate surface

103. . . Gate

104. . . Bungee structure

104a. . . First doped region

104b. . . Second doped region

104c. . . Third doped region

105. . . Source structure

105a. . . N-doped region

106. . . Protective ring

107a. . . First shallow trench isolation zone

111. . . Gate grounded n-type metal-oxide-semiconductor field effect transistor unit

D1. . . First lateral dimension

D2. . . Second lateral dimension

D3. . . Third lateral dimension

HVPW. . . High voltage p-well

N-Drift. . . First doping concentration

N+. . . Second doping concentration

N-Well. . . Third doping concentration

P+. . . Doped region

P-Field. . . Doped region

Claims (17)

An electrostatic discharge (ESD) protection device comprising: a substrate having a first electrical property; a gate disposed on a surface of the substrate; and a drain structure having a second electrical property The method includes a first doped region adjacent to the gate and extending from the surface into the substrate and having a first doping concentration, and a second doped region extending from the surface into the first a doped region located in the first doped region and having a second doping concentration substantially greater than the first doping concentration; and a third doped region located in the substrate, first a third doping concentration substantially greater than the first doping concentration, wherein the third doping concentration is substantially greater than the second doping concentration; and a source structure adjacent to the gate, And located in the substrate, having the second electrical property. The electrostatic discharge protection device of claim 1, further comprising a first shallow trench isolation layer disposed in the first doped region and isolating the second doped region from the gate. The electrostatic discharge protection device described in claim 1 is a double-diffused-drain metal-Oxide-Semiconductor Field-Effect-Transistor (DDD). NMOS FET), or a drift metal-oxide-semiconductor field effect transistor (Field-Drift) Metal-Oxide-Semiconductor Field-Effect-Transistor, FD-MOSFET). The electrostatic discharge protection device of claim 1, wherein the source structure comprises: a fourth doping region adjacent to the gate and extending from the surface into the substrate, and having the first a doping concentration; and a fifth doping region extending from the surface into the fourth doping region and having the second doping concentration. The electrostatic discharge protection device of claim 4, further comprising a second shallow trench isolation layer, located in the fourth doped region, and isolating the fifth doped region from the gate. The electrostatic discharge protection device of claim 1, wherein the third doped region has a third lateral dimension perpendicular to the gate; the third lateral dimension is substantially smaller than a first doped region A lateral dimension, and substantially greater than a second lateral dimension of the second doped region. An electrostatic discharge protection circuit for protecting an internal circuit, the ESD protection circuit comprising: a metal-oxide-semiconductor conductor transistor unit coupled to the internal circuit, the metal-oxide-semiconductor conductor transistor unit comprising a substrate having a first electrical property; a gate on a surface of the substrate; a drain structure having a second electrical property, the drain structure comprising: a first doped region adjoins the gate and extends from the surface into the substrate and has a first doping concentration; a second doped region extending from the surface into the first doping a region having a second doping concentration substantially greater than the first doping concentration; and a third doping region located in the substrate, the lower portion of the first doping region having substantially greater than the first a third doping concentration of the doping concentration; and a source structure adjacent the gate and located in the substrate to have the second electrical property. The electrostatic discharge protection circuit of claim 7, wherein the internal circuit is a power circuit or an I/O circuit. The electrostatic discharge protection circuit of claim 7, wherein the third doping concentration is substantially greater than the second doping concentration. The electrostatic discharge protection circuit of claim 7, wherein the third doping concentration is substantially equal to or less than the second doping concentration. The electrostatic discharge protection device of claim 7, further comprising a first shallow trench isolation layer located in the first doped region and isolating the second doped region from the gate. The electrostatic discharge protection circuit according to claim 7, wherein the gate metal-oxide-semiconductor conductor transistor unit is a double diffusion gate structure Metal-oxide-semiconductor field effect transistor, or a drift metal-oxide-semiconductor field effect transistor. The electrostatic discharge protection circuit of claim 7, wherein the source structure comprises: a fourth doped region adjacent to the gate and extending from the surface into the substrate, and having the first a doping concentration; and a fifth doping region extending from the surface into the fourth doping region and having the second doping concentration. The electrostatic discharge protection circuit of claim 13 further comprising a second shallow trench isolation layer disposed in the fourth doped region and isolating the fifth doped region from the gate. The electrostatic discharge protection circuit of claim 7, wherein the third doped region has a third lateral dimension perpendicular to the gate; the third lateral dimension is substantially smaller than one of the first doped regions The first lateral dimension is substantially greater than a second lateral dimension of the second doped region. The electrostatic discharge protection circuit according to claim 7, wherein the metal-oxide-semiconductor conductor transistor unit is a gate grounded n-type metal-oxide-semiconductor (Gate Ground n-Type Metal-Oxide). a -Semiconductor, GGNMOS) field effect transistor, and the source structure and the gate are grounded, and the gate structure is coupled to a VDD power line or a pad of the internal circuit. The electrostatic discharge protection circuit according to claim 7, wherein the metal-oxide-semiconductor conductor transistor unit is a gate connected to a power source p-type metal-oxide-semiconductor (Gate VDD P-Type Metal- Oxide-Semiconductor Field-Effect-Transistor, GDPMOS) field-effect transistor, the source structure and the gate are coupled to a VDD power line of the internal circuit, and the drain structure and a VSS power line of the internal circuit Or a pad is coupled.