TWI506784B - Semiconductor device - Google Patents

Description

Semiconductor component

The present invention relates to a semiconductor element, and more particularly to a semiconductor element used in an integrated circuit.

In the process of packaging, testing, and transportation of integrated circuit chips, static electricity accumulated in the human body and the instrument will instantaneously cause electrostatic discharge (ESD) when these objects are in contact with the integrated circuit chip, so that the integrated circuit is formed. The circuit components in the wafer are damaged by unrecoverable, which in turn affects the function of the integrated circuit.

Therefore, in order to prevent the circuit components in the integrated circuit chip from being damaged by the electrostatic discharge, the designer adds an electrostatic discharge protection circuit to the integrated circuit component, and the high voltage semiconductor component currently used to complete the electrostatic discharge protection circuit is common. A laterally diffused NMOS (LDNMOS). Nowadays, the structure of high-voltage semiconductor components generally has a phenomenon of insufficient withstand voltage, and how to improve the lack of such conventional components in the case of increasingly smaller component size requirements is the main purpose of the development of the present case.

It is an object of the present invention to provide a semiconductor component that enhances the ability of electrostatic discharge protection.

In order to achieve the above advantages, in an embodiment of the present invention, a semiconductor device including a substrate, a gate structure, a source structure, and a drain structure is provided. The substrate has a deep well region, the gate structure is disposed above the deep well region, and the source structure is disposed in the deep well region, and is located on the first side of the gate structure, the drain structure is disposed in the deep well region, and the gate structure is located The second side. The first electrode includes a first electrically doped region, a first electrode and a second electrically doped region, wherein the first electrically doped region is located in the deep well region, and the first electrode is electrically connected to the first electrically doped region The second electrically doped region is disposed in the first electrically doped region and is located between the first electrode and the gate structure.

In another embodiment of the invention, the substrate is a germanium substrate.

In another embodiment of the present invention, the deep well region is an N-type deep well region, and the first electrically-doped region includes an N-type gradation region and a first high-concentration N-type region, and the first high-concentration N-type region The region is located in the N-type gradation region, and the second electrically-doped region is the first high-concentration P-type region, and the first high-concentration P-type region is located in the first high-concentration N-type region.

In another embodiment of the present invention, the first high-concentration P-type region includes a plurality of high-concentration P-type sub-regions separated from each other, and the high-concentration P-type sub-regions are arranged in the high-concentration N-type region.

In another embodiment of the invention, the source structure includes a P-type base region, a second high-concentration N-type region, a second electrode, and a second high-concentration P-type region. Wherein the P-type base region is located in the deep well region, the second high-concentration N-type region is disposed in the P-type base region, and the second electrode is electrically connected to the second high-concentration N-type region, and the second high-concentration P-type region is configured In the second high concentration N-type region.

In another embodiment of the invention, the first electrode is electrically connected to the anode for supplying an operating voltage, and the second electrode is electrically connected to the cathode to provide a ground voltage.

In another embodiment of the present invention, the first high concentration P-type region and the second high concentration P-type region have the same P-type doping concentration and the same set depth.

In another embodiment of the invention, the gate structure includes a gate insulating layer and a gate conductor layer, and the gate insulating layer is located between the deep well region and the gate conductor layer.

In another embodiment of the invention, the semiconductor component described above is completed in an electrostatic discharge protection circuit.

In another embodiment of the invention, a guard ring is disposed around the semiconductor component.

In another embodiment of the invention, the first electrical property is different from the second electrical property.

In the semiconductor device of the present invention, the high concentration P-type region is doped in the drain structure to enhance the electrostatic discharge protection capability.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1 is a top plan view of a laterally diffused N-type MOS device for use in an ESD protection circuit, and FIG. 2 is a cross-sectional structural view taken along line AA' of FIG. 1. The laterally diffused N-type MOS device 1 is mainly located in a region defined by a guard ring 19 in the substrate 10, and an N-type deep well region (Den N-Well, DNW) 11 and a gate structure 12 are completed in the region. The source structure 13 and the drain structure 14 include a N-type 141, a high-concentration N-type region (N+) 142, and a drain electrode 143. The problem that the component withstand voltage is insufficient can be improved by widening the distance Dcg between the gate electrode 12 and the gate structure 12 and the x-direction, so that the completed electrostatic discharge protection circuit can pass various types of electrostatic discharge tests, such as the human body. Human body model (HBM) and machine model (MM), etc.

However, it can be seen from the experimental data of the above various types of electrostatic discharge tests that when the distance Dcg is amplified to a certain value, the withstand voltage capability of the component can no longer be increased or even decreased. This phenomenon is caused by the fact that the strong electric field generated in the element adjacent to the N-type gradation region 141 and the high-concentration N-type region 142 is too close to the gate structure 12 when the ESD protection circuit operates, resulting in insulation in the gate structure 12. The layer begins to leak due to a strong electric field. In order to improve this deficiency, the inventors propose another embodiment.

3 is a top plan view of a semiconductor device according to another embodiment of the present invention. Figure 4 is a schematic cross-sectional view taken along line AA' of Figure 3. Referring to FIG. 3 and FIG. 4, the semiconductor device 2 of the present embodiment is mainly completed in a region defined by a guard ring 29 in the substrate 20, and the deep well region 21, the gate structure 22, and the source structure 23 are completed in the region. And the drain structure 24, wherein the gate structure 22 is disposed above the deep well region 21, the source structure 23 is disposed in the deep well region 21, and is located at the first side 22a of the gate structure 22, and the drain structure 24 is disposed in the deep well region 21 And located on the second side 22b of the gate structure 22. The drain structure 24 includes a first electrically doped region 241 , a first electrode 242 and a second electrically doped region 243 , wherein the first electrically doped region 241 is located in the deep well region 21 and is electrically coupled to the first electrode 242 . The second electrically doped region 243 is disposed in the first electrically doped region 241 and is located between the first electrode 242 and the gate structure 22 . In the present embodiment, the gate structure 22 includes a gate insulating layer 221 and a gate conductor layer 222, and the gate insulating layer 221 is located between the deep well region 21 and the gate conductor layer 222.

This embodiment also exemplifies a laterally diffused N-type MOS device, wherein the substrate 20 is, for example, a ruthenium substrate, the deep well region 21 is, for example, an N-type deep well region, and the first electrically doped region 241 includes an N-type gradation region 241a. And a first high concentration N-type region 241b, wherein the first high concentration N-type region 241b is located in the N-type gradation region 241a, and the N-type doping concentration of the first high-concentration N-type region 241b is larger than the N-type gradation region 241a high.

In this embodiment, a second electrically doped region 243 is disposed in the first high concentration N-type region 241b, for example, a first high-concentration P-type region formed by doping P-type impurity boron, and the structure is mainly used to avoid The N-type gradation region 241a and the first adjacent portion 25 of the first high-concentration N-type region 241b form a maximum electric field, and move the maximum electric field formation to the first high-concentration N-type region 241b and the second electrical doping The second adjacent portion 26 of the region 243 is moved away from the relatively fragile gate structure 22 to avoid a strong electric field from damaging the gate structure 22. Therefore, the present invention has the object of enhancing the performance of the electrostatic discharge protection circuit.

In this embodiment, the source structure 23 may include a P-type base region 231, a second high-concentration N-type region 232, a second electrode 233, and a second high-concentration P-type region 234, wherein the P-type base region 231 is located in the deep well region. 21, the second high-concentration N-type region 232 is disposed in the P-type base region 231, mainly for use as a source contact region, and the second electrode 233 is electrically connected to the second high-concentration N-type region 232, and The two high concentration P-type regions 234 are disposed in the second high concentration N-type region 232, mainly for use as a body contact region. In addition, the first electrode 242 of the embodiment is electrically connected to the anode for providing an operating voltage, the second electrode 233 is electrically connected to the cathode to provide a ground voltage, and when the electrostatic discharge state occurs, the semiconductor component 2 of the present invention can be A current path is formed between the anode and the cathode to direct the electrostatic current.

It is noted that the second electrically doped region 243 of the drain structure 24 (ie, the first high concentration P-type region in this example) and the second high concentration P-type region 234 of the source structure 23 are implanted. The second photo-doped region 243 and the second high-concentration P-type region 234 may have the same doping concentration, and the set depth may be the same, and the photomask may not be additionally added to be particularly completed. Accordingly, the embodiment can effectively save the number of masks.

In addition, the second electrically doped region 243 can be rectangular or other shape, but the second electric doping region 243 can be blocked between the first electrode 242 and the gate structure 22, thereby forming a maximum electric field. The distance between the gate structure 22 and the gate structure 22 can be improved. Therefore, the second electrical doping region 243 can have other shapes and configurations.

For example, as shown in FIG. 5 , which is a top view of another example of the shape of the second electrically doped region, the second electrically doped region between the first electrode 242 and the gate structure 22 ( FIGS. 3 and 4 ) may be The three high-concentration P-type sub-regions 31, 32, and 33 are separated from each other, and may be rectangular in shape, but are not limited thereto. The three high-concentration P-type sub-regions 31, 32, and 33 are arranged in parallel at the first high concentration N. In the type area 341. The three high-concentration P-type sub-regions are separated from each other and are not adjacent to each other, so that the structure of any of the sub-regions is incomplete and the barrier effect cannot be effectively achieved. In addition, the arrangement of the high-concentration P-type sub-regions may also vary. As shown in FIG. 6, the second electrically-doped region includes, for example, five high-concentration P-type sub-regions 41, 42, 43, 44 separated from each other. And 45, five sub-regions parallel to each other are staggered in the first high-concentration N-type region 441, and the barrier effect is also effectively achieved. According to the technical features of the invention, the number of high-concentration P-type sub-regions is not limited, in other words, the number of the invention does not affect the purpose of the invention.

Further, the present invention is not limited to the N-type MOS device, and for example, it can be applied to a P-type MOS device, and it is only necessary to replace the electrical properties of the doping impurities.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1. . . Lateral diffusion N-type MOS device

2. . . Semiconductor component

10, 20. . . Substrate

11, 21. . . Deep well area

12, 22. . . Gate structure

13,23. . . Source structure

14, 24. . . Bungee structure

141, 241a. . . N-type gradation zone

142, 241b, 232, 341, 441. . . High concentration N-type zone

143, 233, 242. . . electrode

15, 25, 26. . . Adjacent

22a. . . First side

22b. . . Second side

221. . . Gate insulation

222. . . Gate conductor layer

231. . . P-type base area

234. . . Second high concentration P-type zone

241. . . First electrically doped region

243, 343, 443. . . Second electrically doped region

31, 32, 33, 41, 42, 43, 44, 45. . . High concentration P-type sub-region

19, 29. . . Guard ring

Dcg. . . distance

1 is a top plan view of a laterally diffused N-type MOS device.

Figure 2 is a schematic cross-sectional view taken along line AA' of Figure 1.

3 is a top plan view of a semiconductor device in accordance with an embodiment of the present invention.

Figure 4 is a schematic cross-sectional view taken along line AA' of Figure 3.

5 is a top plan view showing a second electrically doped region in a semiconductor device according to another embodiment of the present invention.

6 is a top plan view showing a second electrically doped region in a semiconductor device according to another embodiment of the present invention.

2. . . Semiconductor component

20. . . Substrate

twenty one. . . Deep well area

twenty two. . . Gate structure

twenty three. . . Source structure

twenty four. . . Bungee structure

233, 242. . . electrode

25, 26. . . Adjacent

22a. . . First side

22b. . . Second side

221. . . Gate insulation

222. . . Gate conductor layer

231. . . P-type base area

234. . . Second high concentration P-type zone

241. . . First electrically doped region

241a. . . N-type gradation zone

241b, 232. . . High concentration N-type zone

243. . . Second electrically doped region

Claims (11)

A semiconductor component comprising: a substrate having a deep well region; a gate structure disposed above the deep well region; a source structure disposed in the deep well region and located at one of the gate structures One side; and a drain structure disposed in the deep well region and located on a second side of the gate structure, the drain structure comprising: a first electrically doped region located in the deep well region; a first electrode electrically connected to the first electrically doped region; and a second electrically doped region disposed in the first electrically doped region and located at the first electrode and the gate structure between. The semiconductor device of claim 1, wherein the substrate is a germanium substrate. The semiconductor device of claim 1, wherein the deep well region is an N-type deep well region, the first electrically-doped region includes an N-type gradation region and a first high-concentration N-type region, and The first high concentration N-type region is located in the N-type gradation region, and the second electrically-doped P-region is a first high-concentration P-type region, and the first high-concentration P-type region is located at the first high Concentration in the N-type zone. The semiconductor device of claim 3, wherein the first high-concentration P-type region comprises a plurality of high-concentration P-type sub-regions separated from each other, and the high-concentration P-type sub-regions are arranged in the first High concentration in the N-type zone. The semiconductor device of claim 3, wherein the source structure comprises: a P-type base region located in the deep well region; and a second high concentration N-type region disposed in the P-type base region; a second electrode electrically connected to the second high concentration N-type region; and a second high concentration P-type region disposed in the second high concentration N-type region. The semiconductor device of claim 5, wherein the first electrode is electrically connected to an anode for providing an operating voltage, and the second electrode is electrically connected to a cathode to provide a ground voltage. The semiconductor device of claim 5, wherein the first high concentration P-type region and the second high concentration P-type region have the same P-type doping concentration and the same set depth. The semiconductor device of claim 1, wherein the gate structure comprises a gate insulating layer and a gate conductor layer, and the gate insulating layer is located between the deep well region and the gate conductor layer. The semiconductor component of claim 1, wherein the semiconductor component is completed in an electrostatic discharge protection circuit. A semiconductor component according to claim 1, wherein a guard ring is disposed around the semiconductor component. The semiconductor component of claim 1, wherein the first electrical property is different from the second electrical property.