TWI449150B - Esd protection device structure - Google Patents

Description

Electrostatic discharge protection component structure

The present invention relates to an electrostatic discharge protection element structure, and more particularly to an electrostatic discharge protection element structure of a gate-grounded MOS transistor.

Electrostatic discharge (ESD) phenomenon is a common phenomenon in semiconductor manufacturing process, and the excess charge caused by it will be transmitted through the input/output (I/O) pin of the integrated circuit in a very short time. In the integrated circuit, the internal circuit of the integrated circuit is destroyed. In order to solve this problem, the industry usually sets an ESD protection device between the internal circuit and the I/O pin, which must be started before the electrostatic discharge pulse reaches the internal circuit to quickly eliminate the excessively high The voltage, which in turn reduces the damage caused by the electrostatic discharge phenomenon.

In recent years, in order to avoid internal circuit damage caused by electrostatic discharge phenomena, conventional ESD protection devices utilize a PMOS transistor and an NMOS transistor to protect internal circuits. In general, the discharge path of the ESD protection device includes four modes, namely, a PS (positive to VSS) mode, an NS (negative to VSS) mode, a PD (positive to VDD) mode, and an ND (negative to VDD) mode, wherein the PD, The NS mode utilizes a parasitic diode in a PMOS transistor and an NMOS transistor to achieve ESD protection, while the ND and PS modes utilize a parasitic bipolar junction transistor in a PMOS transistor and an NMOS transistor (parasitic Bipolar transistor) to protect the internal circuit. However, since the turn-on voltage of the parasitic bipolar transistor is high, when the integration degree of the integrated circuit is increased and the process level is reduced, the thickness of the gate dielectric layer under the gate becomes small, which causes the breakdown voltage thereof. The (breakdown voltage) also decreases, so that the gate dielectric layer cannot withstand high voltage and damage, greatly reducing the protection function of the conventional ESD protection device.

Therefore, how to provide an effective ESD protection device for integrated circuits under the space limitation of the process level is still an important issue in the industry.

One of the objects of the present invention is to provide an electrostatic discharge (ESD) protection element structure to improve the pulse voltage that the ESD protection element structure can withstand in the human body discharge mode and in the machine discharge mode.

In order to achieve the above object, the present invention provides an ESD protection device structure disposed on a semiconductor substrate, and the electrostatic discharge protection device structure includes a well region having a first conductivity type disposed in the semiconductor substrate. a first doped region having a second conductivity type disposed in the well region, a second doped region having a first conductivity type, and a third doped region having a second conductivity pattern disposed in the well In the area. The first doped region encapsulates the second doped region such that the first doped region and the second doped region constitute a vertical bipolar junction transistor (vertical BJT), and the first doped region, the well The region and the third doped region constitute a horizontal type bipolar junction transistor (lateral BJT).

The invention forms a second doped region with different conductivity patterns in the first heavily doped region and the first drift region of the ESD protection device structure to improve the secondary breakdown current of the ESD protection component structure and reduce the trigger voltage, thereby improving The pulse voltage that the ESD protection component structure can withstand.

Please refer to FIG. 1. FIG. 1 is a cross-sectional view showing the structure of an electrostatic discharge (ESD) protection element according to a first embodiment of the present invention. As shown in FIG. 1, the ESD protection device structure 10 is disposed on a semiconductor substrate 12, and the ESD protection device structure 10 includes a well region 14, a drain region 16, a source region 18, and a gate dielectric. Layer 20, a gate electrode 22, and a doped region 24. The well region 14 has a first conductivity type, such as an N-type or a P-type, and is disposed in the semiconductor substrate 12. The drain region 16 and the source region 18 are respectively disposed in the well region 14, and the drain region 16 has a second conductivity type, and the source region 18 also has a second conductivity pattern.

In the first embodiment, the first conductivity type is P type, and the second conductivity type is N type. Conversely, when the first conductivity type is N type, the second conductivity type may be P type. The gate dielectric layer 20 is disposed on the surface of the semiconductor substrate 12 between the drain region 16 and the source region 18, and the gate electrode 22 is disposed on the gate dielectric layer 20 to enable the drain region 16 and the source. The pole region 18, the well region 14, the gate dielectric layer 20, and the gate electrode 22 constitute an N-type MOS transistor. The doped region 24 is disposed in the well region 14 and electrically connected to a ground terminal 26 for electrically connecting the well region 14 to the ground terminal 26 as a body electrode of the MOS transistor. 46.

In addition, the drain region 16 may include an N-type first heavily doped region 28 and an N-type first drift region 30, and the first heavily doped region 28 is disposed above the first drift region 30. The first heavily doped region 28 is electrically connected between an internal circuit 31 to be protected and an input/output (I/O) conductive pad 32. The source region 18 may also include an N-type second heavily doped region 34 and an N-type second drift region 36, and the second heavily doped region 34 is disposed above the second drift region 36 and electrically Connected to ground terminal 26. It can be seen that the ESD protection device structure 10 of the present embodiment is a gate-grounded N-type MOS transistor. In addition, the ESD protection component structure 10 may further include a first isolation structure 38, a second isolation structure 40, and a third isolation structure 42. The first isolation structure 38 surrounds the first heavily doped region 28. The second isolation structure 40 is disposed in the source region 18. The third isolation structure 42 surrounds the doped region 24 to isolate the doped region 24 from the MOS transistor.

The relationship between the pulse voltage and the pulse current in the transmission line pulse (TLP) test of the ESD protection component structure of the present embodiment will be further described below to simulate the range that the ESD protection component structure can withstand during the electrostatic discharge process. Furthermore, the ESD protection capability of the ESD protection component structure will be explained. Please refer to FIG. 2 to FIG. 4 . FIG. 2 is a schematic diagram of the circuit of the ESD protection component structure according to the first embodiment of the present invention during TLP testing, and FIG. 3 is a schematic diagram of the ESD protection component structure of the first embodiment of the present invention. The relationship between the pulse voltage and the pulse current in the test and the relationship between the leakage current and the pulse current of the gate electrode, and FIG. 4 is a diagram showing the relationship between the operating voltage and the operating current of the structure of the ESD protection element according to the first embodiment of the present invention. As shown in FIG. 2, during testing, the drain region 16 of the ESD protection device structure 10 is electrically connected to one end of the TLP generator 44, and the source region 18, the gate electrode 22, and the base of the ESD protection device structure 10. The pole 46 is electrically connected to the ground, and the other end of the TLP generator 44 is electrically connected to the ground. As shown in Fig. 3, the secondary breakdown current It2 is a pulse current value when the leakage current of the ESD protection element structure 10 at the gate electrode 22 is 10 ^-6 A. The secondary breakdown current It2 of the ESD protection element structure 10 of the present embodiment is approximately 1.5 A, whereby the pulse voltage of the ESD protection element structure 10 under the Human-Body Model (HBM) can be withstand 1 kV. The ESD protection component structure 10 can withstand a pulse voltage of 275V in the Machine Model (MM). In addition, the trigger voltage Vt1 of the ESD protection component structure 10 can also be approximately 50V from FIG. 3, which means that when the ESD pulse voltage exceeds 50V, the ESD protection component structure 10 is turned on and ESD protection is started. . Further, as shown in Fig. 4, the holding voltage of the ESD protection element structure 10 is approximately 25 V, so that the power consumption (power = ESD current × holding voltage) of the ESD protection element structure 10 can be obtained.

However, the industry's ESD protection specification in human discharge mode is 2kV, so to comply with the industry's ESD protection specifications, the above embodiments still need to improve ESD protection. In order to improve the ESD protection capability, the present invention implants a doped region having a second conductivity type in the drain region, so that the drain region forms a vertical bipolar junction transistor (vertical BJT), thereby improving ESD protection capabilities.

Please refer to FIG. 5. FIG. 5 is a cross-sectional view showing the structure of an ESD protection element according to a second embodiment of the present invention. As shown in FIG. 5, the ESD protection device structure 100 is disposed on a semiconductor substrate 102, and the ESD protection device structure 100 includes a well region 104 having a first conductivity type and a second conductivity pattern for A first doped region 106 as a drain, a second doped region 108 having a first conductive form, and a third doped region 110 having a second conductivity type for use as a source. Similarly, if the first conductivity type is a P type, the second conductivity type is an N type, and conversely, when the first conductivity type is an N type, the second conductivity type may be a P type.

Taking the first conductivity type as the P type as an example, the well region 104 is a high voltage P-well (HVPW) disposed in the semiconductor substrate 102. The N-type first doped region 106 is disposed in the well region 104 and is electrically It is connected to an internal circuit 111 to be protected and an I/O conductive pad 112. The first doped region 106 includes an N-type first heavily doped region 114 and an N-type first drift region 116, and the first heavily doped region 114 is disposed above the first drift region 116. It is noted that the first doped region 106 is covered with the P-type second doped region 108, a portion of the first doped region 106 is disposed on the second doped region 108, and the first doped region 106 is Another portion of the portion is disposed below the second doped region 108. In this embodiment, the second doped region 108 is disposed between the first heavily doped region 114 and the first drift region 116, and completely separates the first heavily doped region 114 from the first drift region 116 region. The first doped region 106 and the second doped region 108 form an npn-type bipolar junction transistor, and is a vertical bipolar junction transistor 118. In the present embodiment, the first heavily doped region 114 is electrically connected to the I/O conductive pad 112, thereby introducing or deriving an ESD current. The N-type third doping region 110 is disposed in the well region 104 on one side of the first doping region 106, and the well region 104 is disposed between the first doping region 106 and the third doping region 110, so that The first doped region 106, the well region 104, and the third doped region 110 constitute another npn-type bipolar junction transistor, and is a horizontal type bipolar junction transistor (lateral BJT) 120. The third doped region 110 includes an N-type second heavily doped region 122 and an N-type second drift region 124, wherein the second heavily doped region 122 is disposed above the second drift region 124 and is electrically Connected to a ground terminal 126. In this embodiment, the second doping region 110 has a P-type doping, and can be formed by a P-type ESD implantation process, for example, a boron ion implantation process, and can be controlled by adjusting the energy of the implant. The depth of the doped region 110 in the semiconductor substrate 102.

In addition, the ESD protection device structure 100 of the present embodiment further includes a P-type fourth doping region 128, and is disposed in the well region 104 and electrically connected to the ground terminal 126 for electrically connecting the ground terminal 126. And the well region 104, such that the base of the horizontal type bipolar junction transistor 120 formed by the first doping region 106, the well region 104, and the third doping region 110 can pass through the well region 104 and the fourth The doped region 128 is electrically connected to the ground terminal 126, wherein the well region 104 between the horizontal bipolar junction transistor 120 and the fourth doped region 128 constitutes a resistor R _HVPW . When the voltage across the resistor R _HVPW is greater than the cut-in voltage of the horizontal bipolar junction transistor 120, the horizontal bipolar junction transistor 120 is turned on. The fourth doped region 128 of the present embodiment may include a third heavily doped region 130 and a third drift region 132. The third heavily doped region 130 is disposed above the third drift region 132 and electrically connected. To ground 126. However, the present invention is not limited to the fourth doped region 128 to include a heavily doped region and a drift region or the fourth doped region 128 is a P-type doped region, and the fourth doped region 128 may also be only a well. The regions 104 are doped regions of the same conductive form.

In the present embodiment, the ESD protection device structure 100 further includes a gate dielectric layer 134 and a gate electrode 136. The gate dielectric layer 134 is disposed on the surface of the semiconductor substrate 102 and is located in the N-type first doping. The impurity region 106 is between the N-type third doping region 110. The gate dielectric layer 134 of the present embodiment partially covers the first doping region 106 and the third doping region 110, but the invention is not limited thereto. The gate electrode 136 is disposed on the gate dielectric layer 134 to make the gate The dielectric layer 134, the gate electrode 136, the N-type first doped region 106, the N-type third doped region 110, and the P-type well region 104 constitute an N-type MOS transistor. Wherein, the first doping region 106 is used as a drain of the MOS transistor, and the third doping region 110 is used as a source of the MOS transistor, and the well region 104 is adjacent to the gate dielectric. The region of layer 134 acts as a channel region for the MOS transistor. In addition, the gate electrode 136 is electrically connected to the ground terminal 126 to allow the N-type MOS transistor to be turned off when no ESD is generated.

In addition, the ESD protection component structure 100 further includes a first isolation structure 138, a second isolation structure 140, and a third isolation structure 142. The first isolation structure 138 surrounds the first heavily doped region 114 for isolating the sidewall of the first heavily doped region 114 from the first drift region 116 such that the ESD current entering by the first heavily doped region 114, The first doped region 108 having the second conductivity type is first passed through the path of the first drift region 116, the well region 104, and the third doping region 110 of the horizontal bipolar junction transistor 120. Lead to ground 126. Moreover, when the ESD having the high pulse voltage enters the first heavily doped region 114, the first isolation structure 138 can effectively protect the gate dielectric layer 134 to avoid ESD damage, thereby improving the ESD protection device structure 100 in I/O conduction. The ESD pulse voltage that the pad 112 can withstand. The second isolation structure 140 is disposed in the third doping region 110 and is located between the junction of the second heavily doped region 122 and the ground terminal 126 and the second drift region 124 below the gate electrode 136. Avoid entering ESD damage from ground 126 with high voltage Gate dielectric layer 134. The third isolation structure 142 surrounds the P-type fourth doping region 128 for isolating the fourth doping region 128 from the N-type MOS transistor.

In order to clearly compare the difference between the ESD protection capability of the first embodiment and the first embodiment, the following describes the relationship between the pulse voltage and the pulse current of the ESD protection component structure of the embodiment in the TLP test, and the first implementation described above. The results of the examples are compared. Please refer to FIG. 6 to FIG. 7 . FIG. 6 is a schematic diagram of the circuit of the ESD protection component structure according to the second embodiment of the present invention during TLP testing, and FIG. 7 is a diagram showing the structure of the ESD protection component of the second embodiment of the present invention. The relationship between the pulse voltage and the pulse current in the test and the relationship between the leakage current of the gate electrode and the pulse current. As shown in FIG. 6, the first heavily doped region 114 of the ESD protection device structure 100 of the present embodiment is electrically connected to one end of the TLP generator 144, and the second heavily doped region 122 of the ESD protection device structure 100. The gate electrode 136 and the third heavily doped region 130 are electrically connected to the ground terminal 126, and the other end of the TLP generator 144 is also electrically connected to the ground terminal 126. As shown in FIG. 7, the secondary breakdown current It2 of the ESD protection element structure 100 of the second embodiment is 1.52 compared to the second embodiment, and the gate electrode leakage current exceeds 10 The pulse current value at ^-6 A is approximately 4.2 A, so it can withstand a large ESD pulse current. Further, from the secondary breakdown current It2, the ESD protection element structure can withstand a pulse voltage of 7 kV in the human body discharge mode, which is higher than the 1 kV of the first embodiment, and conforms to the industry's ESD protection specification of 2 kV. In the machine discharge mode, the ESD protection element structure of the second embodiment can withstand a pulse voltage of 575 V, which is also higher than the 275 V of the first embodiment. In addition, compared with the trigger voltage Vt1 of the first embodiment, the trigger voltage Vt1 of the ^E S ^D protection device structure of the second embodiment is approximately 40V, which can effectively reduce the ESD protection component structure being triggered when the ESD occurs. The voltage, which in turn increases the range of pulse voltages that the internal circuitry can withstand ESD.

In addition, please refer to FIG. 8. FIG. 8 is a diagram showing the relationship between the operating voltage and the operating current of the structure of the ESD protection element according to the second embodiment of the present invention. As shown in FIG. 8 , the holding voltage of the structure of the ES ^D protection device of the present embodiment is only about 5 V compared with the holding voltage of the first embodiment, which not only effectively reduces the power consumption of the ESD protection component structure, but also reduces the power consumption of the ESD protection component structure. Reduce the impedance of the ESD protection component structure. It can be seen that the ESD protection device structure of the embodiment implants a second doped region having a P-type in a first doped region having an N-type to generate a low-impedance path, and the ESD current is from the I/O conductive pad. Directly leading to the ground via the first heavily doped region, the second doped region, the first drift region, the well region, and the third doped region, that is, when the ESD voltage is greater than the first heavily doped region of the N-type The breakdown voltage with the P-type second doping interval and the voltage across the resistor R _HVPW is greater than the cut-off voltage of the horizontal npn bipolar junction transistor, and the ESD current can be electrically _connected by the vertical npn bipolar junction The low impedance path produced by the turn-on of the crystal and the horizontal npn bipolar junction transistor is effectively directed to ground to effectively protect the internal circuitry.

Furthermore, the second doped region of the present invention is not limited to separating the first heavily doped region from the first drift region, that is, the first heavily doped region may be in contact with the first drift region. For the sake of clarity, the differences between the other embodiments and the second embodiment will be omitted, and the same reference numerals will be used for the same structures as those of the second embodiment, and the same components will not be described again. Please refer to FIG. 9 and FIG. 10 , FIG. 9 is a schematic cross-sectional view showing the structure of an ESD protection element according to a third embodiment of the present invention, and FIG. 10 is a diagram showing the structure of the ESD protection element of the present invention in different first heavily doped regions and The experimental results measured by the TLP test at the contact width of a drift region correspond to a list of ESD pulse voltages that can be withstood. As shown in FIG. 9, the second doped region 108 of the P-type of the ESD protection device structure 150 of the present embodiment does not completely replace the first heavily doped region 114 of the N-type with the second embodiment. A drift region 116 is isolated such that the first heavily doped region 114 is in partial contact with the first drift region 116. In this embodiment, the second doped region 108 is located directly below the first heavily doped region 114, and the first heavily doped region 114 and the first drift region 116 have a contact width Px, but the present invention Without being limited thereto, the second doping region 108 may also be shifted to the left or right. As shown in Fig. 10, as the contact width Px becomes larger, the secondary breakdown current It2 becomes lower and lower, and the trigger voltage Vt1 becomes higher and higher. It can be seen that the pulse voltage that the ESD protection element structure not doped with the second doping region can withstand is the lowest, and as the contact width Px is reduced, the pulse voltage that the ESD protection element structure can withstand gradually increases. When the second doped region completely isolates the first heavily doped region from the first drift region, the pulse voltage that the ESD protection device structure can withstand is maximized.

The structure of the ESD protection component of the present invention may also have other variations. Please refer to FIG. 11 to FIG. 15 , which are the structures of the ESD protection components of the fourth embodiment to the eighth embodiment of the present invention, respectively. Schematic diagram of the section. As shown in FIG. 11, the second doping region 108 of the ESD protection device structure 160 of the fourth embodiment is disposed in the first heavily doped region 114 and is first heavily doped as compared to the second embodiment. The region 114 encapsulates the second doped region 108. As shown in FIG. 12, the second doping region 108 of the ESD protection device structure 170 of the fifth embodiment is disposed in the first drift region 116, and the first drift region 116 covers the second doping region 108. That is, the position and size of the second doping region 108 can be adjusted according to different processes or product requirements, and constitute embodiments of the second, third, fourth, fifth, etc., respectively. In addition, as shown in FIG. 13, the ESD protection element structure 180 of the sixth embodiment further includes a fifth doping region 182 having a first conductivity type and a second conductivity type, as compared with the second embodiment. The third doped region 110 covers the fifth doped region 182, so that the third doped region 110 and the fifth doped region 182 form another vertical bipolar junction transistor 184, such as an npn type dual load. Sub-junction transistor. In the sixth embodiment, the fifth doping region 182 is disposed between the second heavily doped region 122 and the second drift region 124. However, the present invention is not limited thereto, and the fifth doping region 182 may also be coated. In the second heavily doped region 122 or in the second drift region 124, as the second doped region 108 is in the relative position of the first heavily doped region 114 and the first drift region 116, respectively A plurality of sets of embodiments are constructed.

As shown in FIG. 14, the ESD protection element structure 190 of the seventh embodiment does not include the first isolation structure, the second isolation structure, and the third isolation structure for use in a low voltage operating environment as compared with the second embodiment. . However, the present invention is not limited thereto, and may not include only the third isolation structure, only the first isolation structure and the second isolation structure, or only the first isolation structure. Further, as shown in Fig. 15, the ESD protection element structure 200 of the eighth embodiment does not include a gate electrode and a gate dielectric layer as compared with the second embodiment. In the eighth embodiment, the ESD protection device structure 200 can still utilize the first heavily doped region 114, the second doped region 108, the first drift region 116, the well region 104, and the third doped region 110. The impedance path directs the ESD current from the I/O conductive pad 112 to the ground terminal 126, that is, when the ESD voltage is greater than the breakdown voltage between the N-type first heavily doped region 114 and the P-type second doped region 108 and The voltage across the resistor R _HVPW is greater than the cutoff voltage of the horizontal bipolar junction transistor 120. The ESD current can be passed through the vertical npn bipolar junction transistor 118 and the horizontal npn bipolar junction junction. The low impedance path created by the conduction of crystal 120 is effectively directed to ground 126. In addition, the ESD protection element structure of the present invention may also include at least one isolation structure or no first isolation structure, second isolation structure, and third isolation structure.

In summary, the present invention utilizes an ESD implantation process to form a second doped region having a different conductivity pattern in the first heavily doped region of the ESD protection device structure and the first drift region to generate a low impedance path. The I/O conductive pad is via the first heavily doped region, the second doped region, the first drift region, the well region, and the third doping From the zone to the ground, and increase the secondary breakdown current of the ESD protection component structure and reduce the trigger voltage, thereby increasing the pulse voltage that the ESD protection component structure can withstand.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧ESD protection component structure

12‧‧‧Semiconductor substrate

14‧‧‧ Well Area

16‧‧‧Bungee area

18‧‧‧ source area

20‧‧‧ gate dielectric layer

22‧‧‧gate electrode

24‧‧‧Doped area

26‧‧‧ Grounding

28‧‧‧First heavily doped area

30‧‧‧First drift zone

31‧‧‧Internal circuits

32‧‧‧I/O conductive pads

34‧‧‧Second heavily doped area

36‧‧‧Second drift zone

38‧‧‧First isolation structure

40‧‧‧Second isolation structure

42‧‧‧ Third isolation structure

44‧‧‧TPL generator

46‧‧‧base

100‧‧‧ESD protection component structure

102‧‧‧Semiconductor substrate

104‧‧‧ Well Area

106‧‧‧First doped area

108‧‧‧Second doped area

110‧‧‧ third doping zone

111‧‧‧Internal circuits

112‧‧‧I/O conductive pads

114‧‧‧First heavily doped area

116‧‧‧First drift zone

118‧‧‧Vertical type double carrier junction transistor

120‧‧‧Horizontal type double carrier junction transistor

122‧‧‧Second heavily doped area

124‧‧‧Second drift zone

126‧‧‧ Grounding

128‧‧‧fourth doping zone

130‧‧‧ Third heavily doped area

132‧‧‧ Third drift zone

134‧‧‧ gate dielectric layer

136‧‧‧gate electrode

138‧‧‧First isolation structure

140‧‧‧Second isolation structure

142‧‧‧ Third isolation structure

144‧‧‧TPL generator

150‧‧‧ESD protection component structure

160‧‧‧ESD protection component structure

170‧‧‧ESD protection component structure

180‧‧‧ESD protection component structure

182‧‧‧ fifth doping area

184‧‧‧Vertical type double carrier junction transistor

190‧‧‧ESD protection component structure

200‧‧‧ESD protection component structure

It2‧‧‧Second Crash Current

Vt1‧‧‧ trigger voltage

Px‧‧‧ contact width

Fig. 1 is a schematic cross-sectional view showing the structure of an electrostatic discharge protection element according to a first embodiment of the present invention.

FIG. 2 is a schematic circuit diagram of the structure of the ESD protection component of the first embodiment of the present invention during TLP testing.

FIG. 3 is a diagram showing a relationship between a pulse voltage and a pulse current of a structure of an ESD protection element according to a first embodiment of the present invention in a TLP test, and a relationship between a gate electrode leakage current and a pulse current.

Fig. 4 is a view showing the relationship between the operating voltage and the operating current of the structure of the ESD protection element of the first embodiment of the present invention.

Fig. 5 is a cross-sectional view showing the structure of an ESD protection element according to a second embodiment of the present invention.

Figure 6 is a circuit diagram showing the structure of the ESD protection component of the second embodiment of the present invention during TLP testing.

Figure 7 is a diagram showing the relationship between the pulse voltage and the pulse current and the leakage current of the gate electrode in the TLP test of the ESD protection element structure according to the second embodiment of the present invention. Diagram with pulse current.

Figure 8 is a diagram showing the relationship between the operating voltage and the operating current of the structure of the ESD protection element of the second embodiment of the present invention.

Figure 9 is a cross-sectional view showing the structure of an ESD protection element according to a third embodiment of the present invention.

Figure 10 is a diagram showing the trigger voltage Vt1 and the secondary breakdown current It2 measured by the TLP test under the contact width of the first heavily doped region and the first drift region of the ESD protection device of the present invention, and the corresponding Able to withstand ESD pulse voltage.

11 to 15 are schematic cross-sectional views showing the structure of an ESD protection element according to fourth to eighth embodiments of the present invention.

100. . . ESD protection component structure

102. . . Semiconductor substrate

104. . . Well area

106. . . First doped region

108. . . Second doped region

110. . . Third doped region

111. . . Internal circuit

112. . . I/O conductive pad

114. . . First heavily doped region

116. . . First drift zone

118. . . Vertical type double carrier junction transistor

120. . . Horizontal type double carrier junction transistor

122. . . Second heavily doped region

124. . . Second drift zone

126. . . Ground terminal

128. . . Fourth doped region

130. . . Third heavily doped region

132. . . Third drift zone

134. . . Gate dielectric layer

136. . . Gate electrode

138. . . First isolation structure

140. . . Second isolation structure

142. . . Third isolation structure

Claims (19)

An electrostatic discharge (ESD) protection device structure, the electrostatic discharge protection device structure is disposed on a semiconductor substrate, and the electrostatic discharge protection device structure comprises: a well region having a first conductivity type, and Provided in the semiconductor substrate; a first doped region having a second conductivity pattern disposed in the well region; a second doped region having the first conductivity pattern, and the first The doped region encapsulates the second doped region such that the first doped region and the second doped region form a first vertical bipolar junction transistor (vertical BJT), wherein the first doping One portion of the impurity region is disposed on the second doped region, and another portion of the first doped region is disposed under the second doped region; and a third doped region having the second conductive pattern Provided in the well region, the first doped region, the well region and the third doped region constitute a horizontal type bipolar junction transistor (lateral BJT), wherein the well region is disposed at the Between the first doped region and the third doped region. The structure of the electrostatic discharge protection device of claim 1, wherein the first doped region comprises a first heavily doped region and a first drift region, and the first heavily doped region is disposed on the Above the first drift zone. The electrostatic discharge protection device structure of claim 2, wherein the second doped region is disposed between the first heavily doped region and the first drift region. The electrostatic discharge protection device structure of claim 3, wherein the second doped region separates the first heavily doped region from the first drift region. The electrostatic discharge protection device structure of claim 3, wherein the first heavily doped region is in contact with the first drift region. The electrostatic discharge protection device structure of claim 2, wherein the first heavily doped region covers the second doped region. The electrostatic discharge protection device structure of claim 2, wherein the first drift region covers the second doped region. The electrostatic discharge protection device structure of claim 2, further comprising a first isolation structure surrounding the first heavily doped region. The electrostatic discharge protection device structure of claim 8 further comprising a second isolation structure disposed in the third doped region. The electrostatic discharge protection device structure of claim 2, wherein the first heavily doped region is electrically connected to a conductive pad. The electrostatic discharge protection device structure of claim 1, further comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is disposed in the first doped region and the third doped region And superposing the first doped region and the third doped region on the surface of the semiconductor substrate, and the gate electrode is disposed on the gate dielectric layer. The electrostatic discharge protection device structure of claim 11, wherein the gate electrode is electrically connected to a ground. The electrostatic discharge protection device structure of claim 1, further comprising a fourth doped region having the first conductivity pattern disposed in the well region. The electrostatic discharge protection device structure of claim 13, wherein the fourth doped region is electrically connected to the ground terminal and the well region. The electrostatic discharge protection device structure of claim 13 further comprising a third isolation structure surrounding the fourth doped region for isolating the fourth doped region. The electrostatic discharge protection device structure of claim 1, wherein the third doped region comprises a second heavily doped region and a second drift region, and the second heavily doped region is disposed on the Above the second drift zone. The electrostatic discharge protection device structure of claim 1, further comprising a fifth doped region having the second conductive pattern, and the third doped region covers the fifth doped region The third doped region and the fifth doped region form a second vertical type bipolar junction transistor. The electrostatic discharge protection device structure of claim 1, wherein the third doped region is electrically connected to the ground. The electrostatic discharge protection device structure of claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type.