TWI827466B - Esd protection device - Google Patents

Abstract

An ESD protection device includes a first well, a second well, a third well, a fourth well, a fifth well, a first doping region, a second doping region, a third doping region, and a first contact. The first well, the second well, the fourth well, the first diffusion, and the second diffusion have a first conductivity type, and the third well, the fifth well, and the third doping region have a second conductivity type, where the first conductivity type and the second conductivity type are different. The second well is formed in the first well, and the third well is adjacent to the first well. The fourth well and the fifth well are connected and formed in the third well. The first doping region is formed in the second well, the second doping region is formed in the fourth well, and the third doping region is formed in the fifth well. The first contact is in contact with the second well.

Description

Electrostatic protection device

The present invention relates to an electrostatic protection device, in particular to an electrostatic protection device for high-voltage components.

Integrated circuits can be severely damaged due to various electrostatic discharge events. A major electrostatic discharge mechanism comes from the human body, called the Human Body Model (HBM). The human body discharges in 100 nanoseconds ( Within a nano-second (or so), a tip current of several amperes is generated to the integrated circuit and burns the circuit. The second electrostatic discharge mechanism comes from metal objects, which is called machine discharge mode (MM). Produces a much higher rise time and current level than the human body discharge mode. The third electrostatic discharge mechanism is the charged-device model (CDM), in which the integrated circuit itself accumulates charge and the rise time is less than It discharges to the ground within 0.5 nanoseconds. Therefore, we need effective electrostatic protection devices to protect integrated circuits from the hazards of electrostatic discharge.

The present invention proposes an electrostatic protection device and its semiconductor structure suitable for high-voltage transistors. The parasitic effect of terminating, HVJT) produces a silicon controlled rectifier, thereby improving the protection ability of electrostatic discharge. In addition, the present invention forms an electrostatic discharge N-type transistor on the high-voltage junction terminal, which helps to further increase the conduction speed of the silicon controlled rectifier and further improves the electrostatic discharge protection effect. Furthermore, the present invention utilizes staggered generation of first contacts and second contacts in the circuit layout, which can reduce the problem of increased area due to improved electrostatic protection capability. In other words, the present invention can greatly improve the electrostatic discharge protection capability of high-voltage circuits while maintaining the same area.

In view of this, the present invention proposes an electrostatic protection device, which includes a first well area, a second well area, a third well area, a fourth well area, a fifth well area, a first doping area, a second doped region, a third doped region and a first contact. The first well region has a first conductivity type. The second well region has the first conductivity type and is formed in the first well region. The third well region has the second conductivity type and is adjacent to the first well region. The fourth well region has the first conductivity type and is formed in the third well region. The fifth well region has the second conductivity type, is formed in the third well region and is connected to the fourth well region. The first doped region has the first conductivity type and is formed in the second well region. The second doped region has the first conductivity type and is formed in the fourth well region. The third doped region has the second conductivity type and is formed in the fifth well region. The first contact is formed on the second well area and in contact with the second well area. The above-mentioned first conductivity type and the above-mentioned second conductivity type are different.

According to an embodiment of the present invention, the electrostatic protection device further includes a second contact point. The second contact is formed on the first doped region and in contact with the first doped region. The first contact point and the second contact point are made of metal, and the first contact point is electrically connected to the second contact point.

According to an embodiment of the present invention, the above-mentioned electrostatic protection device surrounds a protection area, wherein the above-mentioned first contact point is located between the above-mentioned second contact point and the above-mentioned protection area.

According to another embodiment of the present invention, the electrostatic protection device surrounds a protection area, wherein the second contact point is located between the first contact point and the protection area.

According to another embodiment of the present invention, the above-mentioned electrostatic protection device surrounds a protection area, wherein the above-mentioned first well area, the above-mentioned second well area and the above-mentioned third well area are arranged along a first direction, and the above-mentioned first contact point And the above-mentioned second contacts are arranged along a second direction, wherein the above-mentioned first direction is different from the above-mentioned second direction.

According to an embodiment of the present invention, the second doped region and the third doped region are electrically connected to a ground terminal.

According to an embodiment of the present invention, the electrostatic protection device further includes a first isolation structure, a second isolation structure and a third isolation structure. The first isolation structure is formed between the first doped region and the second doped region. The second isolation structure is formed between the second doped region and the third doped region. The third isolation structure is adjacent to the third doped region.

According to an embodiment of the present invention, the electrostatic protection device further includes a substrate. The substrate has the second conductivity type. The first well region and the third well region are formed in the substrate.

According to an embodiment of the present invention, the electrostatic protection device further includes an epitaxial layer. The epitaxial layer has the first conductivity type, is formed between the first well region and the third well region, and is connected to the first well region and the third well region. The above-mentioned epitaxial layer is formed in the above-mentioned substrate.

According to an embodiment of the present invention, the electrostatic protection device further includes a gate structure. The gate structure is formed on the epitaxial layer and the third well region.

According to an embodiment of the present invention, the gate structure, the second doped region and the third doped region are all electrically connected to a ground terminal.

According to an embodiment of the present invention, the electrostatic protection device further includes a first resistor. The gate structure is electrically connected to the second doped region and the third doped region through the resistor, and the second doped region and the third doped region are electrically connected to a ground terminal.

According to an embodiment of the present invention, the electrostatic protection device further includes a second resistor and an N-type transistor. The above-mentioned second resistor is electrically connected to a supply voltage. The N-type transistor includes a gate terminal, a source terminal and a drain terminal, wherein the gate terminal is electrically connected to the resistor, and the source terminal is electrically connected to the second doping region and the third doping region, The drain terminal is electrically connected to the gate structure. The second doped region and the third doped region are electrically connected to a ground terminal.

The following description is of embodiments of the present disclosure. The purpose is to illustrate the general principles of the present disclosure and should not be regarded as a limitation of the present disclosure. The scope of the present disclosure shall be defined by the scope of the patent application.

It is worth noting that the following disclosure may provide multiple embodiments or examples for practicing different features of the present disclosure. The special component examples and arrangements described below are only used to briefly and concisely illustrate the spirit of the present disclosure, but are not intended to limit the scope of the present disclosure. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of repeated use is only to provide a simplified and clear description, and is not intended to limit the relationship between multiple embodiments and/or configurations discussed below. In addition, the following description of one feature being connected to, coupled to, and/or formed on another feature may actually include multiple different embodiments, including the features being in direct contact, or including other additional features. features are formed between such features, etc., such that the features are not in direct contact.

In addition, relative terms, such as "lower" or "bottom" and "higher" or "top", may be used in the embodiments to describe the relative relationship of one element of the drawings to another element. It will be understood that if the device in the figures is turned upside down, elements described as being on the "lower" side would then be elements described as being on the "higher" side.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions , layers, and/or sections should not be limited by these terms, and these terms are only used to distinguish between different elements, components, regions, layers, and/or sections. Thus, a first element, component, region, layer, and/or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of some embodiments of the present disclosure. and/or part.

Some embodiments of the present disclosure can be understood together with the drawings, and the drawings of the embodiments of the present disclosure are also regarded as part of the description of the embodiments of the present disclosure. It should be understood that the drawings of the embodiments of the present disclosure are not drawn to the scale of actual devices and components. The shapes and thicknesses of embodiments may be exaggerated in the drawings to clearly illustrate features of embodiments of the present disclosure. In addition, the structures and devices in the drawings are illustrated in a schematic manner in order to clearly demonstrate the features of the embodiments of the present disclosure.

As used herein, the terms "about", "approximately" and "approximately" generally mean within 20%, preferably within 10%, and more preferably within 5%, or 3% of a given value or range. Within %, or within 2%, or within 1%, or within 0.5%. The quantities given here are approximate quantities, that is, in the absence of specific instructions of "about", "approximately", and "approximately", the meaning of "approximately", "approximately", and "approximately" can still be implied.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have meanings consistent with the relevant technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner. Interpretation, unless otherwise specifically defined in the embodiments of this disclosure.

In some embodiments of the present disclosure, terms related to joining and connecting, such as "connection", "interconnection", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact. There are other structures located between these two structures. And the terms about joining and connecting can also include the situation where both structures are movable, or both structures are fixed.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have meanings consistent with the relevant technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner. Interpretation, unless otherwise specifically defined in the embodiments of this disclosure.

Some embodiments of the present disclosure can be understood together with the drawings, and the drawings of the embodiments of the present disclosure are also regarded as part of the description of the embodiments of the present disclosure. It should be understood that the drawings of the embodiments of the present disclosure are not drawn to the scale of actual devices and components. The shapes and thicknesses of embodiments may be exaggerated in the drawings to clearly illustrate features of embodiments of the present disclosure. In addition, the structures and devices in the drawings are illustrated in a schematic manner in order to clearly demonstrate the features of the embodiments of the present disclosure.

In some embodiments of the present disclosure, relative terms such as “lower”, “upper”, “horizontal”, “vertical”, “below”, “above”, “top”, “bottom”, etc. shall be Understand the orientation shown in this paragraph and related figures. This relative terminology is only for convenience of explanation and does not mean that the device described needs to be manufactured or operated in a specific orientation. Terms related to joining and connecting, such as "connection" and "interconnection", etc., unless otherwise defined, can mean that two structures are in direct contact, or they can also mean that two structures are not in direct contact, and there are other structures located there. between two structures. And the terms about joining and connecting can also include the situation where both structures are movable or both structures are fixed.

Figure 1 is a circuit diagram showing an electronic circuit according to an embodiment of the present invention. As shown in FIG. 1 , the electronic circuit 100 includes a low-voltage circuit 110 , a high-voltage circuit 120 and a shift transistor ML. The low-voltage circuit 110 is powered by the supply voltage VDD and the ground level of the ground terminal GND, and includes a first electrostatic protection device 111 and a voltage shifter 112 .

The first electrostatic protection device 111 is electrically connected between the supply voltage VDD and the ground terminal GND. When the supply voltage VDD receives electrostatic discharge, the first electrostatic protection device 111 will discharge a large amount of charges generated by the electrostatic discharge from the supply voltage VDD. Discharge to the ground terminal GND to protect the internal circuit of the low-voltage circuit 110. The voltage shifter 112 and the shift transistor ML convert the signal that changes between the supply voltage VDD and the ground level of the ground terminal GND into a signal that changes between the first high voltage voltage VB and the second high voltage voltage VS. and provided to the high voltage circuit 120. According to an embodiment of the present invention, the first high voltage voltage VB is higher than the supply voltage VDD.

The high-voltage circuit 120 is powered by the first high-voltage voltage VB and the second high-voltage voltage VS, and operates according to the signal provided by the shift transistor ML. As shown in FIG. 1 , the high voltage circuit 120 includes a second electrostatic protection device 121 . When the first high voltage voltage VB receives electrostatic discharge, the second electrostatic protection device 121 will discharge a large amount of charges generated by the electrostatic discharge to the second high voltage voltage VS to protect the internal circuit of the high voltage circuit 120 .

However, when the first high voltage voltage VB receives electrostatic discharge, the charge may also be discharged to the ground terminal GND through the resistor RP, the diode DP and the parasitic bipolar junction transistor QP of the shift transistor ML of the electronic circuit 100 . Since the size of the shift transistor ML is small, even if the parasitic bipolar junction transistor QP of the shift transistor ML is turned on, the shift transistor ML may still be burned. Therefore, the electronic circuit 100 further includes a third electrostatic protection device 130 as an additional discharge path.

In order to effectively protect the shift transistor ML, when the first high voltage voltage VB receives electrostatic discharge, the third electrostatic protection device 130 must be turned on earlier than the parasitic bipolar junction transistor QP of the shift transistor ML to facilitate Quickly eliminate charges accumulated by electrostatic discharge. The structure and operating principle of the third electrostatic protection device 130 will be described in detail below.

FIG. 2 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention. As shown in Figure 2, the semiconductor structure 200 corresponds to the third electrostatic protection device 130 in Figure 1, and includes a substrate SUB, a first well area W1, a second well area W2, a third well area W3, and a fourth well area. Area W4, fifth well area W5 and epitaxial layer EPI.

The substrate SUB has a first conductivity type. According to an embodiment of the present invention, the substrate SUB is a silicon substrate. According to other embodiments of the present invention, the substrate SUB may also be a lightly doped semiconductor substrate having the first conductivity type.

The first well region W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type. According to an embodiment of the invention, the first well region W1 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of the predetermined first well region W1 to form the first well region W1.

The second well region W2 is formed in the first well region W1 and has the second conductivity type. According to an embodiment of the invention, the second well region W2 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of the predetermined second well region W2 to form the second well region W2. In this embodiment, the doping concentration of the second well region W2 is higher than the doping concentration of the first well region W1.

The third well region W3 is formed in the semiconductor substrate SUB and is adjacent to the first well region W1, wherein the third well region W3 has the first conductivity type. According to an embodiment of the present invention, the third well region W3 may also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the third well region W3 is intended to be formed to form the third well region W3. In this embodiment, the doping concentration of the third well region W3 is higher than the doping concentration of the semiconductor substrate SUB.

The fourth well region W4 is formed in the third well region W3 and has the second conductivity type. According to an embodiment of the present invention, the fourth well region W4 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area of the predetermined fourth well region W4 to form the fourth well region W4. In this embodiment, the doping concentration of the fourth well region W4 is higher than the doping concentration of the first well region W1.

The fifth well region W5 is formed in the third well region W3, wherein the fifth well region W5 has the first conductivity type. According to an embodiment of the present invention, the fifth well region W5 may also be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the fifth well region W5 is intended to be formed to form the fifth well region W5. In this embodiment, the doping concentration of the fifth well region W5 is higher than the doping concentration of the third well region W3.

The epitaxial layer EPI is formed in the substrate SUB and has a second conductivity type. In addition, the epitaxial layer EPI is located between the first well region W1 and the third well region W3, and is in contact with the first well region W1 and the third well region W3.

As shown in FIG. 2 , the semiconductor structure 200 further includes a first doped region D1 , a second doped region D2 and a third doped region D3 . The first doped region D1 has the second conductivity type and is formed in the second well region W2. According to an embodiment of the present invention, the doping concentration of the first doped region D1 is higher than the doping concentration of the second well region W2.

The second doped region D2 has the second conductivity type and is formed in the fourth well region W4. According to an embodiment of the present invention, the doping concentration of the second doped region D2 is higher than the doping concentration of the second well region W2. The third doped region D3 has the first conductivity type and is formed in the fifth well region W5. According to an embodiment of the present invention, the doping concentration of the third doping region D3 is higher than the doping concentration of the fifth well region W5.

As shown in FIG. 2 , the semiconductor structure 200 further includes a first contact CT1 and a second contact CT2. The first contact CT1 is formed on the second well area W2 and is in direct contact with the second well area W2. According to an embodiment of the present invention, the first contact CT1 and the second contact CT2 are contacts formed of metal. According to an embodiment of the present invention, the first contact CT1 forms a Schottky contact with the second well region W2. The second contact CT2 is formed on the first doped region D1 and contacts the first doped region.

As shown in FIG. 2 , the semiconductor structure 200 further includes a first isolation structure ISO1, a second isolation structure ISO2, and a third isolation structure ISO3. The first isolation structure ISO1 is located between the first doped region D1 and the third doped region D3 and on the epitaxial layer EPI and the third well region W3 to separate the first doped region D1 and the second doped region Area D2.

As shown in FIG. 2 , the first isolation structure ISO1 directly contacts the first doping region D1 and the second doping region D2, but this is not intended to limit the present invention. According to other embodiments of the present invention, the first isolation structure ISO1 does not contact at least one of the first doped region D1 and the second doped region D2.

The second isolation structure ISO2 is located between the second doping region D2 and the third doping region D3, and is located above the fourth well region W4 and the fifth well region W5 to separate the second doping region D2 and the third well region W5. Doped region D3. As shown in FIG. 2 , the second isolation structure ISO2 directly contacts the second doping region D2 and the third doping region D3, but this is not intended to limit the present invention. According to other embodiments of the present invention, the second isolation structure ISO2 does not contact at least one of the second doped region D2 and the third doped region D3.

The third isolation structure ISO3 is adjacent to the third doping region D3 and is used to separate the third doping region D3 from other semiconductor structures. As shown in Figure 2, the third isolation structure ISO3 directly contacts the third doping region D3, but this is not intended to limit the present invention. According to other embodiments of the present invention, the third isolation structure ISO3 does not contact the third doping region D3.

As shown in Figure 2, the second doped region D2 and the third doped region D3 are electrically connected to each other and to the ground terminal GND in Figure 1, and the first contact point CT1 and the second contact point CT2 are are electrically connected to each other and to the first high voltage VB in Figure 1. According to some embodiments of the present invention, the second doped region D2 and the third doped region D3 are electrically connected to the ground terminal GND in FIG. 1 through the interconnection structure of the semiconductor structure 200 . According to some embodiments of the present invention, the first contact point CT1 and the second contact point CT2 can be electrically connected to the first high voltage voltage VB in Figure 1 through other interconnect structures or metal contacts.

Since the first contact CT1, the first doped region D1, the third well region W3 and the second doped region D2 form a silicon controlled rectifier (SCR), when electrostatic discharge occurs at the first high voltage voltage VB, The third electrostatic protection device 130 in Figure 1 is prompted to be turned on earlier than the parasitic bipolar junction transistor QP of the shift transistor ML, thereby preventing a large amount of electrostatic discharge charges of the first high voltage VB from flowing through the shift transistor ML. This causes the possibility of burning the shift transistor ML, thereby protecting the shift transistor ML from burning.

FIG. 3 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 300 in Figure 3 with the semiconductor structure 200 in Figure 2, the first isolation structure ISO1 is divided into a fourth isolation structure ISO4 and a fifth isolation structure ISO5, and the semiconductor structure 300 further includes a gate structure GS. The gate structure GS is formed between the fourth isolation structure ISO4 and the fifth isolation structure ISO5, and is formed on the epitaxial layer EPI and the third well region W3.

Figure 4 is an equivalent circuit diagram showing an electrostatic protection device according to another embodiment of the present invention. As shown in FIG. 4, the electrostatic protection device 400 is an equivalent circuit of the semiconductor structure 300 in FIG. A doped region D1, the epitaxial layer EPI, the third well region W3 and the second doped region D2 are formed. The silicon controlled rectifier 420 is composed of the first contact CT1 of the semiconductor structure 300, the first doped region D1, and the second doped region D2. Three well regions W3 and a second doping region D2 are formed. According to an embodiment of the present invention, the electrostatic protection device 400 corresponds to the third electrostatic protection device 130 in FIG. 1 .

FIG. 5 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 500 in FIG. 5 with the semiconductor structure 300 in FIG. 3 , the semiconductor structure 500 further includes a first resistor R1 , wherein the first resistor R1 is electrically connected between the gate structure GS and the ground terminal GND.

Figure 6 shows an equivalent circuit diagram of an electrostatic protection device according to another embodiment of the present invention. As shown in Figure 6, the electrostatic protection device 600 is an equivalent circuit of the semiconductor structure 500 in Figure 5, including an electrostatic discharge transistor 610, a silicon controlled rectifier 620 and a first resistor R1, wherein the electrostatic discharge transistor 610 is composed of The first doped region D1, the epitaxial layer EPI, the third well region W3 and the second doped region D2 of the semiconductor structure 500 are formed. The silicon controlled rectifier 620 is formed by the first contact CT1 of the semiconductor structure 500 and the first doped region D2. The impurity region D1, the third well region W3 and the second doping region D2 are formed. The first resistor R1 in Figure 6 corresponds to the first resistor R1 in Figure 5. According to an embodiment of the present invention, the electrostatic protection device 600 corresponds to the third electrostatic protection device 130 in FIG. 1 .

According to an embodiment of the present invention, when electrostatic discharge occurs at the first high voltage voltage VB, a large amount of charges accumulated in the first high voltage voltage VB are coupled to the electrostatic discharge transistor 610 through the capacitance from the drain terminal to the gate terminal of the electrostatic discharge transistor 610 the gate terminal, thereby turning on the electrostatic discharge transistor 610. Then, when the electrostatic discharge transistor 610 is turned on, the diode formed by the junction of the third well region W3 and the fourth well region W4 is also turned on, so that the first contact CT1 and the first contact CT1 of the semiconductor structure 500 are also turned on. The silicon controlled rectifier 620 formed by the doped region D1, the third well region W3 and the second doped region D2 is also turned on, thereby expelling the accumulated charge of the first high voltage voltage VB to the ground terminal GND, and protecting the first The shift transistor ML in the picture is protected from burning.

According to an embodiment of the present invention, since the conduction of the electrostatic discharge transistor 610 helps to conduct the diode formed at the junction of the third well region W3 and the fourth well region W4, when the first high voltage voltage VB generates static electricity During discharge, the electrostatic protection device 600 has a faster conduction speed than the electrostatic protection device 400 .

FIG. 7 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 700 in FIG. 7 with the semiconductor structure 300 in FIG. 3 , the semiconductor structure 700 further includes a gate control transistor MGC and a second resistor R2. According to an embodiment of the present invention, the gate control transistor MGC is an N-type transistor and is coupled between the gate structure GS and the ground terminal GND. The second resistor R2 is electrically connected between the gate terminal of the gate control transistor TGC and the supply voltage VDD. According to an embodiment of the present invention, the supply voltage VDD in Figure 7 corresponds to the supply voltage VDD in Figure 1 . In other words, the second resistor R2 receives the supply voltage VDD of the low-voltage circuit 110 in Figure 1 .

Figure 8 shows an equivalent circuit diagram of an electrostatic protection device according to another embodiment of the present invention. As shown in Figure 8, the electrostatic protection device 800 is an equivalent circuit of the semiconductor structure 700 in Figure 7, including an electrostatic discharge transistor 810, a silicon controlled rectifier 820, a second resistor R2 and a gate controlled transistor MGC. The discharge transistor 810 is formed by the first doped region D1 of the semiconductor structure 700, the epitaxial layer EPI, the third well region W3 and the second doped region D2. The silicon controlled rectifier 820 is formed by the first contact of the semiconductor structure 700. Point CT1, the first doped region D1, the third well region W3 and the second doped region D2 are formed. The second resistor R2 in Figure 8 and the gate control transistor MGC respectively correspond to the second resistor in Figure 7 R2 and gate control transistor MGC.

According to an embodiment of the present invention, the electrostatic protection device 800 corresponds to the third electrostatic protection device 130 in FIG. 1 . According to an embodiment of the present invention, the gate transistor MGC is an N-type transistor and the gate terminal of the gate transistor MGC is coupled to the supply voltage VDD of the low-voltage circuit 110 in Figure 1 through the second resistor R2. , therefore the gate control transistor MGC is equivalent to a resistor, and the action of the electrostatic protection device 800 is the same as that of the electrostatic protection device 600, which will not be repeated here.

FIG. 9 is a circuit layout diagram of the electronic circuit of FIG. 1 according to an embodiment of the present invention. As shown in FIG. 9 , the circuit layout 900 includes a high voltage junction terminal 910 , a first region 920 , a second region 930 and a plurality of third regions 940 . The high-voltage junction terminal 910 divides the circuit layout 900 into a first area 920 and a second area 930. The cross-sectional views along the AA' cut of the high-voltage junction terminal 910 are as shown in Figures 2, 3, 5, and 7 shown. In other words, the semiconductor structures 200, 300, 500, and 700 in Figures 2, 3, 5, and 7 form the high-voltage junction terminal 910 and surround the center CT of the circuit layout 900, in which the first well area W1 first surrounds the center CT , the epitaxial layer EPI then surrounds the first well area W1, and the outermost system is surrounded by the third well area W3, which surrounds the epitaxial layer EPI.

According to an embodiment of the present invention, the low-voltage circuit 110 in Figure 1 is disposed in the first region 920 in Figure 9 , the high-voltage circuit 120 in Figure 1 is disposed in the second region 930 in Figure 9 , and the shift in Figure 1 The transistor ML is disposed in a plurality of third regions 940 , wherein the third regions 940 are located on the high voltage junction terminal 910 . According to many embodiments of the present invention, the number of the third regions 940 can be increased or decreased according to the size of the shift transistor ML. In this embodiment, FIG. 9 is illustrated with three third regions 940, and It is not limited in any way to this. The following will focus on the layout method of the first contact CT1, the second contact CT2, the first doped region D1, the first well region W1, the second well region W2 and the epitaxial layer EPI in the fourth region 950 of the circuit layout 900. , explain in detail.

Figure 10 is a top view of the fourth area of Figure 9 according to an embodiment of the present invention. As shown in Figure 10, the order of the semiconductor layers of the circuit layout 1000 from closest to the center CT to farthest from the center CT is: first well area W1, second well area W2, first doped area D1, second well area Region W2, the first well region W1 and the epitaxial layer EPI, the first contact CT1 covers the second well region W2, and the second contact CT2 covers the first doped region D1.

In other words, the sequence of the circuit layout 1000 is the same as that of the first well region W1, the second well region W2, and the first doping region shown in the semiconductor structures 200, 300, 500, and 700 in Figures 2, 3, 5, and 7. The order of D1, the second well area W2, the first well area W1 and the epitaxial layer EPI is consistent.

Figure 11 is a top view of the fourth area of Figure 9 according to another embodiment of the present invention. As shown in Figure 11, the order of the semiconductor layers of the circuit layout 1100 from closest to the center CT to far away from the center CT is: first well area W1, first doped area D1, second well area W2, first well area W1 and the epitaxial layer EPI, in which the first contact CT1 covers the second well region W2, and the second contact CT2 covers the first doped region D1. In other words, the circuit can be obtained by exchanging the order of the first contact CT1, the first doping region D1 and the second contact CT2 of the semiconductor structures 200, 300, 500 and 700 in Figures 2, 3, 5 and 7. The order of layout 1100.

Figure 12 is a top view of the fourth area of Figure 9 according to yet another embodiment of the present invention. As shown in Figure 12, the order of the semiconductor layers of the circuit layout 1200 from closest to the center CT to far away from the center CT is: the first well area W1, the second well area W2, the first well area W1 and the epitaxial layer EPI. The first doped regions D1 are spaced in the second well region W2 in the second direction.

According to an embodiment of the present invention, the first well area W1, the second well area W2, the first well area W1 and the epitaxial layer EPI are arranged along a first direction, where the first direction and the second direction are orthogonal. . According to other embodiments of the present invention, the high voltage junction terminal 910 in Figure 9 can also surround the center CT in any shape, and the first well area W1, the second well area W2, the first well area W1 and the epitaxial layer EPI are The first contact point CT1 and the second contact point CT2 are sorted in the second direction, and the first direction and the second direction are different.

As shown in Figure 12, the metal contact CT extends in the second direction and covers the second well region W2 and the first doped region D1, and is in contact with the second well region W2 and the first doped region D1. . According to an embodiment of the present invention, when the metal contact CT is in contact with the second well region W2, the first contact CT1 is formed. According to another embodiment of the present invention, when the metal contact is in contact with the first doped region D1, the second contact CT2 is formed.

Comparing the circuit layout 1200 with the circuit layout 1000 and the circuit layout 1100, since the circuit layout 1200 only needs one metal contact CT to form the first contact CT1 and the second contact CT2, the circuit layout 1200 is compared with the circuit layout 1000 and the circuit layout 1100. Layout 1100 significantly reduces the required circuit area.

The present invention proposes an electrostatic protection device and its semiconductor structure suitable for high-voltage transistors. A silicon-controlled rectifier is generated through the parasitic effect of high-voltage junction terminals, thereby improving the electrostatic discharge protection capability. In addition, the present invention forms an electrostatic discharge N-type transistor on the high-voltage junction terminal, which helps to further increase the conduction speed of the silicon controlled rectifier and further improves the electrostatic discharge protection effect. Furthermore, the present invention utilizes staggered generation of first contacts and second contacts in the circuit layout, which can reduce the problem of increased area due to improved electrostatic protection capability. In other words, the present invention can greatly improve the electrostatic discharge protection capability of high-voltage circuits while maintaining the same area.

Although the embodiments and their advantages of the present disclosure have been disclosed above, it should be understood that anyone with ordinary skill in the art can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the processes, machines, manufacturing, material compositions, devices, methods and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the relevant technical field can learn from some implementations of the present disclosure. It is understood that processes, machines, manufacturing, material compositions, devices, methods and steps currently or developed in the future can be based on the disclosure of the examples as long as they can perform substantially the same functions or obtain substantially the same results in the embodiments described herein. Some embodiments of the present disclosure use. Therefore, the protection scope of the present disclosure includes the above-mentioned processes, machines, manufacturing, material compositions, devices, methods and steps. In addition, each claimed patent scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes the combination of each claimed patent scope and embodiments.

100: Electronic circuits 110:Low voltage circuit 111: The first electrostatic protection device 112:Voltage shifter 120:High voltage circuit 121: Second electrostatic protection device 130: The third electrostatic protection device 200,300,500,700:Semiconductor structure 400,600,800:Electrostatic protection device 410,610,810: Electrostatic discharge transistor 420,620,820: Silicon controlled rectifier 900,1000,1100,1200:Circuit layout 910: High voltage junction terminal 920:First area 930:Second area 940:The third area 950:The fourth area ML: shift transistor RP: Resistor DP: diode VDD: supply voltage GND: ground terminal VB: first high voltage VS: second high voltage QP: Parasitic bipolar junction transistor SUB:Substrate W1: The first well area W2: The second well area W3: The third well area W4: The fourth well area W5: Fifth well area EPI: epitaxial layer D1: first doped region D2: Second doped region D3: The third doped region CT1: first contact CT2: Second contact ISO1: the first isolation structure ISO2: Second isolation structure ISO3: third isolation structure ISO4: The fourth isolation structure ISO5: fifth isolation structure GS: Gate structure R1: first resistor R2: second resistor MGC: gate controlled transistor CT:center

Figure 1 is a circuit diagram of an electronic circuit according to an embodiment of the invention; Figure 2 is a cross-sectional view of a semiconductor structure according to an embodiment of the invention; Figure 3 is a diagram of an electronic circuit according to an embodiment of the invention. A cross-sectional view of a semiconductor structure according to another embodiment; Figure 4 shows an equivalent circuit diagram of an electrostatic protection device according to another embodiment of the present invention; Figure 5 shows another embodiment of the present invention. A cross-sectional view of the semiconductor structure; Figure 6 is an equivalent circuit diagram showing an electrostatic protection device according to another embodiment of the present invention; Figure 7 is a cross-sectional view showing a semiconductor structure according to another embodiment of the present invention; Figure 8 shows an equivalent circuit diagram of an electrostatic protection device according to another embodiment of the present invention; Figure 9 is a circuit layout diagram showing the electronic circuit of Figure 1 according to one embodiment of the present invention; Figure 10 is a top view of the fourth area of Figure 9 according to an embodiment of the present invention; Figure 11 is a top view of the fourth area of Figure 9 according to another embodiment of the present invention; and Figure 12 is a top view of the fourth area of Figure 9 according to yet another embodiment of the present invention.

200:Semiconductor Structure

SUB:Substrate

W1: The first well area

W2: The second well area

W3: The third well area

W4: The fourth well area

W5: Fifth well area

EPI: epitaxial layer

D1: first doped region

D2: Second doped region

D3: The third doped region

CT1: first contact

CT2: Second contact

ISO1: the first isolation structure

ISO2: Second isolation structure

ISO3: third isolation structure

VB: first high voltage

GND: ground terminal

Claims (13)

An electrostatic protection device, including: a first well area having a first conductivity type; a second well area having the above-mentioned first conductivity type and being formed in the above-mentioned first well area; a third well area, has a second conductivity type and is adjacent to the above-mentioned first well region; a fourth well region has the above-mentioned first conductivity type and is formed in the above-mentioned third well region; a fifth well region has the above-mentioned second well region A conductivity type, formed in the above-mentioned third well region and connected to the above-mentioned fourth well region; a first doping region, having the above-mentioned first conductivity type, and formed in the above-mentioned second well region; a second doping region a region having the above-mentioned first conductivity type and formed in the above-mentioned fourth well region; a third doped region having the above-mentioned second conductivity type and formed in the above-mentioned fifth well region; and a first contact, Formed on the above-mentioned second well region and in contact with the above-mentioned second well region, wherein the above-mentioned first contact and the above-mentioned second well region form a Schottky contact; wherein the above-mentioned first conductivity type and the above-mentioned second conductivity type are for different. The electrostatic protection device of claim 1, further comprising: a second contact formed on the first doped region and in contact with the first doped region; wherein the first contact and the second contact It is made of metal, and the first contact point is electrically connected to the second contact point. The electrostatic protection device of claim 2, wherein the electrostatic protection device surrounds a protection area, and the first contact point is located between the second contact point and the protection area. The electrostatic protection device of claim 2, wherein the electrostatic protection device surrounds a protection area, and the second contact point is located between the first contact point and the protection area. The electrostatic protection device of claim 2, wherein the electrostatic protection device surrounds a protection area, wherein the first well area, the second well area and the third well area are arranged along a first direction, and the first connection The points and the second contact points are arranged along a second direction, wherein the first direction is different from the second direction. The electrostatic protection device of claim 1, wherein the second doped region and the third doped region are electrically connected to a ground terminal. The electrostatic protection device of claim 1, further comprising: a first isolation structure formed between the first doping region and the second doping region; a second isolation structure formed in the second doping region and between the above-mentioned third doping regions; and a third isolation structure adjacent to the above-mentioned third doping regions. The electrostatic protection device of claim 1 further includes: a substrate having the second conductivity type; wherein the first well region and the third well region are formed in the substrate. The electrostatic protection device of claim 8, further comprising: an epitaxial layer having the first conductivity type, formed between the first well area and the third well area and in contact with the first well area and the third well area. The well areas are connected; the epitaxial layer is formed in the substrate. For example, the electrostatic protection device in claim 9 further includes: A gate structure is formed on the epitaxial layer and the third well region. The electrostatic protection device of claim 10, wherein the gate structure, the second doped region and the third doped region are all electrically connected to a ground terminal. The electrostatic protection device of claim 10, further comprising: a first resistor, wherein the gate structure is electrically connected to the second doped region and the third doped region through the first resistor; wherein the second doped region The region and the third doped region are electrically connected to a ground terminal. The electrostatic protection device of claim 10 further includes: a second resistor electrically connected to a supply voltage; and an N-type transistor including a gate terminal, a source terminal and a drain terminal, wherein the gate terminal is electrically connected to the above-mentioned second resistor, the above-mentioned source terminal is electrically connected to the above-mentioned second doping region and the above-mentioned third doping region, and the above-mentioned drain terminal is electrically connected to the above-mentioned gate structure; wherein the above-mentioned second doping region and the above-mentioned The third doped region is electrically connected to a ground terminal.

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