TWI720867B - Semiconductor device - Google Patents

Abstract

A semiconductor device, which is configured to protect an internal circuit, includes a transistor and an ESD protection device. The transistor includes a gate terminal, a source terminal coupled to the internal circuit, a drain terminal coupled to an input/output pad, and a bulk terminal coupled to a ground. The ESD device is coupled between the input/output pad and the ground. When the input/output pad receives an ESD current, the ESD protection device expels the ESD current to the ground.

Description

Semiconductor device

The present invention relates to a semiconductor device and a semiconductor structure, and particularly relates to a semiconductor device and a semiconductor structure as electrostatic protection.

The integrated circuit system can cause serious damage due to various electrostatic discharge events. One of the main electrostatic discharge mechanisms comes from the human body, which is called the Human Body Model (HBM). The human body is in 100 nanoseconds ( nano-second (a few amperes of tip current is generated to the integrated circuit within a period of time, and the circuit is burned. The second type of electrostatic discharge mechanism comes from metal objects, which is called the Machine Model (MM). Produces a much higher rise time and current level than the human body discharge mode. The third electrostatic discharge mechanism is the Charged-Device Model (CDM), in which the integrated circuit itself accumulates charge and the rise time is less than Discharge to the ground terminal within 0.5 nanoseconds. Therefore, we need an effective electrostatic discharge protection device to protect the integrated circuit from electrostatic discharge.

In view of this, the present invention provides a semiconductor device for protecting an internal circuit. The above-mentioned semiconductor device includes a transistor and an electrostatic discharge protection device. The transistor includes a gate terminal, a source terminal, a drain terminal, and a base terminal, wherein the source terminal is coupled to the internal circuit, the drain terminal is coupled to an input/output pad, and the base terminal is coupled to One ground terminal. The electrostatic discharge protection device is coupled between the input/output pad and the ground terminal, wherein when the input/output pad receives an electrostatic discharge current, the electrostatic discharge protection device removes the electrostatic discharge current to the Ground terminal.

According to an embodiment of the present invention, the above-mentioned transistor includes a semiconductor substrate, a first well region, a second well region, a third well region, and a fourth well region. The semiconductor substrate has a first conductivity type. The first well region has a second conductivity type and is formed in the semiconductor substrate. The second well region has the second conductivity type and is formed in the first well region. The third well region has the first conductivity type, is formed in the semiconductor substrate and is connected to the first well region. The fourth well area has the first conductivity type, is formed in the first well area, and is located between the second well area and the third well area. The first top doped region has the first conductivity type, is formed in the first well region and is located between the second well region and the fourth well region, wherein the first top doped region is connected to the first well region. The two well areas are connected to each other. The second top doped region has the first conductivity type and is formed in the fourth well region. The first doped region has the first conductivity type and is formed in the second top doped region, wherein the first doped region forms the gate terminal. The third doped region has the second conductivity type and is formed in the second well region, wherein the third doped region forms the drain terminal. The fourth doped region has the second conductivity type, is formed in the first well region and is located between the third well region and the fourth well region, wherein the fourth doped region forms the source terminal. The fifth doped region has the first conductivity type and is formed in the third well region, wherein the fifth doped region forms the base terminal.

According to an embodiment of the present invention, the above-mentioned electrostatic discharge protection device includes a fifth well region, a third top doped region, a sixth doped region, a seventh doped region, an eighth doped region, and a A first gate structure and a second gate structure. The fifth well region has the first conductivity type and is formed in the semiconductor substrate and is adjacent to the first well region. The third top doped region has the first conductivity type, is formed in the first well region and is located between the second well region and the fifth well region, wherein the third top doped region is connected to the first well region. The two well areas are connected to each other. The sixth doped region has the second conductivity type and is formed in the second well region. The seventh doped region has the first conductivity type and is formed in the fifth well region. The eighth doped region has the second conductivity type, is formed in the fifth well region, and is located between the first well region and the seventh doped region. The first gate structure is formed on the third top doped region, wherein the sixth doped region and the first gate structure are coupled to the input/output pad. The second gate structure is formed on the first well region and the fifth well region, and is located between the third top doped region and the eighth doped region, wherein the second gate structure, the above The seventh doped region and the eighth doped region are coupled to the ground terminal.

According to an embodiment of the present invention, the above-mentioned electrostatic discharge protection device is an electrostatic discharge protection transistor.

According to another embodiment of the present invention, the above-mentioned electrostatic discharge protection device further includes a ninth doped region. The ninth doped region has the first conductivity type, is formed in the first well region, and is connected to the sixth doped region, wherein the ninth doped region is coupled to the input/output pad , Wherein the gate terminal of the transistor is in a floating state.

According to another embodiment of the present invention, the above-mentioned transistor further includes a second doped region. The second doped region has the second conductivity type, is formed in the second top doped region, and is connected to the first doped region.

According to an embodiment of the present invention, the first doped region is located between the second doped region and the third doped region.

According to another embodiment of the present invention, the second doped region is located between the first doped region and the third doped region.

According to another embodiment of the present invention, the gate terminal is coupled to the ground terminal.

According to an embodiment of the present invention, when the drain terminal receives the electrostatic discharge current, the third doped region, the first doped region, and the second doped region form a bipolar transistor for the The electrostatic discharge current is discharged to the ground terminal through the gate terminal, thereby protecting the internal circuit.

According to an embodiment of the present invention, the first doped region, the fourth doped region, and the fifth doped region surround the third doped region.

According to an embodiment of the present invention, the seventh doped region and the eighth doped region surround the sixth doped region.

According to an embodiment of the present invention, the third doped region and the sixth doped region are connected to each other, and the first doped region, the third doped region, the fourth doped region, and the fifth doped region are connected to each other. The region, the sixth doped region, the seventh doped region, and the eighth doped region collectively form a surrounding structure.

The following is a detailed description of the device substrate, the semiconductor device, and the manufacturing method of the semiconductor device according to some embodiments of the disclosure. It should be understood that the following description provides many different embodiments or examples for implementing different aspects of some embodiments of the present disclosure. The specific elements and arrangements described below are only a simple and clear description of some embodiments of the present disclosure. Of course, these are only examples and not the limitation of this disclosure. In addition, repeated reference numbers or labels may be used in different embodiments. These repetitions are only to briefly and clearly describe some embodiments of the present disclosure, and do not represent any connection between the different embodiments and/or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or on a second material layer, it includes the case where the first material layer is in direct contact with the second material layer. Or, there may be one or more other material layers spaced apart. In this case, the first material layer and the second material layer may not be in direct contact.

In addition, the embodiments may use relative terms, such as “lower” or “bottom” and “higher” or “top” to describe the relative relationship between one element of the drawing and another element. It can be understood that if the device in the drawing is turned upside down, the elements described on the "lower" side will become the elements on the "higher" side.

Here, the terms "about", "approximately", and "approximately" usually mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3 Within %, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, the meaning of "about", "approximately" and "approximately" can still be implied without specifying "about", "approximately" or "approximately".

It can be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and/or parts, these elements, components, regions , Layers, and/or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and/or parts. Therefore, a first element, component, region, layer, and/or part discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of some embodiments of the present disclosure. And/or part.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by the general artisans to whom the disclosure belongs. It is understandable that these terms, such as those defined in commonly used dictionaries, should be interpreted as having meanings consistent with the relevant technology and the background or context of this disclosure, rather than in an idealized or overly formal way. Interpretation, unless there is a special definition in the embodiment of the present disclosure.

Some embodiments of the present disclosure can be understood in conjunction with the drawings, and the drawings of the embodiments of the present disclosure are also regarded as part of the description of the embodiments of the present disclosure. It should be understood that the drawings of the embodiments of the present disclosure are not drawn to the scale of actual devices and components. In the drawings, the shape and thickness of the embodiment may be exaggerated in order to clearly show the characteristics of the embodiment of the present disclosure. In addition, the structures and devices in the drawings are shown schematically in order to clearly show the characteristics of the embodiments of the present disclosure.

In some embodiments of this disclosure, relative terms such as "down", "up", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be Understand the orientation shown in this paragraph and related drawings. This relative term is only for the convenience of explanation, and it does not mean that the device described in it needs to be manufactured or operated in a specific orientation. As for the terms of joining and connecting, such as "connect", "interconnect", etc., unless specifically defined, it can mean that two structures are in direct contact, or it can also mean that two structures are not in direct contact, and there are other structures provided here. Between the two structures. Moreover, the terms of joining and connecting can also include the case where both structures are movable or both structures are fixed.

The embodiments of the present invention disclose embodiments of semiconductor devices, and the above-mentioned embodiments can be included in integrated circuits (ICs) such as microprocessors, memory devices, and/or other devices. The above-mentioned integrated circuit can also include different passive and active microelectronic components, such as thin-film resistors, other types of capacitors, such as metal-insulator-metal capacitors (MIMCAP), inductors , Diodes, Metal-Oxide-Semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), lateral diffusion Type MOS transistors, high-power MOS transistors or other types of transistors. Those with ordinary knowledge in the technical field of the present invention can understand that semiconductor devices can also be used to include other types of semiconductor elements in integrated circuits.

Fig. 1 shows a circuit diagram of an integrated circuit according to an embodiment of the present invention. As shown in FIG. 1, the integrated circuit 100 includes a transistor 110, an input/output pad 120, a resistor R, an internal circuit 130, and an electrostatic discharge protection device 140. The transistor 110 includes a gate terminal G, a source terminal S, a drain terminal D, and a base terminal B. The base terminal B is coupled to the ground terminal, the drain terminal D is coupled to the input/output pad 120, and the source terminal S passes through The resistor R is coupled to the internal circuit 130. According to an embodiment of the present invention, the gate terminal G is in a floating state. According to an embodiment of the present invention, the transistor 110 is a junction field effect transistor. The electrostatic discharge protection device 140 is coupled between the input/output pad 120 and the ground terminal.

According to an embodiment of the present invention, when the input/output pad 120 receives the electrostatic discharge current IESD generated by electrostatic discharge, the electrostatic discharge protection device 140 removes the electrostatic discharge current IESD to the ground terminal, so that the electrostatic discharge current IESD is not It will flow through the internal circuit 130 and cause damage to the internal circuit 130. When working normally, the gate terminal G of the transistor 110 is coupled to the ground terminal, the input/output pad 120 is coupled to the internal circuit 130 so that the internal circuit 130 operates normally, and the electrostatic discharge protection device 140 does not affect the internal circuit 130 efficacy.

FIG. 2 is a circuit diagram of an integrated circuit according to another embodiment of the present invention. Comparing the integrated circuit 200 in FIG. 2 with the integrated circuit 100 in FIG. 1, the electrostatic discharge protection device 140 is an electrostatic discharge protection transistor 240. According to an embodiment of the present invention, the ESD protection transistor 240 is a transistor whose gate terminal is grounded. When the input/output pad 120 receives the electrostatic discharge current IESD, the parasitic bipolar junction transistor of the electrostatic discharge protection transistor 240 is turned on to remove the electrostatic discharge current IESD to the ground terminal.

FIG. 3 is a circuit diagram of an integrated circuit according to another embodiment of the present invention. Comparing the integrated circuit 300 in FIG. 3 with the integrated circuit 100 in FIG. 1, the electrostatic discharge protection device 140 is a silicon controlled rectifier 340. When the input/output pad 120 receives the electrostatic discharge current IESD, the silicon controlled rectifier 340 is turned on to remove the electrostatic discharge current IESD to the ground terminal.

FIG. 4 is a cross-sectional view of the transistor according to an embodiment of the present invention. According to an embodiment of the present invention, the transistor 400 corresponds to the transistor 110 in FIG. 1. As shown in FIG. 4, the transistor 400 includes a semiconductor substrate SUB, a first well region W1, a second well region W2, a third well region W3, and a fourth well region W4.

The semiconductor substrate SUB has a first conductivity type. According to an embodiment of the present invention, the semiconductor substrate SUB is a silicon substrate. According to other embodiments of the present invention, the semiconductor substrate SUB can also be a lightly doped semiconductor substrate with the first conductivity type.

The first well region W1 is formed in the semiconductor substrate SUB and has the second conductivity type. According to an embodiment of the present invention, the first conductivity type is P-type, and the second conductivity type is N-type. According to an embodiment of the present invention, the first well region W1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions may be implanted in the region of the predetermined first well region W1 to form the first well region W1.

The second well region W2 is formed in the first well region W1 and has a second conductivity type. According to an embodiment of the present invention, the second well region W2 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the region of the predetermined second well region W2 to form the second well region W2.

The third well region W3 is formed in the semiconductor substrate SUB and is connected to the first well region W1, wherein the third well region W3 has the first conductivity type. According to an embodiment of the present invention, the third well region W3 can also be formed by an ion implantation step. For example, boron ions or indium ions may be implanted in the region where the third well region W3 is scheduled to be formed to form the third well region W3. In this embodiment, the doping concentration of the third well region W3 is higher than the doping concentration of the semiconductor substrate SUB.

The fourth well area W4 is formed in the first well area W1 and is located between the second well area W2 and the third well area W3, wherein the fourth well area W4 has the first conductivity type. According to an embodiment of the present invention, the fourth well region W4 can also be formed by an ion implantation step. For example, boron ions or indium ions may be implanted in the region where the fourth well region W4 is scheduled to be formed to form the fourth well region W4. In this embodiment, the doping concentration of the fourth well region W4 is higher than the doping concentration of the semiconductor substrate SUB.

According to an embodiment of the present invention, the first conductivity type and the second conductivity type are different. In other words, the first well region W1 and the second well region W2 have the same conductivity type, and the semiconductor substrate SUB, the third well region W3 and the fourth well region W4 have the same conductivity type.

As shown in FIG. 4, the transistor 400 further includes a first top doped region TOP1 and a second top doped region TOP2. The first top doped region TOP1 is formed in the first well region W1 and is located between the second well region W2 and the fourth well region W4, wherein the first top doped region TOP1 has the first conductivity type. According to an embodiment of the present invention, the first top doped region TOP1 and the second well region W2 are connected to each other. The second top doped region TOP2 is formed in the fourth well region W4 and has the first conductivity type.

As shown in FIG. 4, the transistor 400 further includes a first doped region D1, a third doped region D3, a fourth doped region D4, and a fifth doped region D5. The first doped region D1 is formed in the second top doped region TOP2 and has the first conductivity type. According to an embodiment of the present invention, the doping concentration of the first doping region D1 is higher than the doping concentration of the second top doping region TOP2 and higher than the doping concentration of the fourth well region W4.

The third doped region D3 is formed in the second well region W2 and has the second conductivity type. According to an embodiment of the present invention, the doping concentration of the third doping region D3 is higher than the doping concentration of the second well region W2. The fourth doped region D4 is formed in the first well region W1 and has the second conductivity type.

As shown in Figure 4, the fourth doped region D4 is located between the third well region W3 and the fourth well region W4. According to an embodiment of the present invention, the doping concentration of the fourth doping region D4 is higher than the doping concentration of the third well region W3.

The fifth doped region D5 is formed in the third well region W3 and has the first conductivity type. According to an embodiment of the present invention, the doping concentration of the fifth doping region D5 is higher than the doping concentration of the third well region W3.

As shown in FIG. 4, the transistor 400 further includes a first isolation structure ISO1, a second isolation structure ISO2, a third isolation structure ISO3, and a fourth isolation structure ISO4. The first isolation structure ISO1 is located between the first doped region D1 and the third doped region D3 to separate the first doped region D1 and the third doped region D3.

As shown in FIG. 4, the first isolation structure ISO1 directly contacts the first doped region D1 and the third doped region D3, but it is not intended to limit the present invention. According to other embodiments of the present invention, the first isolation structure ISO1 does not contact at least one of the first doped region D1 and the third doped region D3.

The second isolation structure ISO2 is located between the first doped region D1 and the fourth doped region D4 to separate the first doped region D1 and the fourth doped region D4. As shown in FIG. 2, the second isolation structure ISO2 directly contacts the first doped region D1 and the fourth doped region D4, but it is not intended to limit the present invention. According to other embodiments of the present invention, the second isolation structure ISO2 does not contact at least one of the first doped region D1 and the fourth doped region D4.

The third isolation structure ISO3 is located between the fourth doped region D4 and the fifth doped region D5 to separate the fourth doped region D4 and the fifth doped region D5. As shown in FIG. 2, the third isolation structure ISO3 directly contacts the fourth doped region D4 and the fifth doped region D5, but it is not used to limit the present invention. According to other embodiments of the present invention, the third isolation structure ISO3 does not contact at least one of the fourth doped region D4 and the fifth doped region D5.

The fourth isolation structure ISO4 is adjacent to the fifth doped region D5 for separating the fifth doped region D5 from other semiconductor structures. As shown in FIG. 4, the fourth isolation structure ISO4 directly contacts the fifth doped region D5, but it is not used to limit the present invention. According to other embodiments of the present invention, the fourth isolation structure ISO4 does not contact the fifth doped region D5.

As shown in FIG. 4, the transistor 400 further includes a first interconnection structure IC1, a second interconnection structure IC2, a third interconnection structure IC3, and a fourth interconnection structure IC4. The first interconnection structure IC1 is used to electrically connect the first doped region D1 to the first gate electrode EG1, where the first gate electrode EG1 corresponds to the gate terminal G of the transistor 110 in FIG. 1, where the gate The extreme G system is in a floating state.

The second interconnection structure IC2 is used to electrically connect the third doped region D3 to the first drain electrode ED1, wherein the first drain electrode ED1 corresponds to the drain terminal D of the transistor 110 in FIG. 1. In other words, the first drain electrode ED1 is coupled to the input/output pad 120 in FIG. 1. The third internal connection IC3 is used to electrically connect the fourth doped region D4 to the first source electrode ES1, wherein the first source electrode ES1 corresponds to the source terminal S of the transistor 110 in FIG. 1. In other words, the first source electrode ES1 is coupled to the internal circuit 130 through the resistor R in FIG. 1.

The fourth interconnection structure IC4 is used to electrically connect the fifth doped region D5 to the first base electrode EB1, wherein the first base electrode EB1 corresponds to the base terminal B of the transistor 110 in FIG. 1. In other words, the first base electrode EB1 is coupled to the ground terminal.

According to an embodiment of the present invention, the first gate electrode EG1, the first drain electrode ED1, the first source electrode ES1, and the first base electrode EB1 can be implemented by using the same or different metal layers.

FIG. 5 shows a cross-sectional view of an ESD protection transistor according to an embodiment of the present invention, wherein the ESD protection transistor 500 corresponds to the ESD protection transistor 240 in FIG. 2. As shown in FIG. 5, the ESD protection transistor 500 includes a semiconductor substrate SUB, a first well region W1, a second well region W2, a fifth well region W5, and a third top doped region TOP3.

According to an embodiment of the present invention, the semiconductor substrate SUB of the ESD protection transistor 500 is the same as the semiconductor substrate SUB in FIG. 4, and the first well W1 of the ESD protection transistor 500 is the same as the first well in FIG. 4 The area W1 is the same. In other words, the ESD protection transistor 500 and the transistor 400 are connected to each other and are formed on the same semiconductor substrate SUB.

The fifth well region W5 is formed in the semiconductor substrate W5, is adjacent to the first well region W1, and has the first conductivity type. The third top doped region TOP3 is formed in the first well region W1, is located between the second well region W2 and the fifth well region W5, and is connected to the second well region W2, wherein the third top doped region TOP3 Has the first conductivity type.

As shown in FIG. 5, the ESD protection transistor 500 further includes a sixth doped region D6, a seventh doped region D7, and an eighth doped region D8. The sixth doped region D6 is formed in the second well region W2 and has the second conductivity type. The seventh doped region D7 is formed in the fifth well region W5 and has the first conductivity type. The eighth doped region D8 is formed in the fifth well region D5, is located between the first well region W1 and the seventh doped region D7, and has the second conductivity type.

As shown in FIG. 5, the ESD protection transistor 500 further includes a fifth isolation structure ISO5, a sixth isolation structure ISO6, and a seventh isolation structure ISO7. The fifth isolation structure ISO5 is located between the sixth doped region D6 and the fifth well region W5, and is located above the third top doped region TOP3. As shown in FIG. 5, the fifth isolation structure ISO5 does not contact the sixth doped region D6 and the fifth well region W5, but it is not used to limit the present invention. According to other embodiments of the present invention, the fifth isolation structure ISO5 can directly contact the sixth doped region D6.

The sixth isolation structure ISO6 is located between the seventh doped region D7 and the eighth doped region D8 to separate the seventh doped region D7 and the eighth doped region D8. As shown in FIG. 5, the sixth isolation structure ISO6 directly contacts the seventh doped region D7 and the eighth doped region D8, but it is not used to limit the present invention. According to other embodiments of the present invention, the sixth isolation structure ISO6 does not contact at least one of the seventh doped region D7 and the eighth doped region D8.

The seventh isolation structure ISO7 is adjacent to the seventh doped region D7 for separating the seventh doped region D7 from other semiconductor structures. As shown in FIG. 5, the seventh isolation structure ISO7 directly contacts the seventh doped region D7, but it is not used to limit the present invention. According to other embodiments of the present invention, the seventh isolation structure ISO7 does not contact the seventh doped region D7.

As shown in FIG. 5, the ESD protection transistor 500 further includes a first gate structure PLY1 and a second gate structure PLY2. The first gate structure PLY1 is formed on the third top doped region TOP3 and covers the fifth isolation structure ISO5. The second gate structure PLY2 is formed on the first well region W1 and the fifth well region W5, is located between the third top doped region TOP3 and the eighth doped region D8, and covers the fifth isolation structure ISO5.

As shown in FIG. 5, the ESD protection transistor 500 further includes a fifth interconnection structure IC5, a sixth interconnection structure IC6, a seventh interconnection structure IC7, an eighth interconnection structure IC8, and a ninth interconnection structure IC9. The fifth interconnection structure IC5 is used to electrically connect the sixth doped region D6 to the second drain electrode ED2. The sixth interconnection structure IC6 is used to electrically connect the first gate structure PLY1 to the second electrode ED2, wherein the second drain electrode ED2 is coupled to the input/output pad 120.

The seventh interconnect structure IC7 is used to electrically connect the seventh doped region D7 to the second base electrode EB2, and the eighth interconnect structure IC8 is used to electrically connect the eighth doped region D8 to the second source electrode ES2, the ninth interconnection structure IC9 is used to electrically connect the second gate structure PLY2 to the second gate electrode EG2, wherein the second gate electrode EG2, the second source electrode ES2, and the second base electrode EB2 are all Coupled to the ground terminal.

According to an embodiment of the present invention, when the input/output pad 120 receives the electrostatic discharge current IESD, the parasitic bipolar junction formed by the sixth doped region D6, the seventh doped region D7, and the eighth doped region D8 The transistor is turned on, and the electrostatic discharge current IESD is quickly discharged to the ground terminal, thereby protecting the transistor 110 and the internal circuit 130 from collapse and damage.

FIG. 6 shows a top view of the transistor and the electrostatic discharge protection transistor according to an embodiment of the present invention. As shown in FIG. 6, the cross-sectional view of the dotted line from point A to point A'is shown in FIG. 4, and the cross-sectional view of the dotted line from point X to point X'is shown in FIG. 5. In other words, the transistor 400 and the ESD protection transistor 500 form a surrounding structure.

As shown in FIG. 6, the first doped region D1, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 of the circuit layout 600 are centered on the third doped region D3 A surrounding structure is formed, in which the arrangement of the first doped region D1, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 of the circuit layout 600 is as shown in FIG. 4.

The sixth doped region D6, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region D8 of the circuit layout 600 are formed with the sixth doped region D6 as the center Surrounding structure, in which the sixth doped region D6, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region D8 are arranged in the arrangement of the sixth doped region D6 As shown in Figure 5.

As shown in FIG. 6, the third doped region D3 and the sixth doped region D6 are connected to each other to form the center of the surrounding structure, and the fifth doped region D5 is connected to the seventh doped region D7. According to an embodiment of the present invention, the circuit layout 600 corresponds to the transistor 110 and the ESD protection transistor 240 in FIG. 2.

FIG. 7 shows a cross-sectional view of the silicon controlled rectifier according to an embodiment of the present invention. The silicon controlled rectifier 700 corresponds to the silicon controlled rectifier 340 in FIG. 3. Comparing the silicon controlled rectifier 700 in FIG. 7 with the ESD protection transistor 500 in FIG. 5, the silicon controlled rectifier 700 further includes a ninth doped region D9.

The ninth doped region D9 is formed in the first well region W1 and is connected to the sixth doped region D6, and the ninth doped region D9 has the first conductivity type. As shown in FIG. 7, the fifth interconnection structure IC5 couples the sixth doped region D6 and the ninth doped region D9 to the second drain electrode ED2, wherein the second drain electrode ED2 is coupled to Input/output pad 120.

As shown in FIG. 7, the fifth isolation structure ISO5 is located between the ninth doped region D9 and the fifth well region W5, and is located on the third top doped region TOP3. As shown in FIG. 7, the fifth isolation structure ISO5 does not contact the ninth doped region D9 and the fifth well region W5, but it is not used to limit the present invention. According to other embodiments of the present invention, the fifth isolation structure ISO5 can directly contact the ninth doped region D9.

According to an embodiment of the present invention, when the input/output pad 120 receives the electrostatic discharge current IESD, the sixth doped region D6, the ninth doped region D9, the seventh doped region D7, and the eighth doped region D8 The formed silicon controlled rectifier is turned on, and the electrostatic discharge current IESD is quickly discharged to the ground terminal, thereby protecting the transistor 110 and the internal circuit 130 from collapse and damage.

FIG. 8 is a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention. As shown in Figure 8, the cross-sectional view of the dotted line from point A to point A'is shown in Figure 4, and the cross-sectional view of the dotted line from point X to point X" is shown in Figure 7. In other words, electricity The crystal 400 and the electrostatic discharge protection transistor 700 form a surrounding structure.

As shown in FIG. 8, the first doped region D1, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 of the circuit layout 800, and the first doped region D1 of the circuit layout 800 The arrangement of the third doped region D3, the fourth doped region D4, and the fifth doped region D5 is as shown in FIG. 4.

The sixth doped region D6, the ninth doped region D9, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region D8 of the circuit layout 800 are based on the sixth doped region. The doped region D6 is the center to form a surrounding structure, wherein the sixth doped region D6, the ninth doped region D9, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region The arrangement of the region D8 with the sixth doped region D6 is as shown in FIG. 7.

As shown in FIG. 8, the third doped region D3 and the sixth doped region D6 are connected to each other to form the center of the surrounding structure, and the fifth doped region D5 is connected to the seventh doped region D7. According to an embodiment of the present invention, the circuit layout 800 corresponds to the transistor 110 and the silicon controlled rectifier 340 in FIG. 3.

Figure 9 is a cross-sectional view of a transistor according to another embodiment of the present invention. Comparing the transistor 900 in FIG. 9 with the transistor 400 in FIG. 4, the transistor 900 further includes a second doped region D2. As shown in FIG. 9, the second doped region D2 is formed in the second top doped region TOP2 and is connected to the first doped region D1, and the second doped region D2 has the second conductivity type. As shown in Figure 9, the second doped region D2 is located between the first doped region D1 and the third doped region D3, and the first interconnection structure IC1 combines the first doped region D1 and the second doped region D1. The area D2 is also electrically connected to the first gate electrode EG1.

According to an embodiment of the present invention, the first gate electrode EG1 is coupled to the ground terminal. According to an embodiment of the present invention, when the gate terminal G of the transistor 110 in FIG. 1 is coupled to the ground terminal, the transistor 900 corresponds to the transistor 110 in FIG. 1. When the input/output pad 120 of Figure 1 receives the electrostatic discharge current IESD, the first doped region D1, the second doped region D2, and the third doped region D3 of the transistor 900 corresponding to the transistor 110 are formed The parasitic bipolar junction transistor is turned on, so that the electrostatic discharge current IESD can be quickly discharged to the ground terminal through the gate electrode EG.

Therefore, the combination of the parasitic bipolar junction transistor of the transistor 900 and the electrostatic discharge protection device 140 can further improve the protection capability of the internal circuit 130. In other words, the combination of the transistor 900 in Figure 9 and the ESD protection transistor 500 in Figure 5 and the combination of the transistor 900 in Figure 9 and the silicon controlled rectifier 700 in Figure 7 can further enhance the transistor 110 And the resistance of the internal circuit 130 against electrostatic discharge.

FIG. 10 is a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention. As shown in Figure 11, the cross-sectional view of the dotted line from point A to point A" is shown in Figure 9, and the cross-sectional view of the dotted line from point X to point X'is shown in Figure 5. In other words, electricity The crystal 900 and the electrostatic discharge protection transistor 500 form a surrounding structure.

As shown in Figure 10, the first doped region D1, the second doped region D2, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 of the circuit layout 1000 are in the third The doped region D3 is the center to form a surrounding structure, wherein the first doped region D1, the second doped region D2, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 of the circuit layout 1100 The arrangement is shown in Figure 9.

The sixth doped region D6, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region D8 of the circuit layout 1000 are formed with the sixth doped region D6 as the center The surrounding structure, wherein the arrangement of the sixth doped region D6, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region D8 is as shown in FIG. 5.

As shown in FIG. 10, the third doped region D3 and the sixth doped region D6 are connected to each other to form the center of the surrounding structure, and the fifth doped region D5 is connected to the seventh doped region D7. According to an embodiment of the present invention, the circuit layout 1000 corresponds to the transistor 110 and the ESD protection transistor 240 in FIG. 2, wherein the gate terminal G of the transistor 110 in FIG. 2 is coupled to the ground terminal.

FIG. 11 shows a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention. As shown in FIG. 11, the cross-sectional view of the dotted line from point A to point A" is shown in FIG. 9, and the cross-sectional view of the dotted line from point X to point X" is shown in FIG. 7. In other words, the transistor 900 and the ESD protection transistor 700 form a surrounding structure.

As shown in FIG. 11, the first doped region D1, the second doped region D2, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 of the circuit layout 1100, wherein the circuit layout 800 The arrangement of the first doped region D1, the second doped region D2, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 is as shown in FIG. 9.

The sixth doped region D6, the ninth doped region D9, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region D8 of the circuit layout 1100 are based on the sixth doped region. The doped region D6 is the center to form a surrounding structure, wherein the sixth doped region D6, the ninth doped region D9, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region The arrangement of area D8 is shown in Figure 7.

As shown in FIG. 11, the third doped region D3 and the sixth doped region D6 are connected to each other to form the center of the surrounding structure, and the fifth doped region D5 is connected to the seventh doped region D7. According to an embodiment of the present invention, the circuit layout 1100 corresponds to the transistor 110 and the silicon controlled rectifier 340 in FIG. 3, wherein the gate terminal G of the transistor 110 in FIG. 3 is coupled to the ground terminal.

Fig. 12 is a cross-sectional view of a transistor according to another embodiment of the present invention. Comparing the transistor 1200 in FIG. 12 with the transistor 900 in FIG. 9, the first doped region D1 of the transistor 1200 is located between the second doped region D2 and the third doped region D3. According to an embodiment of the present invention, the current gain of transistor 900 in Fig. 9 is greater than the current gain of transistor 1200 in Fig. 12. The current gain is the collector current and base current of the bipolar junction transistor Ratio.

FIG. 13 is a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention. As shown in Figure 13, the cross-sectional view of the dotted line from point A to point A" is shown in Figure 12, and the cross-sectional view of the dotted line from point X to point X'is shown in Figure 5. In other words, electricity The crystal 1200 and the electrostatic discharge protection transistor 500 form a surrounding structure.

As shown in FIG. 13, the first doped region D1, the second doped region D2, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 of the circuit layout 1300 are in the third The doped region D3 is the center to form a surrounding structure, wherein the first doped region D1, the second doped region D2, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 of the circuit layout 1300 The arrangement is shown in Figure 12. Comparing the circuit layout 1300 in FIG. 13 with the circuit layout 1000 in FIG. 10, the difference lies in the relative positions of the first doped region D1 and the second doped region D2.

The sixth doped region D6, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region D8 of the circuit layout 1300 are formed with the sixth doped region D6 as the center The surrounding structure, wherein the arrangement of the sixth doped region D6, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region D8 is as shown in FIG. 5.

As shown in FIG. 13, the third doped region D3 and the sixth doped region D6 are connected to each other to form the center of the surrounding structure, and the fifth doped region D5 is connected to the seventh doped region D7. According to an embodiment of the present invention, the circuit layout 1300 corresponds to the transistor 110 and the ESD protection transistor 240 in FIG. 2, wherein the gate terminal G of the transistor 110 in FIG. 2 is coupled to the ground terminal.

FIG. 14 is a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention. As shown in Fig. 14, the cross-sectional view of the dotted line from point A to point A" is shown in Fig. 12, and the cross-sectional view of the broken line from point X to point X" is shown in Fig. 7. In other words, the transistor 1200 and the ESD protection transistor 700 form a surrounding structure.

As shown in FIG. 14, the first doped region D1, the second doped region D2, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 of the circuit layout 1400, in which the circuit layout 800 The arrangement of the first doped region D1, the second doped region D2, the third doped region D3, the fourth doped region D4, and the fifth doped region D5 is as shown in FIG.

The sixth doped region D6, the ninth doped region D9, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region D8 of the circuit layout 1400 are based on the sixth doped region. The doped region D6 is the center to form a surrounding structure, wherein the sixth doped region D6, the ninth doped region D9, the first gate structure PLY1, the second gate structure PLY2, the seventh doped region D7, and the eighth doped region The arrangement of area D8 is shown in Figure 7.

As shown in FIG. 14, the third doped region D3 and the sixth doped region D6 are connected to each other to form the center of the surrounding structure, and the fifth doped region D5 is connected to the seventh doped region D7. According to an embodiment of the present invention, the circuit layout 1400 corresponds to the transistor 110 and the silicon controlled rectifier 340 in FIG. 3, wherein the gate terminal G of the transistor 110 in FIG. 3 is coupled to the ground terminal.

FIG. 15 is a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention. As shown in FIG. 15, the cross-sectional view of the dotted line from point A to point A'is shown in FIG. 4, and the cross-sectional view of the dotted line from point X to point X'is shown in FIG. 5. In other words, the transistor 400 and the ESD protection transistor 500 are cross-spaced to form a surrounding structure of the circuit layout 1500.

FIG. 16 shows a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention. As shown in Figure 16, the cross-sectional view of the dotted line from point A to point A'is shown in Figure 4, and the cross-sectional view of the dotted line from point X to point X" is shown in Figure 7. In other words, electricity The crystal 400 and the ESD protection transistor 700 are cross-spaced to form a surrounding structure of the circuit layout 1600.

The present invention proposes an electrostatic discharge protection device that can be combined with a transistor, so that the electrostatic protection capability of an integrated circuit is improved under the condition of increasing a limited circuit area. The present invention further proposes the electrostatic discharge protection capability of the transistor itself. After being equipped with an electrostatic discharge protection element, the electrostatic discharge protection capability is further improved to a new level.

Although the embodiments of the present disclosure and their advantages have been disclosed as above, it should be understood that anyone with ordinary knowledge in the relevant technical field can make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the protection scope of the present disclosure is not limited to the manufacturing processes, machines, manufacturing, material composition, devices, methods, and steps in the specific embodiments described in the specification. Anyone with ordinary knowledge in the technical field can implement some implementations from this disclosure. The disclosed content of the examples understands the current or future developed processes, machines, manufacturing, material composition, devices, methods, and steps, as long as they can implement substantially the same functions or obtain substantially the same results in the embodiments described herein. The present disclosure uses some embodiments. Therefore, the protection scope of the present disclosure includes the above-mentioned manufacturing processes, machines, manufacturing, material composition, devices, methods, and steps. In addition, each patent application scope constitutes an individual embodiment, and the protection scope of the present disclosure also includes each patent application scope and a combination of embodiments.

100, 200, 300, 700: integrated circuit 110, 400, 900, 1200: Transistor 120: input/output pad 130: internal circuit 140: Electrostatic discharge protection device 240,500: Electrostatic discharge protection transistor 340,700: Silicon controlled rectifier 600, 800, 1000, 1100, 1300, 1400: circuit layout R: resistance G: gate extreme S: Source extreme D:Extreme B: Base extreme IESD: Electrostatic discharge current SUB: Semiconductor substrate W1: The first well area W2: The second well area W3: The third well area W4: The fourth well area W5: The fifth well area TOP1: The first top doped area TOP2: the second top doped region TOP3: The third top doped region D1: the first doped region D2: second doped region D3: third doped region D4: Fourth doped region D5: fifth doped region D6: sixth doped region D7: seventh doped region D8: Eighth doped region D9: Ninth doped region ISO1: The first isolation structure ISO2: Second isolation structure ISO3: Third isolation structure ISO4: Fourth isolation structure ISO5: Fifth isolation structure ISO6: The sixth isolation structure ISO7: Seventh isolation structure PLY1: first gate structure PLY2: second gate structure IC1: The first interconnection structure IC2: second interconnect structure IC3: The third interconnection structure IC4: Fourth interconnect structure IC5: Fifth interconnect structure IC6: The sixth interconnection structure IC7: seventh interconnect structure IC8: Eighth interconnect structure IC9: Ninth interconnect structure EG1: first gate electrode ED1: first drain electrode ES1: First source electrode EB1: first base electrode EG2: second gate electrode ED2: second drain electrode ES2: second source electrode EB2: second base electrode

Figure 1 is a circuit diagram of an integrated circuit according to an embodiment of the present invention; Figure 2 is a circuit diagram of an integrated circuit according to another embodiment of the present invention; Figure 3 is a circuit diagram of an integrated circuit according to another embodiment of the present invention; Figure 4 is a cross-sectional view of the transistor according to an embodiment of the present invention; Figure 5 shows a cross-sectional view of an electrostatic discharge protection transistor according to an embodiment of the present invention; Fig. 6 shows a top view of the transistor and the electrostatic discharge protection transistor according to an embodiment of the present invention; Figure 7 is a cross-sectional view of the silicon controlled rectifier according to an embodiment of the present invention; Fig. 8 shows a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention; Figure 9 is a cross-sectional view of a transistor according to another embodiment of the present invention; FIG. 10 shows a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention; Figure 11 shows a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention; Figure 12 shows a cross-sectional view of a transistor according to another embodiment of the present invention; Figure 13 shows a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention; Figure 14 is a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention; FIG. 15 shows a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention; and FIG. 16 shows a top view of a transistor and an electrostatic discharge protection transistor according to another embodiment of the present invention.

300: Integrated circuit

110: Transistor

120: input/output pad

130: internal circuit

340: Silicon Controlled Rectifier

R: resistance

G: gate extreme

S: Source extreme

D:Extreme

B: Base extreme

IESD: Electrostatic discharge current

Claims (12)

A semiconductor device for protecting an internal circuit, comprising: a transistor including a gate terminal, a source terminal, a drain terminal, and a base terminal, wherein the source terminal is coupled to the internal circuit, and the drain terminal is coupled To an input/output pad, the base terminal is coupled to a ground terminal, wherein the transistor includes: a semiconductor substrate with a first conductivity type; a first well region with a second conductivity type and is formed In the above-mentioned semiconductor substrate; a second well region having the above-mentioned second conductivity type and formed in the above-mentioned first well region; a third well region having the above-mentioned first conductivity type, formed in the above-mentioned semiconductor substrate and being formed in the above-mentioned semiconductor substrate The first well area is connected to each other; a fourth well area having the first conductivity type is formed in the first well area and is located between the second well area and the third well area; a first top The doped region has the above-mentioned first conductivity type, is formed in the above-mentioned first well region and is located between the above-mentioned second well region and the above-mentioned fourth well region, wherein the first top doped region is the same as the second well region Mutually connected; a second top doped region having the above-mentioned first conductivity type and formed in the above-mentioned fourth well region; A first doped region having the first conductivity type is formed in the second top doped region, wherein the first doped region forms the gate terminal; a third doped region has the second conductivity type , Formed in the second well region, wherein the third doped region forms the drain terminal; a fourth doped region having the second conductivity type is formed in the first well region and is located in the third well Region and the fourth well region, wherein the fourth doped region forms the source terminal; and a fifth doped region having the first conductivity type is formed in the third well region, wherein the fifth doped region The doped region forms the base terminal; and an electrostatic discharge protection device coupled between the input/output pad and the ground terminal, wherein when the input/output pad receives an electrostatic discharge current, the electrostatic discharge The protection device removes the above-mentioned electrostatic discharge current to the above-mentioned ground terminal. The semiconductor device of claim 1, wherein the electrostatic discharge protection device includes: a fifth well region having the first conductivity type, formed in the semiconductor substrate and adjacent to the first well region; and a third top dopant The miscellaneous region has the first conductivity type, is formed in the first well region and is located between the second well region and the fifth well region, wherein the third top doped region and the second well region are mutually Connection; a sixth doped region having the above-mentioned second conductivity type and formed in the above-mentioned second well region; a seventh doped region having the above-mentioned first conductivity type and formed in the above-mentioned fifth well In the region; an eighth doped region having the above-mentioned second conductivity type, formed in the above-mentioned fifth well region, and located between the above-mentioned first well region and the above-mentioned seventh doped region; a first gate structure, Formed on the third top doped region, wherein the sixth doped region and the first gate structure are coupled to the input/output pad; and a second gate structure is formed on the first well Above the fifth well region and between the third top doped region and the eighth doped region, wherein the second gate structure, the seventh doped region, and the eighth doped region It is coupled to the above-mentioned ground terminal. The semiconductor device of claim 2, wherein the electrostatic discharge protection device is an electrostatic discharge protection transistor. The semiconductor device of claim 2, wherein the electrostatic discharge protection device further includes: a ninth doped region having the first conductivity type, formed in the first well region, and connected to the sixth doped region , Wherein the ninth doped region is coupled to the input/output pad, and the gate terminal of the transistor is in a floating state. The semiconductor device of claim 2, wherein the transistor further includes: a second doped region having the second conductivity type, formed in the second top doped region, and connected to the first doped region . The semiconductor device of claim 5, wherein the first doped region is located between the second doped region and the third doped region. The semiconductor device of claim 5, wherein the second doped region is Located between the first doped region and the third doped region. The semiconductor device of claim 5, wherein the gate terminal is coupled to the ground terminal. The semiconductor device of claim 8, wherein when the drain terminal receives the electrostatic discharge current, the third doped region, the first doped region, and the second doped region form a bipolar transistor for The electrostatic discharge current is discharged to the ground terminal through the gate terminal, thereby protecting the internal circuit. The semiconductor device of claim 2, wherein the first doped region, the fourth doped region, and the fifth doped region surround the third doped region. The semiconductor device of claim 10, wherein the seventh doped region and the eighth doped region surround the sixth doped region. The semiconductor device of claim 11, wherein the third doped region and the sixth doped region are connected to each other, and the first doped region, the third doped region, the fourth doped region, and the fifth doped region are connected to each other. The miscellaneous region, the sixth doped region, the seventh doped region, and the eighth doped region jointly form a surrounding structure.

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