TWI678788B - Semiconductor structure and esd protection device - Google Patents

Abstract

A semiconductor structure includes a first P-type well, a first P-type diffusion region, a first N-type well, a first N-type diffusion region, a second P-type diffusion region, and a first polycrystalline silicon layer. The first P-type diffusion region is disposed within the first P-type well and is coupled to the first electrode. The first N-type well is adjacent to the first P-type well. The first N-type diffusion region is disposed within the first N-type well. The second P-type diffusion region is disposed between the first P-type diffusion region and the first N-type diffusion region, and is disposed within the first N-type well. The second P-type diffusion region and the first N-type diffusion region are coupled to the second electrode. The first polycrystalline silicon layer is disposed on the first P-type diffusion region.

Description

Semiconductor structure and electrostatic protection device

The invention relates to a semiconductor structure, and more particularly to a semiconductor structure as an electrostatic protection device.

Integrated circuit systems can be severely damaged due to various electrostatic discharge events. A major electrostatic discharge mechanism is derived from the human body, which is called the Human Body Model (HBM). The human body is within 100 nanoseconds ( nano-second), a tip current of several amperes is generated to the integrated circuit and the circuit is burned. The second type of electrostatic discharge mechanism is derived from metal objects, called Machine Model (MM), which generates a much higher rise time and current level than the human body discharge mode. The third type of electrostatic discharge mechanism is the Charged-Device Model (CDM), in which the integrated circuit itself accumulates charges and discharges to the ground terminal within a rise time of less than 0.5 nanoseconds. Therefore, we need effective electrostatic protection devices to protect integrated circuits from the danger of electrostatic discharge.

In view of this, the present invention provides a semiconductor structure including: a first P-type well, a first P-type diffusion region, a first N-type well, a first N-type diffusion region, and a second P-type diffusion region. And a first polycrystalline silicon layer. The first P-type diffusion region is disposed in the first P-type well and is coupled to a first electrode. The first N-type well is adjacent to the first P-type well. The first N-type diffusion region is disposed in the first N-type well. The second P-type diffusion region is disposed between the first P-type diffusion region and the first N-type diffusion region, and is disposed within the first N-type well, wherein the second P-type diffusion region and the first An N-type diffusion region is coupled to a second electrode. The first polycrystalline silicon layer is disposed on the first P-type diffusion region.

According to an embodiment of the present invention, the semiconductor structure further includes an epitaxial layer, a second P-type well, and a second N-type well. The second P-type well is disposed above the epitaxial layer, and the first P-type well system is disposed within the first P-type well. The second N-type well is disposed above the epitaxial layer and adjacent to the second P-type well, wherein the first N-type well system is disposed within the second N-type well, wherein the epitaxial layer system It is N type.

According to an embodiment of the present invention, the first polycrystalline silicon layer is coupled to the first electrode.

According to another embodiment of the present invention, the first polycrystalline silicon layer is floating.

According to an embodiment of the present invention, the semiconductor structure further includes a first oxidation protection layer and a shallow trench isolation region. The first oxidation protection layer is formed on the second P-type diffusion region and is adjacent to the first polycrystalline silicon layer. The oxidation protection layer and the first polycrystalline silicon layer have a first distance. The shallow trench isolation region is formed between the first P-type diffusion region and the second P-type diffusion region.

According to an embodiment of the present invention, the first P-type diffusion region and the shallow trench isolation region have a second pitch, and the second type diffusion region is directly Coupled to the shallow trench isolation area.

According to another embodiment of the present invention, the first polycrystalline silicon layer is disposed on the first P-type diffusion region and the second P-type diffusion region.

According to an embodiment of the invention, the semiconductor structure further includes a second polycrystalline silicon layer. The second polycrystalline silicon layer is disposed on the second P-type diffusion region and the first N-type diffusion region. The second polycrystalline silicon layer is floating.

The invention further provides an electrostatic protection device for discharging the electrostatic charge of a first electrode to a second electrode, including: a first P-type well, a first P-type diffusion region, a first N-type well, A first N-type diffusion region, a second P-type diffusion region, and a first polycrystalline silicon layer. The first P-type diffusion region is disposed within the first P-type well and is coupled to the first electrode. The first N-type well is adjacent to the first P-type well. The first N-type diffusion region is disposed in the first N-type well. The second P-type diffusion region is disposed between the first P-type diffusion region and the first N-type diffusion region, and is disposed within the first N-type well, wherein the second P-type diffusion region and the first An N-type diffusion region is coupled to the second electrode. The first polycrystalline silicon layer is disposed on the first P-type diffusion region.

According to an embodiment of the present invention, the first polycrystalline silicon layer is coupled to the first electrode.

According to another embodiment of the present invention, the first polycrystalline silicon layer is floating.

According to an embodiment of the present invention, the electrostatic protection device further includes: a first oxidation protection layer and a shallow trench isolation area. The first oxidation protection layer is formed on the second P-type diffusion region and is adjacent to the first polycrystalline silicon layer. The oxidation protection layer and the first polycrystalline silicon layer have a first distance. on The shallow trench isolation region is formed between the first P-type diffusion region and the second P-type diffusion region.

According to an embodiment of the present invention, the first P-type diffusion region and the shallow trench isolation region have a second pitch, and the second type diffusion region is directly coupled to the shallow trench isolation region.

According to another embodiment of the present invention, the first polycrystalline silicon layer is disposed on the first P-type diffusion region and the second P-type diffusion region.

According to an embodiment of the present invention, the ESD protection device further includes: a second polycrystalline silicon layer. The second polycrystalline silicon layer is disposed on the second P-type diffusion region and the first N-type diffusion region. The second polycrystalline silicon layer is floating.

100, 200, 300, 400, 500‧‧‧ semiconductor structures

600, 700, 800, 900, 1000‧‧‧ semiconductor structures

110‧‧‧The first P-type diffusion zone

120‧‧‧Second P-type diffusion zone

130‧‧‧The first N-type diffusion zone

141, 541, 641, 741, 841, 941, 1043 ‧‧‧ the first polycrystalline silicon layer

142‧‧‧Oxidation protective layer

151‧‧‧first electrode

152‧‧‧Second electrode

160‧‧‧Shallow trench isolation zone

943, 1043‧‧‧‧Second polycrystalline silicon layer

PW1‧‧‧The first P-well

PW2‧‧‧Second P-well

NW1‧‧‧The first N type well

NW2‧‧‧Second N-well

EPI‧‧‧Epitaxial Layer

S1‧‧‧First Pitch

S2‧‧‧Second Pitch

FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention; FIG. 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention; A cross-sectional view of a semiconductor structure according to another embodiment of the invention; FIG. 4 is a cross-sectional view of a semiconductor structure according to another embodiment of the invention; FIG. 5 is a cross-sectional view of another embodiment of the invention A cross-sectional view of the semiconductor structure; FIG. 6 shows a semiconductor structure according to another embodiment of the present invention. FIG. 7 is a sectional view showing a semiconductor structure according to another embodiment of the present invention; FIG. 8 is a sectional view showing a semiconductor structure according to another embodiment of the present invention; FIG. 10 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention; and FIG. 10 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention.

In the following, the element substrate, the semiconductor device, and the manufacturing method of the semiconductor device according to some embodiments of the present disclosure are described in detail. It should be understood that the following description provides many different embodiments or examples for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only a simple and clear description of some embodiments of the disclosure. Of course, these are only examples and not the limitations of this disclosure. In addition, duplicate numbers or designations may be used in different embodiments. These repetitions are only for simply and clearly describing some embodiments of the present disclosure, and do not represent any correlation between the different embodiments and / or structures discussed. Furthermore, when referring to a first material layer on or above a second material layer, it includes the case where the first material layer is in direct contact with the second material layer. Alternatively, it is also possible to have one or more other material layers spaced apart, in which case the first material layer and the second material layer may not be in direct contact.

In addition, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe one element of the diagram The relative relationship of a piece to another component. It can be understood that if the illustrated device is turned upside down, the components described on the "lower" side will become the components on the "higher" side.

Here, the terms "about", "approximately", and "mostly" generally indicate within a given value or range within 20%, preferably within 10%, and more preferably within 5%, or 3 Within%, or within 2%, or within 1%, or within 0.5%. The quantity given here is an approximate quantity, that is, the meanings of "about", "approximately", and "approximately" can still be implied without specifying "about", "approximately", and "mostly".

It can be understood that although the terms "first", "second", "third" and the like can be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions , Layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, composition, region, layer, and / or portion discussed below may be referred to as a second element, composition, region, layer, and / or layer without departing from the teachings of some embodiments of the present disclosure. And / or parts.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary artisans to whom this disclosure belongs. Understandably, these terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the relevant technology and the background or context of this disclosure, and should not be in an idealized or overly formal manner Interpretation, unless specifically defined in the disclosed embodiments.

Some embodiments of the present disclosure can be understood together with the drawings, and the drawings of the embodiments of the present disclosure are also considered as part of the description of the embodiments of the present disclosure. What you need to know However, the drawings of the embodiments of the present disclosure are not drawn with the scale of actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings so as to clearly show the features of the disclosed embodiments. In addition, the structures and devices in the drawings are illustrated in a schematic manner so as to clearly show the characteristics of the embodiments of the disclosure.

In some embodiments of the disclosure, relative terms such as "down", "up", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be used Understand the orientation shown in this paragraph and related drawings. This relative term is for illustrative purposes only, and it does not mean that the device it describes needs to be manufactured or operated in a particular orientation. The terms of joining and connection, such as "connected", "interconnected", etc., unless specifically defined, may mean that two structures are in direct contact, or that two structures are not in direct contact, among which other structures are provided here Between the two structures. Moreover, the term about joining and connecting may also include a case where both structures are movable or both structures are fixed.

The embodiments of the present invention disclose the embodiments of the semiconductor device, and the above embodiments may be included in, for example, an integrated circuit (IC) of a microprocessor, a memory element, and / or other elements. The above integrated circuit can also include different passive and active microelectronic components, such as thin-film resistors, other types of capacitors, such as metal-insulator-metal capacitors (MIMCAP), and inductors. , Diodes, Metal-Oxide-Semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), lateral diffusion Type MOS transistor, high power MOS transistor or other type of transistor. Those having ordinary knowledge in the technical field to which the present invention pertains may understand The device is used to include other types of semiconductor elements in integrated circuits.

FIG. 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor structure 100 includes a first P-type well PW1 and a first N-type well NW1. The first P-type diffusion region 110 is disposed within the first P-type well PW1, and the second P-type diffusion region 120 and the first N-type diffusion region 130 are disposed within the first N-type well NW1.

According to an embodiment of the present invention, the semiconductor structure 100 further includes a first polycrystalline silicon layer 141 and an oxidation protection layer 142. As shown in FIG. 1, a first polycrystalline silicon layer 141 is formed on the first P-type diffusion region 110, and an oxide protection layer 142 is formed on the second P-type diffusion region 120 and the first N-type diffusion region 130. The first polycrystalline silicon layer 141 and the oxidation protection layer 142 have a first distance S1 therebetween.

According to an embodiment of the present invention, as shown in FIG. 1, the first polycrystalline silicon layer 141 is coupled to the first electrode 151. According to an embodiment of the present invention, the first N-type well NW1 series surrounds the first P-type well PW1. Therefore, in the sectional view of FIG. 1, the first N-type well NW1 series is shown as being located in the first P-type well PW1 On both sides.

As shown in FIG. 1, the first P-type diffusion region 110 is coupled to the first electrode 151, and the second P-type diffusion region 120 and the first N-type diffusion region 130 are coupled to the second electrode 152. According to an embodiment of the present invention, the first electrode 151 and the second electrode 152 are both metal layers.

As shown in FIG. 1, a shallow trench isolation region (STI) 160 is disposed between the first P-type diffusion layer 110, the second P-type diffusion layer 120, and the first N-type diffusion layer 130. The first P-type diffusion layer 110, the second P-type diffusion layer 120, and the first N-type diffusion layer 130 are electrically separated from each other.

According to an embodiment of the present invention, the first P-type diffusion region 110, the first An N-type diffusion region 130 and a second P-type diffusion region 120 form a PNP transistor. The first P-type diffusion region 110 is a collector and the first N-type diffusion region 130 is a base. The second P-type diffusion region 130 is an emitter.

According to an embodiment of the present invention, the semiconductor structure 100 shown in FIG. 1 is an electrostatic protection device. According to an embodiment of the present invention, the first electrode 151 is coupled to a supply voltage pad, and the second electrode 152 is coupled to a ground terminal. The semiconductor structure 100 is used to static electricity accumulated by the supply voltage pad. The charge is removed to ground.

According to another embodiment of the present invention, the first electrode 151 is coupled to the output and input pads, and the second electrode 152 is coupled to the ground. The semiconductor structure 100 is used to charge the electrostatic charges accumulated by the output and input pads Exclude to ground.

According to an embodiment of the present invention, the first polycrystalline silicon layer 141 may be used to generate a free electron-electric pair in the first P-type diffusion region 110, thereby increasing the protection capability of a machine model (MM) for electrostatic protection. According to an embodiment of the present invention, the protection capability of the machine discharge mode of the semiconductor structure 100 can reach 550V.

FIG. 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Compared with FIG. 1, the semiconductor structure 200 of FIG. 2 further includes a second P-type well PW2, a second N-type well NW2, and an epitaxial layer EPI. The first P-type well PW1 is formed in the second P-type well PW2, and the first N-type well NW1 is formed in the second N-type well NW2. The second P-type well PW2 and the second N-type well NW2 are formed on the epitaxial layer EPI. According to an embodiment of the present invention, the epitaxial layer EPI is N-type. According to an embodiment of the present invention, the second P-type well PW2, the second N-type well The well NW2 and the epitaxial layer EPI help to reduce the impedance of the path through which the electrostatic discharge passes, thereby effectively improving the protection capacity of the machine model (MM) of the electrostatic protection.

FIG. 3 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 300 in FIG. 3 with the semiconductor structure 100 in FIG. 1, the first P-type diffusion region 110 and the shallow trench isolation region 160 have a second distance S2 to increase the first P-type diffusion region 110 and The distance and impedance of the second P-type diffusion region 120 are beneficial to improve the protection capability of the machine model (MM) of the electrostatic protection.

FIG. 4 is a cross-sectional view showing a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 400 of FIG. 4 with FIG. 2, the first P-type diffusion region 110 of the semiconductor structure 400 of FIG. 4 has a second distance S2 from the shallow trench isolation region 160 to increase the first P-type diffusion. The distance between the region 110 and the second P-type diffusion region 120 is to improve the protection capability of the machine model (MM) of the electrostatic protection.

FIG. 5 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 500 in FIG. 5 with the semiconductor structure 100 in FIG. 1, the semiconductor structure 500 includes a first polycrystalline silicon layer 541, wherein the first polycrystalline silicon layer 541 is formed in the first P-type diffusion region 110. on. As shown in FIG. 5, the first polycrystalline silicon layer 541 is not electrically coupled to the first electrode 151. In other words, the first polycrystalline silicon layer 541 is in a floating state.

FIG. 6 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 600 of FIG. 6 with the half-body structure 200 of FIG. 2, the semiconductor structure 600 includes a first polycrystalline silicon layer 641, where The first polycrystalline silicon layer 641 is not electrically coupled to the first electrode 151. In other words, the first polycrystalline silicon layer 641 is in a floating state.

FIG. 7 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 700 of FIG. 7 with the semiconductor structure 100 of FIG. 1, the semiconductor structure 700 includes a first polycrystalline silicon layer 741. As shown in FIG. 7, the first polycrystalline silicon layer 741 is formed on the first P-type diffusion layer 110 and the second P-type diffusion layer 120 and extends from the first P-type diffusion layer 110 to the second P-type diffusion layer. 120, and the first polycrystalline silicon layer 741 is in a floating state.

According to an embodiment of the present invention, since the first polycrystalline silicon layer 741 extends from the first P-type diffusion layer 110 to the second P-type diffusion layer 120, the first pitch S1 shown in FIG. 1 can be omitted, and further, The circuit area occupied by the semiconductor structure 700 is reduced, thereby saving manufacturing costs. According to another embodiment of the present invention, the first polycrystalline silicon layer 741 may also be coupled to the first electrode 151 as shown in FIG. 1, which will not be repeated here.

FIG. 8 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 800 of FIG. 8 with the semiconductor structure 200 of FIG. 2, the semiconductor structure 800 includes a first polycrystalline silicon layer 841. As shown in FIG. 8, the first polycrystalline silicon layer 841 is formed on the first P-type diffusion layer 110 and the second P-type diffusion layer 120 and extends from the first P-type diffusion layer 110 to the second P-type diffusion layer. 120, and the first polycrystalline silicon layer 841 is in a floating state.

According to an embodiment of the present invention, since the first polycrystalline silicon layer 841 extends from the first P-type diffusion layer 110 to the second P-type diffusion layer 120, the first pitch S1 shown in FIG. 2 can be omitted, and the phase Compared with the semiconductor structure 200 shown in FIG. 2, the semiconductor structure 800 occupies a smaller circuit area, thereby saving manufacturing costs. according to In another embodiment of the present invention, the first polycrystalline silicon layer 841 may also be coupled to the first electrode 151 as shown in FIG. 2, which will not be repeated here.

FIG. 9 is a cross-sectional view showing a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 900 in FIG. 9 with the semiconductor structure 700 in FIG. 7, the semiconductor structure 900 includes a first polycrystalline silicon layer 941 and a second polycrystalline silicon layer 943. The oxidation protection layer 142 of the semiconductor structure 700 is composed of The second polycrystalline silicon layer 943 is replaced.

As shown in FIG. 9, the first polycrystalline silicon layer 941 is also formed on the first P-type diffusion layer 110 and the second P-type diffusion layer 120 and extends from the first P-type diffusion layer 110 to the second P-type diffusion layer. 120. A second polycrystalline silicon layer 943 is formed on the second P-type diffusion layer 120 and the first N-type diffusion layer 130.

According to an embodiment of the present invention, since the oxidation protection layer 142 of the semiconductor structure 700 of FIG. 7 is replaced by the second polycrystalline silicon layer 943, the first P-type diffusion layer 110, the second P-type diffusion layer 120, and the first Above the N-type diffusion layer 130 is a polycrystalline silicon layer, so the manufacturing cost of the mask for the oxidation protection layer can be saved.

According to an embodiment of the present invention, the first polycrystalline silicon layer 941 is in a floating state. According to another embodiment of the present invention, the first polycrystalline silicon layer 941 may also be coupled to the first electrode 151. According to an embodiment of the present invention, the second polycrystalline silicon layer 943 is in a floating state. According to another embodiment of the present invention, the second polycrystalline silicon layer 943 may also be coupled to the second electrode 152.

FIG. 10 is a cross-sectional view of a semiconductor structure according to another embodiment of the present invention. Comparing the semiconductor structure 1000 in FIG. 10 with the semiconductor structure 800 in FIG. 8, the semiconductor structure 1000 includes a first polycrystalline silicon layer 1041 and a second polycrystalline silicon layer 1043. The oxidation protection layer 142 of the semiconductor structure 800 is It is replaced by the second polycrystalline silicon layer 1043.

According to an embodiment of the present invention, since the oxidation protection layer 142 of the semiconductor structure 800 of FIG. 8 is replaced by the second polycrystalline silicon layer 1043, the first P-type diffusion layer 110, the second P-type diffusion layer 120, and the first Above the N-type diffusion layer 130 is a polycrystalline silicon layer, so the manufacturing cost of the mask for the oxidation protection layer can be saved.

According to an embodiment of the present invention, the first polycrystalline silicon layer 1041 is in a floating state. According to another embodiment of the present invention, the first polycrystalline silicon layer 1041 may also be coupled to the first electrode 151. According to an embodiment of the present invention, the second polycrystalline silicon layer 1043 is in a floating state. According to another embodiment of the present invention, the second polycrystalline silicon layer 1043 may also be coupled to the second electrode 152.

The invention relates to a semiconductor structure of an electrostatic protection device, which is used to effectively improve the protection capability of a machine discharge mode of electrostatic protection. According to many embodiments of the present invention, the protection capability of the machine discharge mode can be up to 550V.

Although the embodiments and advantages of this disclosure have been disclosed as above, it should be understood that anyone with ordinary knowledge in the technical field can make changes, substitutions, and decorations without departing from the spirit and scope of this disclosure. In addition, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, devices, methods, and steps in the specific embodiments described in the description. Any person with ordinary knowledge in the technical field can implement some implementations from this disclosure. In the disclosure of the examples, understand the current or future development of processes, machines, manufacturing, material composition, devices, methods and steps. As long as the same functions can be implemented or the same results can be obtained in the embodiments described herein, they can be based on This disclosure uses some embodiments. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, devices, methods and steps. In addition, the scope of each patent application constitutes a Other embodiments, and the protection scope of this disclosure also includes the scope of each patent application and the combination of the embodiments.

Claims (15)

A semiconductor structure includes: a first P-type well; a first P-type diffusion region disposed in the first P-type well and coupled to a first electrode; a first N-type well and the foregoing The first P-type wells are adjacent to each other; a first N-type diffusion region is disposed in the first N-type well; a second P-type diffusion region is disposed in the first P-type diffusion region and the first N-type diffusion region; Between the diffusion regions and within the first N-type well, wherein the second P-type diffusion region and the first N-type diffusion region are coupled to a second electrode; and a first polycrystalline silicon layer Is disposed above the first P-type diffusion region. The semiconductor structure described in item 1 of the patent application scope further includes: an epitaxial layer; a second P-type well disposed on the epitaxial layer, wherein the first P-type well system is disposed on the second Within a P-type well; and a second N-type well disposed above the epitaxial layer and adjacent to the second P-type well, wherein the first N-type well system is disposed in the second N-type well Wherein, the epitaxial layer is N-type. The semiconductor structure according to item 1 of the scope of patent application, wherein the first polycrystalline silicon layer is coupled to the first electrode. The semiconductor structure according to item 1 of the scope of patent application, wherein the first polycrystalline silicon layer is floating. The semiconductor structure according to item 1 of the patent application scope further includes: a first oxidation protection layer formed on the second P-type diffusion region and adjacent to the first polycrystalline silicon layer, wherein the oxidation protection The layer has a first distance from the first polycrystalline silicon layer; and a shallow trench isolation region is formed between the first P-type diffusion region and the second P-type diffusion region. The semiconductor structure according to item 5 of the scope of the patent application, wherein the first P-type diffusion region and the shallow trench isolation region have a second pitch, and the second type diffusion region is directly coupled to the shallow trench isolation region. The semiconductor structure according to item 1 of the scope of patent application, wherein the first polycrystalline silicon layer is disposed on the first P-type diffusion region and the second P-type diffusion region. The semiconductor structure according to item 1 of the patent application scope further includes: a second polycrystalline silicon layer disposed on the second P-type diffusion region and the first N-type diffusion region, wherein the second polycrystal The silicon layer is floating. An electrostatic protection device for discharging an electrostatic charge of a first electrode to a second electrode, comprising: a first P-type well; and a first P-type diffusion region disposed in the first P-type well, And is coupled to the first electrode; a first N-type well adjacent to the first P-type well; a first N-type diffusion region disposed within the first N-type well; a second P-type A diffusion region is disposed between the first P-type diffusion region and the first N-type diffusion region, and is disposed within the first N-type well, wherein the second P-type diffusion region and the first N-type diffusion region. The region is coupled to the second electrode; and a first polycrystalline silicon layer is disposed on the first P-type diffusion region. The electrostatic protection device according to item 9 of the scope of the patent application, wherein the first polycrystalline silicon layer is coupled to the first electrode. The electrostatic protection device according to item 9 of the scope of the patent application, wherein the first polycrystalline silicon layer is floating. The electrostatic protection device according to item 9 of the scope of the patent application, further comprising: a first oxidation protection layer formed on the second P-type diffusion region and adjacent to the first polycrystalline silicon layer, wherein the oxidation The protective layer and the first polycrystalline silicon layer have a first distance; and a shallow trench isolation region is formed between the first P-type diffusion region and the second P-type diffusion region. The electrostatic protection device according to item 12 of the scope of patent application, wherein the first P-type diffusion region and the shallow trench isolation region have a second distance, and the second type diffusion region is directly coupled to the shallow trench isolation region. . The electrostatic protection device according to item 9 of the scope of the patent application, wherein the first polycrystalline silicon layer is disposed on the first P-type diffusion region and the second P-type diffusion region. The electrostatic protection device according to item 9 of the scope of patent application, further comprising: a second polycrystalline silicon layer disposed on the second P-type diffusion region and the first N-type diffusion region, wherein the second The crystalline silicon layer is floating.