TWI831638B - Electrostatic discharge protection device - Google Patents
Electrostatic discharge protection device Download PDFInfo
- Publication number
- TWI831638B TWI831638B TW112108698A TW112108698A TWI831638B TW I831638 B TWI831638 B TW I831638B TW 112108698 A TW112108698 A TW 112108698A TW 112108698 A TW112108698 A TW 112108698A TW I831638 B TWI831638 B TW I831638B
- Authority
- TW
- Taiwan
- Prior art keywords
- strip
- electrostatic discharge
- protection device
- discharge protection
- well region
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000002513 implantation Methods 0.000 description 40
- 238000000034 method Methods 0.000 description 38
- 230000015556 catabolic process Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- 230000000873 masking effect Effects 0.000 description 9
- 239000002019 doping agent Substances 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 238000004380 ashing Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052787 antimony Inorganic materials 0.000 description 4
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229910000807 Ga alloy Inorganic materials 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- -1 arsenic aluminum indium Chemical compound 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910000967 As alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000846 In alloy Inorganic materials 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- 229910001096 P alloy Inorganic materials 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- CTNCAPKYOBYQCX-UHFFFAOYSA-N [P].[As] Chemical compound [P].[As] CTNCAPKYOBYQCX-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
本發明是有關於一種半導體裝置,且特別關於一種靜電放電(Electrostatic Discharge, ESD)保護半導體裝置。The present invention relates to a semiconductor device, and in particular to an electrostatic discharge (Electrostatic Discharge, ESD) protection semiconductor device.
靜電放電是指在某一絕緣介質的兩面分別出現正電荷和負電荷,並且逐漸累積時,這時加於該絕緣介質上的電壓也會同時增加,當該電壓高於一定程度(崩潰電壓)後,這時絕緣介質會發生電擊穿,繼而使得一部分絕緣介質變為導體,使電流能夠通過。在電流通過絕緣介質後,絕緣介質兩面的正負電荷便會消失,加於該絕緣介質的電壓也會回復到零,因此靜電放電只會在一段短時間之內出現。Electrostatic discharge refers to the occurrence of positive and negative charges on both sides of an insulating medium, and when they gradually accumulate, the voltage applied to the insulating medium will also increase at the same time. When the voltage is higher than a certain level (collapse voltage) , at this time, the insulating medium will undergo electrical breakdown, which in turn causes part of the insulating medium to become a conductor, allowing current to pass through. After the current passes through the insulating medium, the positive and negative charges on both sides of the insulating medium will disappear, and the voltage applied to the insulating medium will return to zero, so electrostatic discharge will only occur within a short period of time.
然而靜電通常瞬間電壓非常高,所以會對電子元件或積體電路系統造成過度電應力(EOS: Electrical Over Stress)破壞,而這種損傷是毀滅性和永久性的,會造成電路直接燒毀。為了避免積體電路由於靜電放電而造成損害,在積體電路內皆有製作靜電放電防護電路。靜電放電防護電路是積體電路上專門用來做靜電放電防護之用的特殊電路,此靜電放電防護電路提供了靜電放電的電流路徑,以免靜電放電時電流流入IC內部電路而造成損傷。However, static electricity usually has a very high instantaneous voltage, which can cause excessive electrical stress (EOS: Electrical Over Stress) damage to electronic components or integrated circuit systems. This damage is devastating and permanent, causing the circuit to be directly burned. In order to prevent damage to integrated circuits due to electrostatic discharge, electrostatic discharge protection circuits are built into integrated circuits. The electrostatic discharge protection circuit is a special circuit on the integrated circuit specially used for electrostatic discharge protection. This electrostatic discharge protection circuit provides a current path for electrostatic discharge to prevent current from flowing into the internal circuit of the IC and causing damage during electrostatic discharge.
如何製造一個有效率的靜電放電保護裝置/元件來保護積體電路,是業界一直不斷探討與研究的問題。How to create an efficient electrostatic discharge protection device/component to protect integrated circuits is a problem that the industry has been constantly discussing and researching.
本案提供一種靜電放電保護裝置,包括:基底,具有第一導電型態;第一井區,設置於基底中,且具有與第一導電型態相反的第二導電型態;第二井區,設置於基底中,具有第二導電型態,且第一井區位於第二井區中;基極,設置於第二井區中,且具有第二導電型態;射極,設置於第井區中,且具有第一導電型態;集極,設置於基極及射極之間,且具有第一導電型態;第一摻雜區,設置於第二井區中且位於射極遠離集極的一側,且具有第二導電型態;以及複數個條狀摻雜區,設置於第二井區中且位於基極與射極之間。This case provides an electrostatic discharge protection device, which includes: a substrate with a first conductivity type; a first well region, which is provided in the substrate and has a second conductivity type that is opposite to the first conductivity type; a second well region, is disposed in the substrate and has a second conductivity type, and the first well region is located in the second well region; the base is disposed in the second well region and has the second conductivity type; the emitter is disposed in the first well region region and has a first conductivity type; a collector is disposed between the base and the emitter and has a first conductivity type; a first doping region is disposed in the second well region and is located away from the emitter One side of the collector has a second conductivity type; and a plurality of strip-shaped doped regions are disposed in the second well region and located between the base and the emitter.
以下內容提供了很多不同的實施例或範例,用於實施本發明實施例的不同部件。組件和配置的具體範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例來說,敘述中若提及第一部件形成於第二部件之上,可能包含第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不直接接觸的實施例。另外,本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的,其本身並非代表所討論各種實施例及/或配置之間有特定的關係。The following content provides many different embodiments or examples for implementing different components of embodiments of the invention. Specific examples of components and configurations are described below to simplify embodiments of the invention. Of course, these are only examples and are not intended to limit the embodiments of the present invention. For example, if the description mentions that a first component is formed on a second component, it may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. , an embodiment in which the first and second components are not in direct contact. In addition, embodiments of the present invention may repeat reference symbols and/or letters in many examples. These repetitions are for the purposes of simplicity and clarity and do not in themselves imply a specific relationship between the various embodiments and/or configurations discussed.
以下描述實施例的一些變化。在不同圖式和說明的實施例中,相似的元件符號被用來標示相似的元件。可以理解的是,在方法的前、中、後可以提供額外的步驟,且一些所敘述的步驟可在所述方法的其他實施例被取代或刪除。Some variations of the embodiments are described below. Similar reference numbers are used to identify similar elements in the various drawings and illustrated embodiments. It will be appreciated that additional steps may be provided before, during, and after the method, and some of the recited steps may be replaced or deleted in other embodiments of the method.
此外,其中可能用到與空間相對用詞,例如「在......下方」、「下方」、「較低的」、「重疊」、「上方」等類似用詞,是為了便於描述圖式中一個(些)部件或特徵與另一個(些)部件或特徵之間的關係。空間相對用詞用以包括使用中或操作中的裝置之不同方位,以及圖式中所描述的方位。當裝置被轉向不同方位時(旋轉90度或其他方位),其中所使用的空間相對形容詞也將依轉向後的方位來解釋。In addition, words relative to space may be used, such as "below", "below", "lower", "overlap", "above" and other similar words, for the convenience of description. The relationship between one component(s) or feature(s) and another(s) component(s) or feature(s) in the diagram. Spatially relative terms are used to encompass different orientations of equipment in use or operation and the orientation depicted in the drawings. When the device is turned at a different orientation (rotated 90 degrees or at any other orientation), the spatially relative adjectives used therein will also be interpreted in accordance with the rotated orientation.
此處所使用的用語「約」、「近似」等類似用語描述數字或數字範圍時,該用語意欲涵蓋的數值是在合理範圍內包含所描述的數字,例如在所描述的數字之+/- 10%之內,或本發明所屬技術領域中具有通常知識者理解的其他數值。例如,用語「約5 nm」涵蓋從4.5nm至5.5nm的尺寸範圍。When the terms "about", "approximately" and similar terms are used herein to describe a number or range of numbers, the term is intended to cover a value that includes the number described within a reasonable range, for example, within +/- 10 of the number described. Within %, or other numerical values understood by those with ordinary knowledge in the technical field to which the present invention belongs. For example, the term "about 5 nm" covers the size range from 4.5nm to 5.5nm.
本案提供一種可用於靜電放電防護的半導體裝置,其崩潰電壓較低且容易調控,能夠適用於不同的電路中。This case provides a semiconductor device that can be used for electrostatic discharge protection. Its breakdown voltage is low and easy to control, and can be applied to different circuits.
以下參照圖示,對本案的靜電放電保護裝置及其形成方法進行說明,在這些實施例中所述的多個階段之前、期間以及∕或之後,可提供額外的步驟。一些所述階段在不同實施例中可被替換或刪去。靜電放電保護裝置結構可增加額外部件。一些所述部件在不同實施例中可被替換或刪去。儘管所討論的一些實施例以特定順序的步驟執行,這些步驟仍可以另一合乎邏輯的順序執行。此外,除非另有說明,否則「第一」、「第二」或其類似者不意欲隱含一時間態樣、一空間態樣、一順序等等。確切言之,此等術語僅用作構件、元件、項目等等之識別符、名稱等等。例如,一第一元件及一第二元件一般對應於元件A及元件B或兩個不同或兩個相同元件或相同元件。The electrostatic discharge protection device and its formation method of the present invention will be described below with reference to the figures. Additional steps may be provided before, during and/or after the multiple stages described in these embodiments. Some of the described stages may be replaced or deleted in different embodiments. Additional components can be added to the structure of the electrostatic discharge protection device. Some of the described components may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, the steps may be performed in another logical order. Furthermore, unless otherwise stated, "first", "second" or the like are not intended to imply a temporal aspect, a spatial aspect, a sequence, etc. Rather, these terms are used only as identifiers, names, etc. of components, components, items, etc. For example, a first element and a second element generally correspond to element A and element B or two different elements or two identical elements or the same element.
首先,如第1圖所示,提供形成有隔離結構400的基底100。隔離結構400所定義的區域將於後續形成靜電放電(Electrostatic Discharge, ESD)保護裝置10的元件,靜電放電保護裝置10用於在靜電放電事件發生期間保護基底100上的其他半導體裝置。在一些實施例中,基底100具有第一導電型態,例如P型導電型態,且摻雜有例如硼(B)、鎵(Ga)、鋁(Al)、銦(In)、或前述之組合。在一些實施例中,基底100可為一半導體基板,例如矽基板。此外,上述半導體基板亦可為元素半導體,包括鍺(germanium);化合物半導體,包括碳化矽(silicon carbide)、砷化鎵(gallium arsenide)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)及/或銻化銦(indium antimonide);合金半導體,包括矽鍺合金(SiGe)、磷砷鎵合金(GaAsP)、砷鋁銦合金(AlInAs)、砷鋁鎵合金(AlGaAs)、砷銦鎵合金(GaInAs)、磷銦鎵合金(GaInP)及/或磷砷銦鎵合金(GaInAsP)或上述材料之組合。此外,基底100也可以是絕緣層上覆半導體(semiconductor on insulator,SOI)。基底100的摻雜濃度可為例如1×10
15~1×10
17atoms/cm
3。
First, as shown in FIG. 1 , a
根據一些實施例,除了靜電放電保護裝置10外,在基底100上還形成其他的半導體裝置(未繪示),例如主動元件、被動元件(例如電阻或電容)、或前述之組合。在一些實施例中,主動元件包含電晶體、金屬氧化物半導體場效電晶體(metal oxide semiconductor field effect transistor,MOSFET)、金屬絕緣體半導體場效電晶體(metal insulator semiconductor FET,MISFET)、接面場效電晶體(junction field effect transistor,JFET)、絕緣閘雙極電晶體(insulated gate bipolar transistor,IGBT)、或前述之組合。According to some embodiments, in addition to the electrostatic
根據一些實施例,隔離結構400自基底100的上表面100s向下延伸。在一些實施例中,隔離結構400可為場氧化物(field oxide,FOX)、局部矽氧化物(local oxide of silicon,LOCOS)、或淺溝槽隔離(shallow trench isolation,STI)結構。According to some embodiments, the
接著,同樣參照第1圖,在基底100的上表面100s上形成遮蔽層210,並執行佈植步驟91,以於基底100之中形成第一井區120。第一井區120具有與基底100相反的第二導電型態,在一些實施例中,第一井區120具有N型導電型態。遮蔽層210的材質可為光阻、氧化矽、氮化矽或其他適合的材料。可利用例如旋轉塗佈(spin-on)技術、化學氣相沉積或任何合適的沉積技術形成遮蔽層,且利用可接受的光學微影技術及/或蝕刻製程將其圖案化,以形成遮蔽層210。佈植步驟91以遮蔽層210作為佈植罩幕。在一些實施例中,佈植步驟91可使用磷(P)、砷(As)、銻(Sb)離子、或前述之組合等作為摻質,且佈植的濃度為約1×10
15atoms/cm
3至約1×10
17atoms/cm
3,例如約3×10
15atoms/cm
3、約6×10
15atoms/cm
3、約9×10
15atoms/cm
3、約1×10
16atoms/cm
3、約3×10
16atoms/cm
3、約6×10
16atoms/cm
3、約9×10
16atoms/cm
3等。佈植的能量為約50KeV至2000KeV,例如60KeV、350KeV、800KeV、1800KeV等。
Next, referring also to FIG. 1 , a
接著參照第2圖,利用遮蔽層220作為佈植罩幕,在基底100中形成較第一井區120更深且寬的第二井區130,而使第一井區120埋設於第二井區130中。第二井區130與基底100具有相反的第二導電型態,根據一些實施例,第二井區130具有N型導電型態。本發明藉由在第二井區130內設置複數個條狀摻雜區來調整靜電放電保護裝置的電場,以使得靜電放電保護裝置的設計更加靈活。在本發明中,條狀摻雜區可以具有各種實施態樣,以下分別參考第2-7圖、第9-10圖、第11-13圖,說明本案不同態樣的複數個條狀摻雜區。Next, referring to Figure 2, the
首先,參照第2-7圖,說明本案的第一種實施態樣,在此實施態樣中,第二井區130內具有兩種相鄰設置但具有不同導電型態、不同深度的條狀摻雜區。First, with reference to Figures 2-7, the first implementation aspect of the present case is described. In this implementation form, the
如第2圖所示,在形成遮蔽層220的同時,形成複數個第一條狀區221,並在執行形成第二井區130的佈植步驟92時,利用第一條狀區221做為佈植罩幕,使得第一條狀區221正下方的區域不被佈植步驟92所摻雜,這使得在形成第二井區130的同時,在第二井區130之內、第一條狀區221的正下方形成了複數個第一條狀摻雜區141。遮蔽層220的材質及形成方法可相同或類似於遮蔽層210,在此不與贅述。在一些實施例中,佈植步驟92可使用磷、砷、銻等作為摻質,且佈植的濃度為約1×10
15atoms/cm
3至約1×10
17atoms/cm
3,例如約3×10
15atoms/cm
3、約6×10
15atoms/cm
3、約9×10
15atoms/cm
3、約1×10
16atoms/cm
3、約3×10
16atoms/cm
3、約6×10
16atoms/cm
3、約9×10
16atoms/cm
3等。佈植的能量為約50KeV至2000KeV,例如60KeV、350KeV、800KeV、1800KeV等。
As shown in FIG. 2 , while forming the
複數個第一條狀摻雜區141將位於後續形成的基極170與集極160之間(詳見第7圖)。雖然離子不會直接佈植到複數個第一條狀區221的正下方,但經過佈植後的退火,鄰近的摻質會擴散,因此使複數個第一條狀摻雜區141與第二井區130相同,具有第二導電型態,但其摻雜濃度低於第二井區130。複數個第一條狀摻雜區141之間的間距d1為0.1-1微米,例如0.2微米、0.4微米、0.6微米、0.8微米。複數個第一條狀摻雜區141的摻雜濃度約為50KeV至2000KeV,例如60KeV、350KeV、800KeV、1800KeV等。佈植後,利用如可接受的灰化(ashing)製程及/或蝕刻製程移除遮蔽層。A plurality of first strip-shaped
接著,如第3圖所示,形成具有複數個第二條狀區231的遮蔽層230,並執行佈植步驟93,以在複數個第一條狀摻雜區141與第一井區120之間,形成複數個第二條狀摻雜區142。與前述佈植步驟92不同之處在於,佈植步驟93是在遮蔽層的條狀區231之間“間隙”的正下方形成複數個第二條狀摻雜區142,而佈植步驟92則是在遮蔽層的條狀區221的正下方形成複數個第一條狀摻雜區141。複數個第一條狀摻雜區141及複數個第二條狀摻雜區142構成靜電放電保護裝置10的複數個條狀摻雜區140a。複數個第二條狀摻雜區142具有第一導電型態,在一些實施例中,複數個第二條狀摻雜區142具有P型導電型態。在一些實施例中,第一條狀摻雜區141的深度小於第二條狀摻雜區142的深度。複數個第二條狀摻雜區142之間的間距d2為0.1-1微米,例如0.2微米、0.4微米、0.6微米、0.8微米。複數個第二條狀摻雜區142與複數個第一條狀摻雜區141之間的間距d3為0.1-1微米,例如0.2微米、0.4微米、0.6微米、0.8微米。遮蔽層230的材質及形成方法可相同或類似於遮蔽層210,在此不與贅述。佈植步驟93可使用硼、鋁、銦、鎵、或前述之組合等作為摻質,且佈植的濃度為約1×10
15atoms/cm
3至約1×10
17atoms/cm
3,例如約3×10
15atoms/cm
3、約6×10
15atoms/cm
3、約9×10
15atoms/cm
3、約1×10
16atoms/cm
3、約3×10
16atoms/cm
3、約6×10
16atoms/cm
3、約9×10
16atoms/cm
3等,佈植的能量為約50KeV至2000KeV,例如60KeV、350KeV、800KeV、1800KeV等。佈植後,利用如可接受的灰化製程及/或蝕刻製程移除遮蔽層。應注意的是,在不同實施例中,多條狀的複數個第二條狀摻雜區142可由塊狀的摻雜區取代(詳見第9圖)。
Next, as shown in FIG. 3 , a
接著,如第4圖所示,形成圖案化的遮蔽層240,並執行佈植步驟94,以形成射極150及集極160。射極150形成於第一井區120的上部,集極160形成於複數個第二條狀摻雜區142的上部。射極150及集極160的上表面與基底100的上表面100s齊平,因此後續形成的接觸件可與射極150及集極160的上表面接觸。射極150及集極160具有第一導電型態,在一些實施例中,射極150及集極160具有P型導電型態。遮蔽層240的材質及形成方法可相同或類似於遮蔽層210,在此不與贅述。在一些實施例中,佈植步驟94可使用硼、鋁、銦、鎵、或前述之組合等作為摻質,且佈植的濃度為約1×10
16atoms/cm
3至約1×10
18atoms/cm
3,例如約3×10
16atoms/cm
3、約6×10
16atoms/cm
3、約9×10
16atoms/cm
3、約1×10
17atoms/cm
3、約3×10
17atoms/cm
3、約6×10
17atoms/cm
3、約9×10
17atoms/cm
3等,佈植的能量為約50KeV至2000KeV,例如60KeV、350KeV、800KeV、1800KeV等。在另一些實施例中,射極150及集極160亦可藉由不同的遮罩而分別形成,且可具有相同或不同的摻雜濃度。佈植後,利用如可接受的灰化製程及/或蝕刻製程移除光遮蔽層。
Next, as shown in FIG. 4 , a
接著,如第5圖所示,形成圖案化的遮蔽層250,並執行佈植步驟95,以在第二井區130中形成基極170及第一摻雜區180。基極170及射極150位於及集極160外側(即,集極160位於基極170與射極150之間),且第一摻雜區180位於射極150遠離該集極160的一側。基極170及第一摻雜區180的上表面與基底100的上表面100s齊平,因此後續形成的接觸件可與基極170及第一摻雜區180的上表面接觸。基極170及第一摻雜區180具有第二導電型態,在一些實施例中,基極170及第一摻雜區180具有N型導電型態。遮蔽層250的材質及形成方法可相同或類似於遮蔽層210,在此不與贅述。佈植步驟95可使用磷、砷、銻、或前述之組合等作為摻質,且佈植的濃度為約約1×10
16atoms/cm
3至約1×10
18,例如約3×10
16atoms/cm
3、約6×10
16atoms/cm
3、約9×10
16atoms/cm
3、約1×10
17atoms/cm
3、約3×10
17atoms/cm
3、約6×10
17atoms/cm
3、約9×10
17atoms/cm
3等,佈植的能量為約50KeV至2000KeV,例如60KeV、350KeV、800KeV、1800KeV等(請申請人補充)。在另一些實施例中,基極170及第一摻雜區180可藉由不同的遮罩而分別形成,且可具有相同或不同的摻雜濃度。佈植後,利用如可接受的灰化製程及/或蝕刻製程移除遮蔽層。
Next, as shown in FIG. 5 , a
接著,如第6圖所示,在靜電放電保護裝置10的上表面100s上形成第一介電層410,並在第一介電層410中形成接觸件151、161、171及181。在一實施例中,第一介電層410包括例如氮化矽(SiNx)、氧化物(例如,氧化矽(SiOx)及/或其他氧化物材料)、及/或其他類型的介電材料,並藉由化學氣相沉積(CVD)技術,例如低壓化學氣相沉積(LPCVD)、電壓輔助化學氣相沉積(PECVD)、可流動化學氣相沉積(FCVD)、或其他合適的沉積技術,沉積第一介電層410於靜電放電保護裝置10的上表面100s上。之後,可視需要藉由化學機械研磨(CMP)製程或回蝕刻,將第一介電層410平坦化使其具有平坦的上表面。接著,以微影與蝕刻製程圖案化第一介電層410,以形成分別對應於射極150、集極160、基極170及第一摻雜區180的開口。微影製程可包括形成光阻層於第一介電層410上方,將該光阻曝光於一圖案,進行曝光後烘烤製程,並對光阻進行顯影。而後,利用蝕刻將光阻圖案轉移至第一介電層410中。蝕刻製程可包括乾式蝕刻、濕式蝕刻、以及/或其他合適的製程。去除光阻圖案後,藉由一或多道製程,例如濺鍍、化學氣相沉積、以及電鍍或無電鍍,在圖案化的第一介電層410上沉積金屬(例如銅(Cu)、鈷(Co)、釕(Ru)、鋁(Al)、鎳(Ni)、金(Au)、銀(Ag)、錳(Mn)、錫(Sn)及/或上述金屬的合金)導體層。而後,進行化學機械研磨製程或回蝕刻以移除開口以外多餘的金屬材料,而形成分別對應射極150、集極160、基極170及第一摻雜區180的接觸件151、161、171及181。Next, as shown in FIG. 6 , a first
接著,如第7圖所示,在第一介電層410上形成第二介電層420,並在第二介電層420中形成第一場板310、第二場板320及內連線162。第二介電層420的材料及形成方法可參照第一介電層410,在此不再贅述。第一場板310、第二場板320及內連線162的材料及形成方法可參照接觸件151、161、171及181,在此不再贅述。第一場板310、第二場板320及內連線162的材料可以彼此相同或不同,且可與接觸件151、161、171及181相同或不同。第一場板310藉由接觸件171與基極170互連,第二場板320藉由接觸件151及181與射極150及第一摻雜區180互連,而內連線162藉由接觸件161與集極160互連。第一場板310於該基底100的上表面100s的正投影與複數個第二條狀摻雜區142至少部分重疊。在一些實施例中,第一場板310自基極170延伸超過複數個第二條狀摻雜區142靠近基極170的邊緣S1,例如超過邊緣S1至少0.5微米,例如0.7-1.9微米、0.9-1.7微米、1.0-1.5微米、1.2-1.3微米。在一些實施例中,第一場板310及第二場板320耦接至一電壓源,例如3V-30V、5V-25V、8V-20V、10-15V、或12-14V等的工作電壓,且內連線162接地。若第一場板在310未延伸超過邊緣S1,則不能有效的降低靜電放電保護裝置10的崩潰電壓。Next, as shown in FIG. 7 , a
靜電放電保護裝置10藉由複數個條狀摻雜區140a,可改變其電場分布,使其崩潰電壓(Breakdown voltage)下降,以作為更有效的靜電放電(Electrostatic Discharge, ESD)裝置。另外,由於複數個第二條狀摻雜區142具有第一導電型態,第二井區130具有與第一導電型態相反的第二導電型態,因此,複數個第二條狀摻雜區142的邊緣S1處具有一PN接面(p-n junction),藉由對PN接面上方的第一場板310施加高壓,亦可調整靜電放電保護裝置10的崩潰電壓。The electrostatic
第8圖為第7圖的上視圖,為了清楚起見,靜電放電保護裝置10中的一些元件在第8圖中省略。如第8圖所示,第一場板310、第二場板320的寬度明顯大於基極170、集極160、射極150、第一摻雜區180。相對於此,內連線162的寬度大致與集極160相同,即第一場板310與第二場板320的寬度明顯大於內連線162的寬度。在一些實施例中,第一場板310及第二場板320藉由內連線350耦接。Figure 8 is a top view of Figure 7. Some components in the electrostatic
接著,參照第9-10圖,說明本案的第二種實施態樣。在此實施例中,靜電放電保護裝置20的第二井區130內的複數個條狀摻雜區140b不包括位於集極160正下方的部分(見第10圖)。Next, the second implementation aspect of this case will be described with reference to Figures 9-10. In this embodiment, the plurality of strip-shaped
第9圖接續第2圖,且複數個條狀摻雜區140b的形成方法可參照靜電放電保護裝置10的複數個第一條狀摻雜區141,在此不再贅述,複數個條狀摻雜區140b之間的間距d1’為0.1-1微米,例如0.2微米、0.4微米、0.6微米、0.8微米,且d1與d1’可相同或不同。在形成複數個條狀摻雜區140b之後,在靜電放電保護裝置20的上表面100s上形成遮蔽層230’,並執行佈植步驟93,以在條狀摻雜區140b與第一井區120之間,形成第三井區143。第三井區143與複數個第二條狀摻雜區142同樣,具有第一導電型態,但與其不同的是,第三井區143為一連續塊狀的(bulk)摻雜區,而非多條狀、不連續的摻雜區。第三井區143與複數個條狀摻雜區140b之間的間距d3’可為0.1-1微米,例如0.2微米、0.4微米、0.6微米、0.8微米,且d3與d3’可相同或不同。遮蔽層230’的材質及形成方法可相同或類似於遮蔽層210,在此不與贅述。佈植步驟93’以遮蔽層210作為佈植罩幕。佈植步驟93’可使用硼、鋁、銦、鎵等作為摻質,且佈植的濃度為約1×10
15atoms/cm
3至約1×10
17atoms/cm
3,例如約3×10
15atoms/cm
3、約6×10
15atoms/cm
3、約9×10
15atoms/cm
3、約1×10
16atoms/cm
3、約3×10
16atoms/cm
3、約6×10
16atoms/cm
3、約9×10
16atoms/cm
3等,佈植的能量為約50KeV至2000KeV,例如60KeV、350KeV、800KeV、1800KeV等(請申請人補充)。佈植後,利用如可接受的灰化製程及/或蝕刻製程移除遮蔽層。
Figure 9 continues Figure 2, and the formation method of the plurality of strip-shaped
接著,可照第4圖至第7圖的製程,接續靜電放電保護裝置20的製造。靜電放電保護裝置20的結構如第10圖所示,第一場板於該基底100的上表面100s的正投影與第三井區143至少部分重疊。在一些實施例中,第一場板310自基極170延伸超過第三井區143靠近基極170的邊緣S2,例如超過邊緣S2至少0.5微米,例如0.7-1.9微米、0.9-1.7微米、1.0-1.5微米、1.2-1.3微米。Then, the manufacturing of the electrostatic
第10圖中的靜電放電保護裝置20與第7圖中靜電放電保護裝置10的差別在於:靜電放電保護裝置10的複數個條狀摻雜區140a包括位於基極170與集極160之間的複數個第一條狀摻雜區141、及位於集極160正下方的複數個第二條狀摻雜區142(見第7圖),而靜電放電保護裝置20的複數個條狀摻雜區140b不包括位於集極160正下方的部分,且集極160正下方為第三井區143。此外,靜電放電保護裝置20與靜電放電保護裝置10同樣,具有如第8圖所示的俯視結構。藉由改變複數個條狀摻雜區的摻雜濃度、結構等,可適當調整靜電放電保護裝置的電場分佈,以控制靜電放電保護裝置的崩潰電壓。此外,第三井區143的邊緣S2處具有一PN接面(p-n junction),藉由對PN接面上方的第一場板310施加高壓,亦可調整靜電放電保護裝置20的崩潰電壓。The difference between the electrostatic
接著,參照第11-13圖,說明本案的第三種實施態樣。在此實施例中,靜電放電保護裝置30的第二井區130內的複數個條狀摻雜區140c不包括位於基極170與集極160之間的部分(見第13圖)。Next, the third implementation aspect of this case will be described with reference to Figures 11-13. In this embodiment, the plurality of strip-shaped
第11圖接續第1圖,在形成第一井區120之後,形成遮蔽層220’,並執行佈植步驟92’,以形成第二井區130。遮蔽層220’的材質及形成方法可相同或類似於遮蔽層210,在此不與贅述。佈植步驟92’以遮蔽層220’作為佈植罩幕。在一些實施例中,佈植步驟92’可使用磷、砷、銻等作為摻質,且佈植的濃度為約1×10
15atoms/cm
3至約1×10
17atoms/cm
3,例如約3×10
15atoms/cm
3、約6×10
15atoms/cm
3、約9×10
15atoms/cm
3、約1×10
16atoms/cm
3、約3×10
16atoms/cm
3、約6×10
16atoms/cm
3、約9×10
16atoms/cm
3等。佈植的能量為約50KeV至2000KeV,例如60KeV、350KeV、800KeV、1800KeV等(請申請人補充)。與第2圖中的複數個第一條狀遮蔽層220不同的是,遮蔽層220’僅具有對應於第二井區的開口,因此,在形成第二井區130的同時不會在其內形成複數個條狀摻雜區。佈植後,利用如可接受的灰化製程及/或蝕刻製程移除遮蔽層。
Figure 11 is a continuation of Figure 1. After forming the
接著,如第12圖所示,在靜電放電保護裝置30的上表面100s上形成具有複數個第二條狀區的遮蔽層230,並執行佈植步驟93,以在第二井區130中形成複數個條狀摻雜區140c。複數個條狀摻雜區140c的形成方法可參考靜電放電保護裝置10的複數個第二條狀摻雜區142的形成方法,在此不再贅述。複數個條狀摻雜區140c之間的間距d2’為0.1-1微米,例如0.2微米、0.4微米、0.6微米、0.8微米,且d2與d2’可相同或不同。Next, as shown in FIG. 12 , a
接著,可照第4圖至第7圖的製程,接續靜電放電保護裝置30的製造。靜電放電保護裝置30具有如第13圖的結構,第一場板於該基底100的上表面100s的正投影與複數個條狀摻雜區140c至少部分重疊。在一些實施例中,第一場板310自基極170延伸超過複數個條狀摻雜區140c靠近基極170的邊緣S3,例如超過邊緣S3至少0.5微米,例如0.7-1.9微米、0.9-1.7微米、1.0-1.5微米、1.2-1.3微米。Then, the manufacturing of the electrostatic
第13圖中的靜電放電保護裝置30與第7圖中靜電放電保護裝置10的差別在於:靜電放電保護裝置10的第二井區130內的複數個條狀摻雜區140a包括位於基極170與集極160之間的複數個第一條狀摻雜區141、及位於集極160下方的複數個第二條狀摻雜區142(見第7圖),而靜電放電保護裝置30的第二井區130內的複數個條狀摻雜區140c不包括位於基極170與集極160之間的部分。此外,靜電放電保護裝置30與靜電放電保護裝置10同樣,具有如第8圖所示的俯視結構。藉由改變複數個條狀摻雜區的摻雜濃度、結構等,可適當調整靜電放電保護裝置的電場分佈,以控制靜電放電保護裝置的崩潰電壓。此外,複數個條狀摻雜區140c的邊緣S3處具有一PN接面(p-n junction),藉由對PN接面上方的第一場板310施加高壓,亦可調整靜電放電保護裝置30的崩潰電壓。The difference between the electrostatic
第15圖繪示本發明實施例與比較例之靜電放電保護裝置所進行的電性測試結果,其中,實施例為具有如第7圖所示的結構;比較例具有如第14圖所示的結構,除了第二井區130中以位於集極160正下方的第三井區143取代複數條狀摻雜區140a,且以互連線172取代場板310之外,其結構與實驗例相同。藉由射極電流(I
emitter)與射極電壓(V
emitter)兩者之間的變化關係,可判斷靜電放電保護裝置的崩潰電壓。在耦接射極與基極,並將集極接地的情況下,對實施例及比較例的靜電放電保護裝置施加不同的射極電壓(正偏壓)(從0至40V)。由測試結果可看出,比較例的崩潰電壓為約40V,而實施例的崩潰電壓為約35V,明顯低於比較例。因此,實施例的靜電放電保護裝置能夠更靈敏、更快速的將靜電放電產生的電流流引向地,以避免電路由於靜電放電而造成損害。
Figure 15 shows the electrical test results of the electrostatic discharge protection device according to the embodiment and the comparative example of the present invention. The embodiment has the structure shown in Figure 7; the comparative example has the structure shown in Figure 14 The structure is the same as the experimental example except that the plurality of strip-shaped
綜上所述,本發明可藉由現有的靜電放電保護裝置製程,不須使用額外的遮罩即可實現本案的靜電放電保護裝置,且可使用現有的佈植層(implant layer),從而降低裝置的製造成本。此外,藉由調整場板及第二井區中的複數個條狀摻雜區可獲得期望的崩潰電壓,使靜電放電保護裝置的設計範圍更加靈活。因此,本發明具有使用範圍廣、製造簡易等優點。To sum up, the present invention can realize the electrostatic discharge protection device of this case by using the existing electrostatic discharge protection device manufacturing process without using additional masks, and can use the existing implant layer, thereby reducing the Manufacturing cost of the device. In addition, a desired breakdown voltage can be obtained by adjusting a plurality of strip-shaped doped regions in the field plate and the second well region, making the design scope of the electrostatic discharge protection device more flexible. Therefore, the present invention has the advantages of wide application range and simple manufacturing.
以上概述數個實施例之部件,以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解,他們能輕易地以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且他們能在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。The components of several embodiments are summarized above so that those with ordinary knowledge in the technical field to which the present invention belongs can better understand the concepts of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that they can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purposes and/or advantages as the embodiments introduced here. . Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can be used in various ways without departing from the spirit and scope of the present invention. Such changes, substitutions and replacements. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.
10、20、30、40:靜電放電保護裝置
91、92、92’、93、93’、94、95:佈植步驟
100:基底
100s:上表面
120:第一井區
130:第二井區
140a、140b、140c:條狀摻雜區
141:第一條狀摻雜區
142:第二條狀摻雜區
143:第三井區
150:射極
151:接觸件
160:集極
161:接觸件
162:內連線
170:基極
171:接觸件
180:第一摻雜區
181:接觸件
210、220’、230’、240、250:遮蔽層
220:複數個第一條狀遮蔽層
221:第一條狀區
230:複數個第二條狀遮蔽層
231:第二條狀區
310:第一場板
320:第二場板
350:內連線
400:隔離結構
410:第一介電層
420:第二介電層
d1、d1’、d2、d2’、d3、d3’:間距
S1、S2、S3:邊緣
10, 20, 30, 40: Electrostatic
以下將配合所附圖示詳述本揭露之各面向。應注意的是,依據在業界的標準做法,各種特徵並未按照比例繪製且僅用以說明例示。事實上,可能任意地放大或縮小單元的尺寸,以清楚地表現出本揭露的特徵。 第1-7圖根據一些實施例,繪示出本案靜電放電保護裝置在各種製造階段的示意圖。 第8圖根據一些實施例,繪示出本案靜電放電保護裝置的俯視圖。 第9-10圖根據另一些實施例,繪示出本案靜電放電保護裝置在各種製造階段的示意圖。 第11-13圖根據又另一些實施例,繪示出本案靜電放電保護裝置在各種製造階段的示意圖。 第14圖繪示出作為本案比較例的靜電放電保護裝置的示意圖。 第15圖為本案實施例與比較例的靜電放電保護裝置的電流-電壓圖。 Various aspects of the present disclosure will be described in detail below with reference to the accompanying figures. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the cells may be arbitrarily enlarged or reduced to clearly illustrate the features of the present disclosure. Figures 1-7 illustrate schematic diagrams of the electrostatic discharge protection device in various manufacturing stages according to some embodiments. Figure 8 shows a top view of the electrostatic discharge protection device in this case according to some embodiments. Figures 9-10 illustrate schematic diagrams of the electrostatic discharge protection device in various manufacturing stages according to other embodiments. Figures 11-13 illustrate schematic diagrams of the electrostatic discharge protection device in various manufacturing stages according to yet other embodiments. Figure 14 shows a schematic diagram of an electrostatic discharge protection device as a comparative example of this case. Figure 15 is a current-voltage diagram of the electrostatic discharge protection device of the embodiment and the comparative example of this case.
10:靜電放電保護裝置 10: Electrostatic discharge protection device
100:基底 100:Base
100s:上表面 100s: upper surface
120:第一井區 120:First well area
130:第二井區 130:Second well area
140a:複數個條狀摻雜區 140a: Multiple strip-shaped doped regions
141:複數個第一條狀摻雜區 141: A plurality of first strip doping regions
142:複數個第二條狀摻雜區 142: A plurality of second strip-shaped doping regions
150:射極 150: emitter
151:接觸件 151:Contacts
160:集極 160:Jiji
161:接觸件 161:Contacts
162:內連線 162:Internal connection
170:基極 170:Base
171:接觸件 171:Contacts
180:第一摻雜區 180: First doped region
181:接觸件 181:Contacts
310:第一場板 310:First plate
320:第二場板 320: Second plate
400:隔離結構 400:Isolation structure
410:第一介電層 410: first dielectric layer
420:第二介電層 420: Second dielectric layer
d1、d2、d3:間距 d1, d2, d3: spacing
S1:邊緣 S1: Edge
Claims (13)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW112108698A TWI831638B (en) | 2023-03-09 | 2023-03-09 | Electrostatic discharge protection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW112108698A TWI831638B (en) | 2023-03-09 | 2023-03-09 | Electrostatic discharge protection device |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI831638B true TWI831638B (en) | 2024-02-01 |
TW202437507A TW202437507A (en) | 2024-09-16 |
Family
ID=90824732
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW112108698A TWI831638B (en) | 2023-03-09 | 2023-03-09 | Electrostatic discharge protection device |
Country Status (1)
Country | Link |
---|---|
TW (1) | TWI831638B (en) |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160013177A1 (en) * | 2014-07-09 | 2016-01-14 | Rouying Zhan | Esd protection device and related fabrication methods |
US20160300828A1 (en) * | 2015-04-07 | 2016-10-13 | Freescale Semiconductor, Inc. | Esd protection device |
US9502890B2 (en) * | 2013-05-22 | 2016-11-22 | Freescale Semiconductor, Inc. | Protection device and related fabrication methods |
US9620496B2 (en) * | 2015-03-10 | 2017-04-11 | Nxp Usa, Inc. | Stacked protection devices with overshoot protection and related fabrication methods |
EP3367436A1 (en) * | 2017-02-24 | 2018-08-29 | Nxp B.V. | Electrostatic discharge (esd) protection device and method for operating an esd protection device |
CN109427767A (en) * | 2017-08-24 | 2019-03-05 | 新加坡商格罗方德半导体私人有限公司 | The high voltage P NP and its manufacturing method that use for ESD is isolated |
TW202008550A (en) * | 2018-07-30 | 2020-02-16 | 世界先進積體電路股份有限公司 | Semiconductor structure and ESD protection device |
US20210407988A1 (en) * | 2017-10-03 | 2021-12-30 | Nxp Usa, Inc. | Methods of fabricating single-stack bipolar-based esd protection devices |
-
2023
- 2023-03-09 TW TW112108698A patent/TWI831638B/en active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9502890B2 (en) * | 2013-05-22 | 2016-11-22 | Freescale Semiconductor, Inc. | Protection device and related fabrication methods |
US20160013177A1 (en) * | 2014-07-09 | 2016-01-14 | Rouying Zhan | Esd protection device and related fabrication methods |
US9620496B2 (en) * | 2015-03-10 | 2017-04-11 | Nxp Usa, Inc. | Stacked protection devices with overshoot protection and related fabrication methods |
US20160300828A1 (en) * | 2015-04-07 | 2016-10-13 | Freescale Semiconductor, Inc. | Esd protection device |
EP3367436A1 (en) * | 2017-02-24 | 2018-08-29 | Nxp B.V. | Electrostatic discharge (esd) protection device and method for operating an esd protection device |
CN109427767A (en) * | 2017-08-24 | 2019-03-05 | 新加坡商格罗方德半导体私人有限公司 | The high voltage P NP and its manufacturing method that use for ESD is isolated |
US20210407988A1 (en) * | 2017-10-03 | 2021-12-30 | Nxp Usa, Inc. | Methods of fabricating single-stack bipolar-based esd protection devices |
TW202008550A (en) * | 2018-07-30 | 2020-02-16 | 世界先進積體電路股份有限公司 | Semiconductor structure and ESD protection device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8530931B2 (en) | Semiconductor device and method of manufacturing the same | |
US11978733B2 (en) | High-voltage electrostatic discharge devices | |
US11942472B2 (en) | High-voltage electrostatic discharge devices | |
CN104465647A (en) | Stacked protection devices and related fabrication methods | |
US11990466B2 (en) | High voltage electrostatic devices | |
US7012308B2 (en) | Diode | |
US12027587B2 (en) | Electrostatic discharge (ESD) device with improved turn-on voltage | |
US11430881B2 (en) | Diode triggered compact silicon controlled rectifier | |
US20110309409A1 (en) | Semiconductor device | |
TWI831638B (en) | Electrostatic discharge protection device | |
CN113035940B (en) | Grid grounding field effect transistor for ESD protection circuit and preparation method thereof | |
TWI661529B (en) | Transient voltage suppressor | |
US6905924B2 (en) | Diode structure for SOI circuits | |
US12107083B2 (en) | Fin-based and bipolar electrostatic discharge devices | |
US11804481B2 (en) | Fin-based and bipolar electrostatic discharge devices | |
US20240304613A1 (en) | Silicon controlled rectifers with field plate | |
US20230411384A1 (en) | Electrostatic discharge device with pinch resistor | |
US11289471B2 (en) | Electrostatic discharge device | |
US20240243118A1 (en) | Electrostatic device | |
US20240312979A1 (en) | Semiconductor diode structure | |
JP2007184387A (en) | Semiconductor device and its manufacturing method | |
CN117438463A (en) | VDMOSFET (vertical double-diffused metal oxide semiconductor) of integrated SBD (semiconductor on insulator) diode suitable for parallel application and preparation method thereof | |
TWI614901B (en) | Semiconductor structure and method for forming the same | |
CN117199132A (en) | VDMOSFET integrated with SBD diode and preparation method thereof | |
KR20240136835A (en) | Silicon controlled rectifiers with field plate |