KR20020015199A - Electrostatic discharge protection device in a semiconductor device - Google Patents
Electrostatic discharge protection device in a semiconductor device Download PDFInfo
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- KR20020015199A KR20020015199A KR1020000048383A KR20000048383A KR20020015199A KR 20020015199 A KR20020015199 A KR 20020015199A KR 1020000048383 A KR1020000048383 A KR 1020000048383A KR 20000048383 A KR20000048383 A KR 20000048383A KR 20020015199 A KR20020015199 A KR 20020015199A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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Abstract
Description
본 발명은 반도체장치의 정전방전보호소자에 관한 것으로서, 특히, 종래의 입력보호회로를 별도의 독립적인 딥웰(deep well)로 감싸인 트리플 웰 구조로 형성하고 딥웰의 양단을 VCC로 연결하여 입력단을 통하여 외부에서 인가되는 입력 노이즈성분에 의한 메모리소자의 오동작을 방지하여 안정성을 확보하도록 한 반도체장치의 메모리소자의 정전방전보호소자 구조에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection device of a semiconductor device. In particular, a conventional input protection circuit is formed in a triple well structure surrounded by a separate independent deep well, and both ends of the deep well are connected by VCC to connect the input end. The present invention relates to a structure of an electrostatic discharge protection device for a memory device of a semiconductor device which prevents a malfunction of the memory device due to an input noise component applied from the outside to ensure stability.
고전력 구동 반도체집적회로에서 출력단으로 사용되는 고전력 소자의 구조적인 문제인 저농도 도핑영역에 기인한 고저항성에 의하여 정전기가 회로에 인가되었을 때 콘택부위 또는 졍션의 파괴 등 불량이 발생하여 소자의 신뢰도가 저하된다.Due to the high resistance due to the low concentration doping region, which is a structural problem of the high power device used as the output terminal in the high power driving semiconductor integrated circuit, when the static electricity is applied to the circuit, defects such as breakage of contact parts or junctions occur and reliability of the device is degraded. .
종래의 SCR(silicon controlled rectifier) 다이오드(diode)구조는 저전압 구동소자에 적합하도록 설계되었기 때문에 항복전압(breakdown voltage)이 10-30V 정도에 이른다.Conventional silicon controlled rectifier (SCR) diode structures have a breakdown voltage of about 10-30V because they are designed for low voltage driving devices.
종래에는 고전력 반도체 집적회로의 정전방지 보호소자로 고내압을 위한 저농도의 pn졍션 다이오드이다. 즉, 전압-전류 특성이 양극과 음극에 걸리는 전압이 브레이크오버 전압(breakover voltage)에 이르렀을 경우 급격히 과도전류가 흐르게 되어 소자파괴가 발생한다.Conventionally, it is a low concentration pn caption diode for high breakdown voltage as an antistatic protection device of a high power semiconductor integrated circuit. That is, when the voltage applied to the anode and the cathode reaches the breakover voltage, the transient current flows rapidly, resulting in device destruction.
도 1은 종래 기술에 따른 반도체장치의 이에스디 보호회로도로서, 정전방전보호회로에 (-)전위가 인가될 때의 정전회로 보호동작을 예시한 것이다.1 is an ESD protection circuit diagram of a semiconductor device according to the prior art, which illustrates an electrostatic circuit protection operation when a negative potential is applied to an electrostatic discharge protection circuit.
도 1을 참조하면, 일반적으로 정전방전보호회로는 순간적으로 입력패드(10)를 통하여 과도한 전위인 ESD(electrostatic discharge)가 인가되었을 때 내부회로(11)를 보호하기 위하여 사용된다.Referring to FIG. 1, generally, an electrostatic discharge protection circuit is used to protect the internal circuit 11 when an excessive potential electrostatic discharge (ESD) is applied through the input pad 10 at an instant.
입력패드(10)에 (-)전위가 인가되었을 경우, SCR부(SCR) 바이폴라졍션트랜지스터인 Q1의 베이스에 전류 Ib1이 발생하여 Q1의 콜렉터에 증폭된 전류 IC1이 발생하고 이때, 전류 IC1= β*IB1이다. 증폭된 전류 IC1은 또 다른 졍션바이폴라트랜지스터(Q2)를 동작시켜 일반적인 SCR동작인 상호 피드백에 의한 바이폴라트랜지스터 동작으로 입력패드(10)의 (-)전위를 순간적으로 VSS 노드로 전하를 배출하는 역할을 한다.When a negative potential is applied to the input pad 10, a current I b1 is generated at the base of the SCR bipolar junction transistor Q1 to generate an amplified current I C1 at the collector of Q1, and at this time, the current I C1 = β * I B1 . The amplified current I C1 operates another section bipolar transistor (Q2) to discharge electric charges to the VSS node instantaneously with the negative potential of the input pad 10 as a bipolar transistor operation by mutual feedback, which is a general SCR operation. Do it.
또한, 클램프 다이오드부(CLD)에서는, 문턱전압(Vth) 만큼의 전위차가 발생하면 모스 트랜지스터(Q3)가 턴온되어 (-)전위를 VSS로 배출(sink)시킨다.In the clamp diode unit CLD, when the potential difference equal to the threshold voltage Vth occurs, the MOS transistor Q3 is turned on to sink the negative potential to VSS.
도 2는 종래 기술에 따른 반도체장치의 이에스디 보호소자의 단면도이다.2 is a cross-sectional view of an ESD protection element of a semiconductor device according to the prior art.
도 2를 참조하면, SCR부(SCR)와 클램프 다이오드부(CLD)가 정의된 반도체기판(20)인 p형 실리콘기판(20)의 SCR부(SCR)에 제 1 n웰(21)과 제 2 n웰(22)이 제 1 필드산화막(24)에 의하여 격리된 상태로 소정의 깊이로 저농도로 도핑되어 형성되어 있다.Referring to FIG. 2, the first n well 21 and the first n well 21 may be formed in the SCR portion SCR of the p-type silicon substrate 20, which is the semiconductor substrate 20 in which the SCR portion SCR and the clamp diode portion CLD are defined. 2 n wells 22 are formed by being doped at low concentration to a predetermined depth in a state in which they are isolated by the first field oxide film 24.
그리고, 기판의 클램프 다이오드부(CLD)에는 제 2 n웰(22)과 소정거리 이격되어 제 3 n웰(23)이 저농도로 도핑되어 형성되어 있다.In the clamp diode portion CLD of the substrate, the third n well 23 is spaced apart from the second n well 22 by a predetermined distance and is doped at a low concentration.
SCR부(SCR)를 살펴보면, 제 1 n웰(21)의 상부에 해당하는 기판에는 n형 고농도 도핑영역이 형성되어 있고, 제 2 n웰(22)의 상부에 해당하는 기판에는 n+/p+/n+/p+/n+의 고농도 도핑영역들이 졍션을 이루며 차례로 형성되어 있다.Referring to the SCR portion SCR, an n-type high concentration doping region is formed in a substrate corresponding to the upper portion of the first n well 21, and n + / p + / in a substrate corresponding to the upper portion of the second n well 22. High concentration doped regions of n + / p + / n + are formed in a sequential order.
SCR부(SCR)와 클램프 다이오드부(CLD)의 경계면에 인접한 n+고농도 도핑영역에는 또 다른 제 2 필드산화막(25)이 위치하고 있다.Another second field oxide film 25 is positioned in the n + high concentration doping region adjacent to the interface between the SCR portion SCR and the clamp diode portion CLD.
한편, 클램프 다이오드부(CLD)는 제 3 n웰(23)과 일부 중첩하며 제 2 필드산화막(25)과의 사이에 또 다른 n+ 고농도 도핑영역이 위치한다.Meanwhile, the clamp diode part CLD partially overlaps the third n well 23, and another n + high concentration doped region is positioned between the second field oxide layer 25.
제 2 필드산화막(25) 타측의 제 3 n웰(23)의 경게부에는 제 3 필드산화막(26)이 형성되어 NMOS 트랜지스터(Q3)와 npn 바이폴라트랜지스터(Q2)를 격리시킨다. 이때, NMOS 트랜지스터(Q3)의 게이트와 소스단자는 VSS에 연결된다.A third field oxide film 26 is formed in the path portion of the third n well 23 on the other side of the second field oxide film 25 to isolate the NMOS transistor Q3 and the npn bipolar transistor Q2. At this time, the gate and source terminals of the NMOS transistor Q3 are connected to VSS.
정전방전보호소자의 바이폴라트랜지스터들을 살펴보면 다음과 같다.The bipolar transistors of the electrostatic discharge protection device are as follows.
SCR부(SCR)에서, 제 1 n웰(21)에 형성된 n+ 고농도 도핑영역/p형 기판/제 2 n웰의 n+ 고농도 도핑영역은 제 2 바이폴라트랜지스터(Q2)가 되고, n+/p+/n+/p+/n+의 고농도 도핑영역들에서 중앙에 위치한 n+고농도 도핑영역과 인접한 p+고농도 도핑영역/제 2 n웰(22)/p형 기판(20)은 제 1 바이폴라트랜지스터(Q1)가 된다.In the SCR portion SCR, the n + high concentration doping region / p type substrate / n type high concentration doping region of the second n well formed in the first n well 21 becomes the second bipolar transistor Q2, and n + / p + / n +. In the heavily doped regions of / p + / n +, the p + heavily doped region / second n well 22 / p-type substrate 20 adjacent to the n + heavily doped region located at the center becomes the first bipolar transistor Q1.
이러한, 제 1 바이폴라트랜지스터(Q1)와 제 2 바이폴라트랜지스터(Q2)는 n+/p+/n+/p+/n+의 고농도 도핑영역들에서 중앙에 위치한 n+고농도 도핑영역을 중심으로 대칭되도록 한 쌍을 이루도록 형성되어 있다.The first bipolar transistor Q1 and the second bipolar transistor Q2 are formed in a pair so as to be symmetrical with respect to the n + high concentration doping region located at the center in the high concentration doping regions of n + / p + / n + / p + / n +. It is.
또한, n+/p+/n+/p+/n+의 고농도 도핑영역들에서 중앙에 위치한 n+고농도 도핑영역과 양쪽에 위치한 p+영역들은 입력패드(27)와 내부회로(28)를 연결하는 배선에 병렬로 연결되고 모스 트랜지스터(Q3)의 드레인은 역시 병렬로 내부회로(28)에 연결된다.Also, in the high concentration doping regions of n + / p + / n + / p + / n +, the n + high concentration doping region and the p + regions located on both sides are connected in parallel to the wiring connecting the input pad 27 and the internal circuit 28. And the drain of the MOS transistor Q3 is also connected to the internal circuit 28 in parallel.
상기와 같은 구조의 정전방전보호회로에서, ESD동작외에 일반적인 메모리 동작이 일어나는 경우, 입력패드(27)에 (-)전위가 입력되면 기판(20)으로의 전자유입이 일어난다. 아러한 기판으로의 유입전자들은 SCR부(SCR)와 인접한 인근회로부(도시안함)에 형성된 n웰로 p형 기판(20)을 통하여 이동하게 된다.In the electrostatic discharge protection circuit having the above structure, when a general memory operation occurs in addition to the ESD operation, when a negative potential is input to the input pad 27, electrons flow into the substrate 20. Inflow electrons to such a substrate are moved through the p-type substrate 20 to n wells formed in an adjacent circuit portion (not shown) adjacent to the SCR portion SCR.
이와 같이 종래기술에서는 인근회로부로 전파된 전하는 인근회로부 n웰의 바이어스 전위를 낮추어 인근회로의 오동작을 유발하게 된다.As described above, the electric charge propagated to the neighboring circuit part lowers the bias potential of the neighboring circuit part n well to cause the malfunction of the neighboring circuit.
특히, 종래 기술에서 정전방전보호회로의 인근회로가 정전압회로와 같이 전류소모를 극도로 억제하는 회로인 경우, N웰 전위변화에 민감하게 반응하여 오동작이 유발되는 문제점이 있다.In particular, in the prior art, when the neighboring circuit of the electrostatic discharge protection circuit is a circuit that suppresses current consumption extremely like a constant voltage circuit, there is a problem that a malfunction occurs due to a sensitive response to the change in the N well potential.
따라서, 본 발명의 목적은 SCR부와 클램프 다이오드부를 포함하는 종래의 입력보호회로를 별도의 독립적인 딥웰(deep well)로 감싸인 트리플 웰 구조로 형성하고 딥웰의 양단을 VCC로 연결하여 입력단을 통하여 외부에서 인가되는 입력 노이즈성분에 의한 메모리소자의 오동작을 방지하여 안정성을 확보하도록 한 반도체장치의 메모리소자의 정전방전보호소자 구조를 제공하는데 있다.Accordingly, an object of the present invention is to form a triple well structure in which a conventional input protection circuit including an SCR part and a clamp diode part is wrapped in a separate independent deep well, and the both ends of the deep well are connected to the VCC through an input terminal. The present invention provides an electrostatic discharge protection device structure of a memory device of a semiconductor device which prevents a malfunction of the memory device due to an input noise component applied from the outside to ensure stability.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치의 정전방전보호소자는 SCR회로부와 클램프 다이오드부가 정의된 p형 반도체 기판과, 상기 기판의 상기 SCR회로부에 서로 격리되어 위치하고 제 1 저농도로 도핑된 제 1, 제 2 n형 웰과, 상기 제 1 n형 웰의 상부에 형성된 제 1 n+ 고농도 도핑영역과, 상기 제 2 n형 웰의 상부중앙에서 모서리방향으로 졍션을 이루며 차례로 형성된 제 2 n+ 고농도 도핑영역/p+ 고농도 도핑영역/제 3 n+ 고농도 도핑영역과, 상기 클램프 다이오드부에 서로 격리되어 위치한 제 3 n형 웰 및 저농도로 도핑된 p형 웰과, 상기 제 1 내지 제 3 n형 웰과 상기 p형 웰을 상호 격리시키도록 상기 기판의 소정 부위에 형성된 소자격리막과, 상기 제 3 n형 웰의 상부 표면 일부에 형성된 제 4 n+ 고농도 도핑영역과, 상기 p형 웰에 형성되고 게이트, 소스, 드레인으로 이루어진 NMOS 트랜지스터와, 상기 클램프 다이오드부와 상기 SCR부를 주머니 형태로 감싸도록 상기 기판에 상기 제 1 저농도보다 더 낮은 제 2 농도의 n형 불순물로 도핑된 보호웰과, 상기 보호웰의 모서리부에 고농도 n형 불순물로 도핑된 연결단자를 포함하여 이루어진다.The electrostatic discharge protection device of the semiconductor device according to the present invention for achieving the above objects is a p-type semiconductor substrate in which an SCR circuit portion and a clamp diode portion are defined, and a first lightly doped first position which is isolated from each other in the SCR circuit portion of the substrate. , A second n-type well doped region formed on top of the first n-type well, and a second n + heavily doped region formed in a circumferential direction at an upper center of the second n-type well. / p + high concentration doping region / third n + high concentration doping region, third n-type wells and low-doped p-type wells isolated from each other in the clamp diode portion, the first to third n-type wells and the p A device isolation film formed in a predetermined portion of the substrate to isolate the wells from each other, a fourth n + high concentration doped region formed in a portion of the upper surface of the third n-type well, and formed in the p-type well An NMOS transistor comprising a source and a drain, a protection well doped with n-type impurities having a second concentration lower than the first low concentration on the substrate to surround the clamp diode portion and the SCR portion in a bag shape; It comprises a connection terminal doped with a high concentration of n-type impurities in the corner of the.
도 1은 종래 기술에 따른 반도체장치의 이에스디 보호회로도1 is an ESD protection circuit diagram of a semiconductor device according to the prior art.
도 2는 종래 기술에 따른 반도체장치의 이에스디 보호소자의 단면도2 is a cross-sectional view of an ESD protection element of a semiconductor device according to the prior art;
도 3은 본 발명에 따른 반도체장치의 이에스디 보호소자의 단면도3 is a cross-sectional view of an ESD protection element of a semiconductor device according to the present invention.
본 발명은 반도체 메모리의 정전방전보호회로에 관한 것으로 외부에서 인가되는 입력 노이즈 성분에 의한 메모리 칩의 오동작을 방지하고자 하는 것이다.The present invention relates to an electrostatic discharge protection circuit of a semiconductor memory, and is intended to prevent a malfunction of a memory chip due to an input noise component applied from the outside.
본 발명은 SCR(silicon controlled rectifer)회로부, 클램프 다이오드부 및 상기 SCR부와 클램프 다이오드부를 감싸는 웰부로 구성된다. 즉, 본 발명에서는 종래 기술과 차별되게 독립적인 딥웰(deep well)을 채용하여 정전방전보호회로 소자들을 감싸는 구조를 갖는다.The present invention includes a silicon controlled rectifer (SCR) circuit portion, a clamp diode portion, and a well portion surrounding the SCR portion and the clamp diode portion. That is, the present invention has a structure that surrounds the electrostatic discharge protection circuit elements by adopting an independent deep well (independent of the prior art).
따라서, 본 발명에 따른 정전방지보호소자에서는 입력패드를 통하여 (-)전위가 인가되어도 정전방지보호회로용 독립웰이 설치되어 전하가 기판으로 유입되어 인근회로부로 전파되지 않고 VCC로 흡수되는 구조를 갖는다.Therefore, in the antistatic protection device according to the present invention, even if a negative potential is applied through an input pad, an independent well for an antistatic protection circuit is installed so that charge flows into a substrate and is absorbed into the VCC without propagating to a neighboring circuit portion. Have
따라서, 본 발명에서는 종래의 정전방전보호소자와 달리 독립적인 웰로 SCR부와 클램프 다이오드부를 감싸도록 하여 입력단에 (-)전위가 인가되어도 정전압회로 등 인근회로에 전하가 전파되는 것을 원천적으로 봉쇄하여 메모리 소자 동작의 안정성을 확보할 수 있다.Therefore, in the present invention, unlike the conventional electrostatic discharge protection device, so as to surround the SCR portion and the clamp diode portion with independent wells, even if a negative potential is applied to the input terminal, the charge is propagated to the neighboring circuits such as a constant voltage circuit, thereby blocking the memory. The stability of device operation can be ensured.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 반도체장치의 이에스디 보호소자의 단면도이다.3 is a cross-sectional view of an ESD protection element of a semiconductor device according to the present invention.
도 3을 참조하면, SCR부(SCR)와 클램프 다이오드부(CLD)가 정의된 반도체기판(30)인 p형 실리콘기판(30)의 SCR부(SCR)에 제 1 n웰(32)과 제 2 n웰(33)이 제 1 소자격리막(36)에 의하여 격리된 상태로 소정의 깊이로 저농도로 도핑되어 형성되어 있다.Referring to FIG. 3, the first n well 32 and the first n well 32 are formed in the SCR portion SCR of the p-type silicon substrate 30, which is the semiconductor substrate 30 in which the SCR portion SCR and the clamp diode portion CLD are defined. 2 n wells 33 are formed by being doped at low concentration to a predetermined depth in a state in which they are isolated by the first device isolation film 36.
그리고, 기판의 클램프 다이오드부(CLD)에는 제 2 n웰(33)과 소정거리 이격되고 제 2 소자격리막(37)에 의하여 격리된 제 3 n웰(34)이 저농도로 도핑되어 형성되어 있다. 이때, 제 1 소자격리막(36)과 제 2 소자격리막(37)은 서로 연결되어 제 2 n웰(33)을 레이아웃상 둘러싸고 있는 형태를 갖는다.In the clamp diode portion CLD of the substrate, a third n well 34 spaced apart from the second n well 33 by a predetermined distance and isolated by the second device isolation layer 37 is doped at low concentration. In this case, the first device isolation layer 36 and the second device isolation layer 37 may be connected to each other to surround the second n well 33 in a layout manner.
그리고, 제 3 n웰(34)은 제 2 소자격리막(37)과 연결된 제 3 소자격리막(38)에 의하여 저농도로 도핑된 p웰(35)과 결리된다. p웰(35)에는 NMOS 트랜지스터가 형성되어 있다.In addition, the third n well 34 is separated from the p well 35 that is lightly doped by the third device isolation film 38 connected to the second device isolation film 37. An NMOS transistor is formed in the p well 35.
SCR부(SCR)를 살펴보면, 제 1 n웰(32)의 상부에 해당하는 기판에는 n형 고농도 도핑영역이 형성되어 있고, 제 2 n웰(33)의 상부에 해당하는 기판에는 n+/p+/n+/p+/n+의 고농도 도핑영역들이 졍션을 이루며 차례로 형성되어 있다.Looking at the SCR portion (SCR), the n-type high concentration doping region is formed in the substrate corresponding to the upper portion of the first n well 32, n + / p + / in the substrate corresponding to the upper portion of the second n well 33 High concentration doped regions of n + / p + / n + are formed in a sequential order.
SCR부(SCR)와 클램프 다이오드부(CLD)의 경계면에 인접한 n+고농도 도핑영역에는 또 다른 제 2 소자격리막(37)이 위치하고 있다.Another second device isolation layer 37 is positioned in the n + high concentration doping region adjacent to the interface between the SCR portion SCR and the clamp diode portion CLD.
한편, 클램프 다이오드부(CLD)는 제 3 n웰(34)과 일부 중첩하며 제 2 소자격리막(37)과의 사이에 또 다른 n+ 고농도 도핑영역이 위치한다.Meanwhile, the clamp diode part CLD partially overlaps the third n well 34, and another n + high concentration doping region is positioned between the second device isolation layer 37.
제 2 소자격리막(37) 타측의 제 3 n웰(34)의 경계부 위치한 제 3 소자격리막(38)은 NMOS 트랜지스터와 npn 바이폴라트랜지스터를 격리시킨다. 이때, NMOS 트랜지스터의 게이트와 소스단자는 VSS에 연결된다.The third device isolation film 38 positioned at the boundary of the third n well 34 on the other side of the second device isolation film 37 isolates the NMOS transistor from the npn bipolar transistor. At this time, the gate and source terminals of the NMOS transistor are connected to VSS.
그리고, 기판(30)에는 상기 SCR부(SCR)와 클램프 다이오드부(CLD)를 감싸는 포켓구조의 딥 n웰(31)이 상기 제 1 내지 제 3 n웰(32,33,34)보다 낮은 초저농도로 도핑되어 있다.In addition, a deep n well 31 having a pocket structure surrounding the SCR part SCR and the clamp diode part CLD may have a lower thickness than that of the first to third n wells 32, 33, and 34. It is lightly doped.
이러한, 딥 n웰(31)의 모서리부위에는 고농도로 도핑된 한 쌍의 n+ 도핑영역이 위치하여, 각각 VCC에 연결된다.A pair of highly doped n + doped regions are located at the corners of the deep n well 31 and are connected to the VCCs, respectively.
또한, n+/p+/n+/p+/n+의 고농도 도핑영역들에서 중앙에 위치한 n+고농도 도핑영역과 양쪽에 위치한 p+영역들은 입력패드(39)와 내부회로(40)를 연결하는 배선에 병렬로 연결되고 모스 트랜지스터의 드레인은 역시 병렬로 내부회로(40)에 연결된다.In addition, the n + high concentration doping regions located at the center of the high concentration doping regions of n + / p + / n + / p + / n + and the p + regions located at both sides are connected in parallel to the wiring connecting the input pad 39 and the internal circuit 40. The drain of the MOS transistor is also connected to the internal circuit 40 in parallel.
따라서, 본 발명은 종래의 정전방전보호소자와 달리 독립적인 웰로 SCR부와 클램프 다이오드부를 감싸도록 하여 입력단에 (-)전위가 인가되어도 정전압회로 등 인근회로에 전하가 전파되는 것을 원천적으로 봉쇄하여 메모리 소자 동작의 안정성을 확보하는 장점이 있다.Therefore, in the present invention, unlike the conventional electrostatic discharge protection device, the SCR part and the clamp diode part are wrapped in independent wells so that charge is propagated to nearby circuits such as constant voltage circuits even when a negative potential is applied to the input terminal. There is an advantage of ensuring the stability of the device operation.
Claims (5)
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7355252B2 (en) | 2003-12-15 | 2008-04-08 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection device and method of fabricating the same |
| US7633096B2 (en) | 2005-08-10 | 2009-12-15 | Samsung Electronics Co., Ltd. | Silicon-controlled rectifier for electrostatic discharge protection circuits and structure thereof |
| US7741680B2 (en) * | 2008-08-13 | 2010-06-22 | Analog Devices, Inc. | Electro-static discharge and latchup resistant semiconductor device |
| KR100976410B1 (en) * | 2008-05-28 | 2010-08-17 | 주식회사 하이닉스반도체 | Electrostatic Discharge Device |
| KR101006514B1 (en) * | 2004-04-28 | 2011-01-07 | 매그나칩 반도체 유한회사 | A silicon controlled rectifier for protecting the device in a electrostatic discharge |
| US9799641B2 (en) | 2014-12-08 | 2017-10-24 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection device and electronic device having the same |
| CN112889150A (en) * | 2021-01-13 | 2021-06-01 | 香港应用科技研究院有限公司 | Transistor injection Silicon Controlled Rectifier (SCR) with vertical trigger and discharge path |
| US11302689B1 (en) | 2021-01-13 | 2022-04-12 | Hong Kong Applied Science and Technology Research Institute Company Limited | Transistor-injected silicon-controlled rectifier (SCR) with perpendicular trigger and discharge paths |
| CN116454080A (en) * | 2022-01-10 | 2023-07-18 | 长鑫存储技术有限公司 | Electrostatic protection structure and electrostatic protection circuit |
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- 2000-08-21 KR KR1020000048383A patent/KR20020015199A/en not_active Application Discontinuation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7355252B2 (en) | 2003-12-15 | 2008-04-08 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection device and method of fabricating the same |
| KR101006514B1 (en) * | 2004-04-28 | 2011-01-07 | 매그나칩 반도체 유한회사 | A silicon controlled rectifier for protecting the device in a electrostatic discharge |
| US7633096B2 (en) | 2005-08-10 | 2009-12-15 | Samsung Electronics Co., Ltd. | Silicon-controlled rectifier for electrostatic discharge protection circuits and structure thereof |
| KR100976410B1 (en) * | 2008-05-28 | 2010-08-17 | 주식회사 하이닉스반도체 | Electrostatic Discharge Device |
| US8039899B2 (en) | 2008-05-28 | 2011-10-18 | Hynix Semiconductor Inc. | Electrostatic discharge protection device |
| US7741680B2 (en) * | 2008-08-13 | 2010-06-22 | Analog Devices, Inc. | Electro-static discharge and latchup resistant semiconductor device |
| US9799641B2 (en) | 2014-12-08 | 2017-10-24 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection device and electronic device having the same |
| US10134723B2 (en) | 2014-12-08 | 2018-11-20 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection device and electronic device having the same |
| CN112889150A (en) * | 2021-01-13 | 2021-06-01 | 香港应用科技研究院有限公司 | Transistor injection Silicon Controlled Rectifier (SCR) with vertical trigger and discharge path |
| US11302689B1 (en) | 2021-01-13 | 2022-04-12 | Hong Kong Applied Science and Technology Research Institute Company Limited | Transistor-injected silicon-controlled rectifier (SCR) with perpendicular trigger and discharge paths |
| WO2022151396A1 (en) * | 2021-01-13 | 2022-07-21 | Hong Kong Applied Science and Technology Research Institute Company Limited | Transistor-injected silicon-controlled rectifier (scr) with perpendicular trigger and discharge paths |
| CN112889150B (en) * | 2021-01-13 | 2023-10-31 | 香港应用科技研究院有限公司 | Transistor injection type Silicon Controlled Rectifier (SCR) with vertical trigger and discharge paths |
| CN116454080A (en) * | 2022-01-10 | 2023-07-18 | 长鑫存储技术有限公司 | Electrostatic protection structure and electrostatic protection circuit |
| CN116454080B (en) * | 2022-01-10 | 2024-05-14 | 长鑫存储技术有限公司 | Electrostatic protection structure and electrostatic protection circuit |
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