JP3191209B2 - Electrostatic breakdown prevention device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to an electrostatic discharge prevention device capable of protecting an internal circuit from static electricity (ESD).

[0002]

2. Description of the Related Art As the chip size decreases, the size of an electrostatic protection circuit also decreases. In particular, in ultra-high-integration devices and ultra-high-speed devices, the capacitance generated near the junction of the electrostatic protection circuit has been a major cause of RC delay. Therefore, there is a problem that the joining area must be further reduced. However, when an electrostatic protection circuit is formed using an existing parasitic bipolar transistor (generally using a field transistor), there is a limit in reducing the junction capacitance and maintaining the performance of the electrostatic protection as it is. The middle field transistor is a transistor in which a gate is formed in front of a field insulating layer and impurity regions are formed on both sides of a substrate. Therefore, unlike a normal FET, the threshold voltage is increased due to the thick gate oxide film. Typically, thyristors are 2 per unit area more than bipolar transistors.
Since the current discharging capacity is twice or more, even if the junction area is small, the protection against static electricity can be realized more efficiently than when the bipolar transistor is used. An electrostatic protection circuit using such a thyristor (SCR) is described in U.S. Pat. No. 4,896,243.

As shown in FIG. 1, a general electrostatic breakdown prevention device forms an electrostatic protection circuit by using the withstand voltage of a well. An N well 2 in which a low concentration impurity is implanted is formed in a predetermined region in a P-type substrate 1, and a high concentration first N ⁺ impurity region 3 and a first P ⁺ impurity region 4 are respectively formed in the N well 2.
To form Then, a second N ⁺ impurity region 3a and a second P ⁺ impurity region 4a are formed in predetermined regions in the P-type substrate 1 other than the N well 2. FIG. 2 shows an equivalent circuit of the electrostatic discharge protection device.

That is, the N well 2 in FIG. 1 corresponds to the first N layer 22 in FIG. Then, the first P ⁺ impurity region 4 of FIG.
Is formed in the N well 2 by impurity diffusion, and corresponds to the first P layer 24 in FIG. Therefore, the first N layer 22
And the first P layer 24 form a PN junction. And
The first P layer 24 is connected to the pad PAD. FIG.
The second N ⁺ impurity region 3a corresponds to the second N layer 23 in FIG. Therefore, a PN junction is formed with the P-type substrate 1 of FIG. Then, the second N ⁺ impurity region 3a and the second P ⁺
Impurity region 4a is connected to ground or Vss.

In such a device for preventing electrostatic breakdown, as shown in FIG. 1, when static electricity is applied to a pad, a breakdown occurs in the N well 2 and carriers are injected into the P-type substrate 1. Carrier is the second N ⁺ of the P-type substrate 1
The NPN bipolar transistor operates by flowing into the junction with the impurity region 3a, finally forming a PNPN path, and the carriers applied by the static electricity escape.

However, in the case of the thyristor using the withstand voltage of the well as described above, the trigger voltage is as high as about 30 to 50 V. Therefore, there is no problem with the electrostatic protection element itself. The phenomenon that a joint part etc. is destroyed arises. Therefore, instead of using the breakdown voltage of the well to lower the trigger voltage of the thyristor, a method using the breakdown voltage of the junction has been attempted. FIG. 3 is a drawing showing an electrostatic breakdown prevention device using the withstand voltage of the junction. As shown in FIG. 3, in the electrostatic breakdown prevention device using the withstand voltage of the junction, the withstand voltage of the junction is reduced to about 10 to 15 V. However, when the thickness of the gate insulating film is 100 ° or less, the breakdown voltage of the gate insulating film is about 12 V, so that the junction breakdown voltage and the breakdown voltage of the gate insulating film are almost the same. Therefore, the characteristics of the gate insulating film due to static electricity are considerably deteriorated. In particular, since the thickness of the gate insulating film of an ultra-highly integrated device of 256 MDRAM or more is very thin, the problem that the characteristics of such a gate insulating film deteriorates is more serious. Therefore, in order to solve such a problem, a thyristor is used to form an electrostatic protection element, and another synchronous circuit is formed to generate hot carriers at the time of applying static electricity. Attempts have been made to lower this.

FIG. 4 shows an electrostatic discharge prevention device using such a thyristor and a hot carrier generation circuit. V
The initial electrostatic protection circuit against the positive (+) polarity stress of Vcc with respect to ss is provided by an SCR structure comprising bipolar transistors Q1 and Q2 formed using NPN and PNP. The resistances of the N-well and P-well are represented by R _NW and R _PN , respectively, as shown in FIG. SCR is N
The injection of the hot carriers generated by the MOS transistor M1 into the base of the transistor Q1 triggers a low impedance state. The transistors M2 to M5 are S
This circuit controls the CR trigger and generates hot carriers only during the occurrence of ESD. Transistor M2 acts as a capacitor and transistor M2
Vcc power is supplied to one gate. The gate of the transistor M1 is connected to Vss via the transistor M3 which is turned on when the transistor M5 is turned on. Transistors M2 and M3 are connected to NMO during an ESD event.
It is used to ensure that a gate voltage Vgate greater than Vt of the SFET is obtained.

During normal operation of the electrostatic discharge protection circuit using such a hot carrier generation circuit, the transistor M
3 holds the gate voltage of the transistor M1 at V _ss and S
Prevent CR trigger. Then, the transistor M4 operates as an ESD clamp for limiting a voltage across the gate oxide film of the transistor M2.

However, the conventional method of preventing electrostatic breakdown using a hot carrier has the following problems. In the case of using the withstand voltage of the junction, the thickness of the gate insulating film becomes thinner as the ultra-high-speed element is formed, so that the withstand voltage of the insulating film is reduced in proportion thereto. However, since the withstand voltage of the junction does not decrease, it is almost impossible to protect static electricity using the withstand voltage of the junction. When hot carriers are used, the synchronous circuit stops operating when static electricity accumulates due to deterioration of the element itself due to the generation of hot carriers. In addition, a separate equivalent circuit must be added to generate hot carriers, which complicates the configuration.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and has as its object to add a separate circuit for lowering the trigger voltage of a thyristor without damaging a gate insulating film. An object of the present invention is to provide an electrostatic discharge protection device that can protect static electricity without giving it.

[0011]

In order to achieve the above object, an electrostatic discharge protection device according to the present invention has first and second impurity regions, and is fixed within a semiconductor substrate of a first conductivity type. A bipolar transistor formed at an interval of, a field transistor each having two impurity regions formed on both sides thereof with an isolation film therebetween, and formed on both sides of the bipolar transistor; A gate line connected to one of the impurity regions of the transistor and formed on the semiconductor substrate between the first impurity region and the second impurity region of the bipolar transistor; A contact hole is formed in the impurity region not connected to the gate line and the first impurity region of the bipolar transistor. And Vss line connected through,
A metal layer connected to the second impurity region of the bipolar transistor through a contact hole and connected to a pad.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of an electrostatic discharge protection device according to an embodiment of the present invention. FIG. 5 is a layout diagram of the electrostatic discharge protection device of the present embodiment, FIG. 6 is a cross-sectional view taken along the line II ′ of FIG. 5, and FIG.
FIG. 2 is a sectional view taken along the line II ′. In the present embodiment, the first conductivity type first impurity region 3 is formed in the first conductivity type semiconductor substrate 31.
The first impurity region 33 and the second impurity region 34 of the second conductivity type are formed on both sides of the second impurity region 2. A second conductivity type well 35 is further formed in the semiconductor substrate 31. The well 35 of the second conductivity type includes a first impurity region 32 of the first conductivity type and a second impurity region 34 of the second conductivity type.
And is formed on the lower side of the first impurity region 33 of the second conductivity type so as to partially overlap the first impurity region 33. On the surface of the semiconductor substrate 31, a third impurity region 36 of the second conductivity type is further formed at a certain distance from the first impurity region 33 of the second conductivity type.
These impurity regions are formed in an elongated rectangular shape as shown in FIG. 5, and are arranged substantially in parallel with each other.

Fourth and fifth impurity regions 38 and 38a of the second conductivity type formed in a direction perpendicular to these impurity regions at a position slightly perpendicular to the impurity regions arranged in parallel with each other. Is formed. These impurity regions are also formed in a rectangular shape as shown in the figure with a space between them, and are arranged with a first element isolation film 37 interposed therebetween. The sixth and seventh impurity regions 39 of the second conductivity type are symmetrically located with respect to the fourth and fifth impurity regions with the first, second, and third impurity regions of the second conductivity type interposed therebetween. , 39a
Is arranged.

In FIG. 5, the hatched portions are all metal layers. The first metal layer 40 is formed of a third metal of the second conductivity type.
It is formed above the fifth and seventh impurity regions 36, 38a, 39a, and is connected to them through contact holes. The second metal layer 41 is made of a fourth conductive type fourth metal layer.
It is arranged above the sixth impurity regions 38 and 39 and is connected to them through contact holes. As shown, the second metal layer 41 is vertically divided in the drawing.
A gate line 42 is formed to connect these. The gate line 42 is formed on the semiconductor substrate 31 between the first impurity region 33 of the second conductivity type and the third impurity region 36 of the second conductivity type (see FIG. 6). On the first and second element isolation films 37 and 37a, the third
A metal layer 43 is formed. Finally, the fourth metal layer 44
Are the first and second impurity regions 33 and 34 of the second conductivity type and the first
It is formed above the first impurity region 32 of the conductivity type.
The first impurity region 32 of the first conductivity type and the second impurity region 34 of the second conductivity type are connected through a contact hole. The fourth metal layer 44 is not connected to the first impurity region 33 of the second conductivity type. Third and fourth metal layers 43 and 4
A pad 45 is electrically connected to 4. A bipolar transistor is formed by the first impurity region 32 of the first conductivity type, the first impurity region 33 of the second conductivity type, and the second impurity region 34 of the second conductivity type. In addition, the third, fifth, and seventh impurity regions 36, 3 of the second conductivity type.
The first metal layer 40 formed on the upper side of 8a and 39a is used as a Vss line for applying a power supply voltage. further,
A fourth impurity region 38 of the second conductivity type and a fifth impurity region 38 of the second conductivity type;
A field transistor is formed by the impurity region 38a and the third metal layer 43 formed on the isolation film 37. In the present embodiment, the first conductivity type is a P conductivity type, and the second conductivity type is an N conductivity type.

The cross-sectional shape will be described below. FIG. 6 shows FIG.
FIG. 7 is a cross-sectional view taken along the line II ′ of FIG.
FIG. 2 is a sectional view taken along the line II ′. First, as shown in FIG. 6, the electrostatic discharge protection device of the present embodiment includes a second conductive type well 35 in a predetermined region of an active region defined by a field oxide film 61 of a semiconductor substrate 31 of a first conductive type. Are formed. A first impurity region 32 of the first conductivity type is formed in the well 35 of the second conductivity type, and a second impurity region 34 of the second conductivity type is formed along one side thereof. Further, a first impurity region 33 of the second conductivity type is formed on the other side of the first impurity region 32 of the first conductivity type, but is different from the regions 32 and 34 in the well 35 of the second conductivity type. Only contains a part. A third impurity region 36 of the second conductivity type is formed on the surface of the substrate apart from the region 33. A gate line 42 is arranged on the semiconductor substrate 31 between the first impurity region 33 of the second conductivity type and the third impurity region 36 via an insulating layer. A Vss line 40 is formed electrically connected to the third impurity region of the second conductivity type. This is the fifth impurity region 38
a, and is also connected to the seventh impurity region 39a as described above. Furthermore, the first impurity region 3 of the first conductivity type
The fourth metal layer 44 connected to the upper side of the second and second conductivity type second impurity regions 34 through respective contact holes.
Are formed. Impurity regions 32, 33, 34, 36
And a gate line 42, a bipolar transistor is formed, and the third impurity region 36 of the second conductivity type is connected to the Vss line.

FIG. 7 is a sectional view of the field transistor taken along the line II-II 'of FIG. That is, the semiconductor substrate 31 of the first conductivity type, the fourth and fifth impurity regions 38 and 38 a of the second conductivity type formed in a predetermined region of the substrate 31 via the element isolation film 37, and the element isolation film 37. And a third metal layer 43 formed on the upper side and electrically connected to the pad 5
A Vss line connected to the fifth impurity region 38a of the second conductivity type through a contact hole; and a second metal layer 41 electrically connecting the fourth impurity region 38 of the second conductivity type to the gate line 42. It is composed of A field transistor is similarly formed in the sixth and seventh impurity regions 39 and 39a on the lower side of FIG.

Hereinafter, the operation of the thus configured electrostatic discharge protection device of the present embodiment will be described. In this embodiment, since the gate electrode 42 of the bipolar transistor is not grounded but is connected to the N ⁺ layer 38 of the field transistor, when static electricity is applied through the pad, the gate electrode 42 of the bipolar transistor A breakdown voltage is induced depending on the degree of coupling between the field transistor capacitance and the bipolar transistor gate capacitance. Accordingly, the bipolar transistor can be operated at a lower voltage than when the gate electrode 42 of the bipolar transistor is connected to the ground terminal. That is, since a predetermined voltage is induced in the gate electrode, a BVDSS (Breakdown Voltag
e Drain Source Short) can be obtained. Therefore, the bipolar transistor can operate even at a low voltage. As can be seen from the above configuration, the gate electrode 42 of the bipolar transistor
Instead of being connected to the power supply terminal, it is connected to the field transistor. Therefore, when static electricity is applied, an effect is obtained in which a predetermined voltage is applied to the gate. Snapback (snap bac) in the items for evaluating transistor characteristics
k) Measure the operating voltage of the parasitic bipolar transistor by measuring the voltage. Generally, since the snapback voltage is lower than the BVDSS voltage, the use of the snapback voltage effectively removes static electricity. In the present embodiment, the operating voltage of the thyristor is reduced to 10 V or less by synchronizing the thyristor, so that the thyristor can be applied to a process in which the thickness of the oxide film is 100 ° or less.

[0018]

Since the electrostatic discharge protection device of the present invention does not require a separate circuit to lower the trigger voltage of the thyristor, the layout design is easy and the circuit deterioration characteristics are improved. Further, even if an active element is used to lower the trigger voltage of the thyristor, another electrostatic protection element for lowering the BVDSS voltage is not required. further,
The present invention can be used even in a process where the thickness of the gate oxide film is less than 100 ° without changing the process of the electrostatic protection element.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of a conventional electrostatic breakdown prevention device.

FIG. 2 is an equivalent circuit diagram according to FIG. 1;

FIG. 3 is a structural cross-sectional view of a conventional electrostatic breakdown prevention device using the withstand voltage of a junction.

FIG. 4 is a circuit configuration diagram of a conventional electrostatic breakdown prevention device using a hot carrier.

FIG. 5 is a layout diagram of the electrostatic discharge protection device of the present invention.

FIG. 6 is a sectional view taken along the line I-I ′ of FIG. 5;

FIG. 7 is a sectional view taken along the line II-II ′ of FIG. 5;

[Explanation of symbols]

 31 first conductivity type semiconductor substrate 32 first conductivity type impurity region 33, 34 second conductivity type first and second impurity regions 35 second conductivity type well 36 second conductivity type third impurity substrate 37 37a First and second element isolation films 38, 38a Second and fourth conductivity type fourth and fifth impurity regions 39, 39a Second and sixth conductivity type sixth and seventh impurity regions 40 First metal layer 41 Second metal layer 42 Gate line 43 Third metal layer 44 Fourth metal layer 45 Pad

Continued on the front page (72) Inventor Yong Jong Hyo, Republic of Korea, Chuncheonbuk-do-Cheons-Shi-Hungsuk-Guk-Gyeong-dong-Hyun-Shok 1 Apartment 101-907 (56) References JP 7-263633 (JP, A) JP-A-8-293358 (JP, A) JP-A-62-166556 (JP, A) JP-A-5-183107 (JP, A) IEEE Electron Device Letters, vol. ED L-12, no. 1, pp. 21-22 (1991) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/06 H01L 21/331 H01L 29/73

Claims (4)

(57) [Claims] 1. A first conductivity type to the first conductivity type semiconductor substrate
And a first impurity region of the first conductivity type
Between the first and second conductive types formed on both sides thereof.
A bipolar transistor having a pure region and a second impurity region, and a bipolar transistor formed on each side of the bipolar transistor with an isolation film therebetween .
Fourth impurity region and fifth impurity region of two conductivity type,
Has a net things region and the seventh impurity region, and a field transistors respectively formed on both sides of the plane to the bipolar transistor, the fourth impurity region is connected to the sixth impurity regions, the
A first impurity region of a second conductivity type and a first impurity region of the second conductivity type;
A second conductive layer formed at a fixed distance from the impurity region
A gate line formed on the semiconductor substrate between the third impurity region of the mold, and Vss line connected through the contact hole on the fifth impurity regions, a seventh impurity region and the third impurity region, the second And a metal layer connected to the first impurity region of one conductivity type and the pad through a contact hole on the second impurity region of the second conductivity type. Destruction prevention device. 2. The electrostatic discharge protection device according to claim 1, wherein a metal layer is formed above the isolation film of the field transistor, and the metal layer is connected to a pad. 3. The electrostatic discharge protection device according to claim 1, wherein the gate line and the fourth impurity region and the sixth impurity region of each field transistor are connected by a metal layer. 4. A first impurity region of the first conductivity type and a first impurity region .
The lower portion of the entire second conductivity type second impurity region and the second conductive region;
2. The electrostatic discharge protection device according to claim 1, wherein a well of a second conductivity type is formed below a part of the first impurity region of the conductivity type.