JPH07263633A - Static electricity-proof discharge protector of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a device for protecting a device element constituting the internal circuit of a semiconductor device from electrostatic discharge. CONSTITUTION:In an electrostatic discharge protector provided with a P-N-P-N structure, a current by-pass is provided by arranging a MOS field-effect transistor 14 in parallel to a P-N junction 4, which causes an electron avalanche by a reverse bias, a gate electrode 13 of this transistor 14 is connected with an input pad 1 and the P-N-P-N structure is made to operate to the function of an SCR in a low voltage by the switching action of the electrode 13 to enable a device element constituting an internal circuit of a semiconductor device to protect from an ESD breakdown.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection device for protecting a semiconductor device from electrostatic discharge breakdown caused by application of a high voltage to an input terminal or an output terminal of the semiconductor device by electrostatic discharge. is there.

[0002]

2. Description of the Related Art Due to advances in semiconductor manufacturing technology, the degree of integration of semiconductor devices has increased and the operating speed has increased in recent years. At the same time, the miniaturization structure of device elements is required, and the thinning of insulating films such as gate oxide films is being accelerated. Therefore, there is a problem that the device elements are more and more destroyed by electrostatic discharge (hereinafter, abbreviated as ESD).

Here, ESD breakdown means that the high voltage generated by the discharge of static electricity is the IC or LS that constitutes the semiconductor device.
That is, the device element of the internal circuit such as I is damaged and destroyed. Static electricity discharges when a charged human body or equipment contacts the input / output terminals of a semiconductor device that is grounded, or vice versa. It occurs easily even by touching the equipment used for testing.

In the case of a MOS type LSI without any protection measures against this ESD, there is a very small series resistance between the input pad and the internal circuit which actually operates. Therefore, if a large transient voltage is applied to the input terminal, it is also applied to the MOS type LSI as it is, and the device element is destroyed. Therefore, measures to prevent the semiconductor device from ESD damage have become an even more important problem, and various ESD protection circuits have been proposed. One of them is, for example, Japanese Patent Publication No. 5-65061.
There is an integrated circuit provided with a protection device against static electricity disclosed in the publication.

The outline of JP-B-5-65061 will now be described. As shown in FIG. 3, an ESD device having an PNPN structure in series between the input pad 1 and the ground.
20 are connected and configured. In this anti-ESD device 20, an N-type well 46 is defined by diffusion in a lightly-doped P-type semiconductor layer 44, and a lightly-doped N-type semiconductor region is formed to form a PN junction 32. . This N
The P + region 48 is diffused into the mold well 46 to form the PN junction 30. This P + region 48 is connected to pad 1.

A strongly doped N-type impurity N + region 50 is then defined in N-type well 46 to form a resistive connection between pad 1 and N-type well 46.
And allows reverse conduction through PN junction 32 in the presence of an ESD pulse of negative polarity.
Further, a strongly doped N + region 52 is provided in the P-type semiconductor layer 44 outside the N-type well 46, and a PN junction 34 is formed between the N-type well 52 and the N-type well 46. Further, a heavily doped P + region 54 is provided in the P-type semiconductor layer 44 outside the N-type well 46, and a P + resistance region is formed. This P + area
54 is resistively connected by the P-type semiconductor layer 44, and N +
Region 52 and P + region 54 are connected to ground. In this way, the PNPN structure as shown in FIG. 4 is constructed.

Therefore, when a transient ESD pulse having a positive polarity is applied to the pad 1, a current flows from the pad 1 to the P + region 48, and the PN between the N-type well 46 and the P-type semiconductor layer 44. An "electron avalanche" is created at the junction 32, causing a current to flow from the P-type semiconductor layer 44 to the N + region 50 and across the PN junction 34 to ground. That is, the PNPN structure has a reverse blocking three-terminal thyristor SCR (Silicon Controlled Rectifi).
ER), and the SCR is electrically switched on to cause a current to flow from the pad 1 to the ground.

On the contrary, when an ESD pulse having a negative polarity is applied to the pad 1, a current flows from the ground to the P-type semiconductor layer 44 via the P + region 54 and further to the N-type well 46 via the PN junction 32. Moreover, a current flows through the pad 1 through the N + region 50. That is, the PNPN structure acts as a PN diode, and the forward bias of the PN junction 32 causes a current to flow from the pad 1 to the ground.

[0009]

However, in the case of the above-mentioned Japanese Patent Publication No. 65061 / ESD protection device, P
There is a problem with the operating voltage of the NPN structure. That is, in FIG. 3 above, when the ESD pulse having a positive polarity is applied to the pad 12, a voltage exceeding the “electron avalanche” level of the PN junction 32 is required to turn on the SCR. . It is desirable that this voltage be as small as possible so that the semiconductor device to be normally protected is not damaged. This is because if the voltage of the semiconductor device to be protected is higher than the voltage to be damaged, an undesired current will flow to the semiconductor device to be protected before the SCR is sufficiently turned on, and the semiconductor device cannot be sufficiently protected. Because.

By the way, Japanese Patent Publication No. 5-65061 against ESD
In the protective device, as described above, since the PN junction 32 is formed by the lightly doped P-type semiconductor layer 44 and the lightly doped N-type well 46, such a lightly doped semiconductor is formed. When the layers form a PN junction 32, the voltage above the "avalanche" level is relatively high, typically about 20V.

On the other hand, the semiconductor device to be protected is usually
It has a PN junction formed by a high-concentration semiconductor layer and a low-concentration semiconductor layer, and in this case, the voltage that causes "electron avalanche" is about 10 to 15 V, which is smaller than the above voltage. It is common. Therefore, the semiconductor device to be protected causes "electron avalanche", which may lead to destruction when a current flows.

The present invention has been made to solve the above-mentioned problems of the prior art, and provides an electrostatic discharge protection device for a semiconductor device, which makes it possible to operate the SCR at a low operating voltage. The purpose is to do.

[0013]

In order to achieve such an object, the present invention provides a protection device for protecting a semiconductor device from ESD damage, and a MOS device is used as a trigger of the SCR so that the PNPN structure can be quickly operated as the SCR. A field effect transistor is used to set the operating voltage of the SCR to a low voltage with good reproducibility.

That is, the present invention is a device for protecting a semiconductor device against electrostatic discharge by a PNPN structure formed between an input pad and ground, wherein the PN
The MOS type field effect transistor having the N-type region connected to the input pad side of the PN structure as the drain and the N-type region connected to the other ground as the source is the PNPN.
It is an electrostatic discharge protection device for a semiconductor device, characterized in that it is connected in parallel with a PN junction to which a reverse bias is applied in the structure, and the gate electrode of the MOS field effect transistor is connected to an input pad.

[0015]

[Operation] According to the present invention, the MOS field effect transistor is connected in parallel between the PN junctions that cause "electron avalanche" of the PNPN structure, and the gate electrode thereof is connected to the input pad. Is applied to the input pad, the voltage is also applied to the gate electrode, and the trigger of the current flowing through the current path formed by the MOS type field effect transistor causes the P
Since the NPN structure is immediately brought into the conductive state as the SCR, the ESD pulse can be sent to the ground.

[0016]

Embodiments of the present invention will be described in detail below with reference to FIG. FIG. 1 is a sectional view showing an embodiment of the present invention. In the figure, 1 is an input pad provided in a semiconductor device (not shown) to be protected, and 2 is a P-type semiconductor layer. Reference numeral 3 denotes an N-type semiconductor region in which the P-type semiconductor layer 2 is doped with N-type impurities.
Is formed.

Reference numeral 5 is a first P + diffusion layer in which a P-type impurity is doped in the N-type semiconductor region 3, and a second PN junction 6 is formed between the first P + diffusion layer 5 and the N-type semiconductor region 3. Is formed. Reference numeral 7 is a first N + diffusion layer in which N-type impurities are doped in the N-type semiconductor region 3. The first P + diffusion layer 5 and the first N + diffusion layer 7 are connected to the input pad 1 via the wiring 8a. Since the first N + diffusion layer 7 also serves as the drain of a MOS type field effect transistor to be formed later, it is desirable that the first N + diffusion layer 7 is formed over the N type semiconductor region 3 and the P type semiconductor layer 2 as shown in the figure. However, it may be formed so as to be in contact with the N-type semiconductor region 3.

Numeral 9 is another position of the P-type semiconductor layer 2 and the first N
The second P + diffusion layer is formed adjacent to the + diffusion layer 6 and is doped with P-type impurities. Further, 10 is a second N + diffusion layer doped with an N-type impurity formed adjacent to the second P + diffusion layer 9 at another position of the P-type semiconductor layer 2,
The second N + diffusion layer 10 and the P-type semiconductor layer 2 form a third P
The N junction 11 is formed. The second P + diffusion layer 9 and the second N + diffusion layer 10 are connected to the ground via the wiring 8b.

Reference numeral 12 is a gate oxide film deposited between the first N + diffusion layer 7 and the second N + diffusion layer 10, and 13 is a gate electrode formed on the gate oxide film 12. 13
Is connected to the input pad 1 via the wiring 8c. The first N + diffusion layer 7 is the drain and the second N + diffusion layer is the drain.
With 10 as the source, these and the gate electrode 13
N-channel MOS field effect transistor (hereinafter referred to as N-
(Abbreviated as MOSFET) 14 is formed.

As a result, as shown in FIG.
The OSFET 14 is connected in parallel to the first PN junction 4 having the PNPN structure. Here, when a normal power supply voltage is applied to the input pad 1, NM
The OSFET 14 is kept in a sufficiently off state, and the N-MOSFET is previously turned on so that the OSFET 14 is turned on at a voltage lower than a voltage at which the semiconductor device to be protected is damaged.
The thickness of the gate oxide film 12 of 14 is adjusted.

The operation of the ESD protection device of the present invention will now be described. First, the input pad 1 has E having a positive polarity.
When SD pulse is applied, PNPN structure is SCR
At the same time, the N-MOSFET 14 turns on,
Form a current path from input pad 1 to ground. Then, since the current flowing through this current path triggers the SCR to shift the SCR to the ON state, the ESD pulse flows to the ground by using the SCR as a bypass circuit.

On the other hand, the input pad 1 has an ES having a negative polarity.
When the D pulse is applied, the PNPN structure functions as a PN diode, and the first PN junction 4 is forward biased, so that the current flows from the ground to the input pad 1.

[0023]

As described above, the anti-ESD of the present invention.
According to the protection device, the MOS is arranged in parallel with the conventional PNPN structure.
-Type field effect transistor is connected and a current bypass is provided to act as a trigger of SCR.
The SCR can be turned on with a voltage lower than that of the structure, and thus the device element forming the internal circuit of the semiconductor device can be reliably protected from ESD damage.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the PNPN structure of the present invention.

FIG. 3 is a cross-sectional view showing a conventional example.

FIG. 4 is an equivalent circuit diagram of a conventional PNPN structure.

[Description of Reference Signs] 1 input pad 2 P-type semiconductor layer 3 N-type semiconductor region 4 first PN junction 5 first P + diffusion layer 6 second PN junction 7 first N + diffusion layer 8 wiring 9 second P + diffusion layer 10 Second N + diffusion layer 11 Third PN junction 12 Gate oxide film 13 Gate electrode 14 N channel MOS type field effect transistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 27/06 29/74 29/78 H01L 27/06 311 C 29/74 F H 29/78 301 K

Claims (1)

[Claims] 1. A device for protecting a semiconductor device against electrostatic discharge by a PNPN structure formed between an input pad and a ground, comprising an N-type region connected to the input pad side of the PNPN structure. A MOS field effect transistor having a drain and an N type region connected to the other ground as a source is connected in parallel with a PN junction to which a reverse bias of the PNPN structure is applied, and a gate electrode of the MOS field effect transistor. An electrostatic discharge protection device for a semiconductor device, characterized in that the device is connected to an input pad.