KR101006514B1 - A silicon controlled rectifier for protecting the device in a electrostatic discharge - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor controlled rectifiers for electrostatic discharge protection devices used in integrated circuits. will be.

The present invention provides a semiconductor controlled rectifier for an electrostatic discharge protection device operating at high speed by a reduced turn on voltage by reducing the turn on voltage of the semiconductor controlled rectifier through a transistor present therein.

Description

A silicon controlled rectifier for protecting the device in a electrostatic discharge

1 is a view showing a plane of a conventional HHVSCR.

Figure 2a is a cross-sectional view of the HHVSCR applied to the pull down in the HHVSCR of Figure 1;

FIG. 2B is a cross-sectional view of the HHVSCR applied to the pull up in the HHVSCR of FIG. 1; FIG.

3 shows the circuit of FIGS. 2A and 2B;

4 shows a plane of the HHVSCR of the present invention.

5a to 5b are cross-sectional views of the HHVSCR applied to the pull down in the HHVSCR of FIG.

6a to 6b are cross-sectional views of the HHVSCR applied to the pull-up in the HHVSCR of FIG.

7 shows a plane of a wrong layout in the HHVSCR of the present invention.

8 is a cross-sectional view of the HHVSCR applied to the pull-down in the HHVSCR of FIG.

9A to 9C are diagrams showing current-voltage graphs of the HHVSCRs of FIGS. 5A and 8.

-Explanation of symbols for the main parts of the drawings-

214, 266, 301, 519, 569, 622, 682, 819: I / O pad

303, 304: cathode

302: anode

305 trigger

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor controlled rectifiers for electrostatic discharge protection devices used in integrated circuits, and more particularly, to semiconductor controlled rectifiers that perform protection against static discharge in low voltage integrated circuits using semiconductor (or silicon) controlled rectifiers. will be.

Semiconductor integrated circuits are very sensitive to high voltages coming from externally generated static discharges (or static electricity). When a high voltage flows into a chip at a time due to the electrostatic discharge (ESD, hereinafter referred to as ESD), the introduced high voltage destroys the thin film, channels, etc. formed in the integrated circuit, thereby destroying the chip itself. The ESD protection device pre-discharges the instantaneous high voltage or high current into other circuitry on the chip. It is known that a semiconductor (or silicon) controlled rectifier (SCR, hereinafter referred to as SCR) using a PN junction as a protection device against ESD is excellent as a protection device.

In the early integrated circuits, the SCR was a popular device for ESD protection because of the large current consumption per unit area, but the high turn-on voltage (or trigger) of the SCR is increased as the integrated circuit is more densely integrated and the chip size is reduced. Voltage, threshold voltage) and a holding voltage that maintains the turn-on state of the SCR are difficult to apply to recent integrated circuits. In order to reduce the high turn-on voltage of the SCR, the SCR has been improved to the LSCR (Lateral SCR), the MSCR (Modified SCR), and the Low Voltage Triggered SCR (LVTSCR) to maintain a low turn-on voltage. In addition, in recent years, a high holding voltage SCR (HHVSCR) device in which the holding voltage of the SCR is increased has been invented to prevent latch-up through an improved holding voltage than the conventional SCR device.

1 is a view showing a plane of a conventional HHVSCR.

FIG. 2A shows a cross section of the HHVSCR applied to pull down in the HHVSCR of FIG. 1.

As shown in FIG. 2A, the HHVSCR applied to the pull-down includes a p-type semiconductor substrate (P-sub) 201, an n-type well region 202, and a high concentration of p-type (hereinafter P +). Regions 203, 208 and 213 and n-type high concentration (hereinafter referred to as N +) regions 205, 207 and 211, insulating regions 204 and 212, gate electrodes 206 and 209, An input / output pad 214 is provided.

When a large amount of positive charge flows through the input / output pad 214, the HHVSCR performs the PNPN SCR operation by the P + region 210, the well region 202, the semiconductor substrate 201, and the N + region 205. Discharge. In addition, when a large amount of negative charge flows through the input / output pad 214, the HHVSCR performs NP forward diode operation by the N + region 211, the well region 202, the semiconductor substrate 201, and the P + region 213. Discharge the incoming charge.

FIG. 2B illustrates a cross section of the HHVSCR applied to the pull up of FIG. 1.

As shown in FIG. 2B, the HHVSCR applied to the pull up includes a p-type semiconductor substrate 251, an n-type deep well region 252, and an n-type well region 253. ), p-type Pwell region 254, N + regions 255, 260, 262, 265, P + regions 257, 259, 263, insulation regions 256, 264, gate electrodes 258, 261 and an input / output pad 266.

When a large amount of positive charge flows through the input / output pad 266, the HHVSCR discharges charges introduced by the PN forward diode operation by the P + region 263, the well region 254, and the N + region 265. In addition, when a large amount of negative charge flows through the input / output pad 266, the HHVSCR is formed by the N + region 262, the well region 254, the deep well region 252, the well region 253, and the P + region 257. NPNP SCR is operated to discharge the charged charge.

3 is a diagram illustrating both pull-down and pull-up circuits of the HHVSCR shown in FIGS. 2A and 2B.

As shown, the HHVSCR includes an input / output pad 301, BJT transistors B1, B2, B3, and B4, and a separate trigger 305 provided externally.

The trigger 305 includes the MOS transistors M1 and M2. When a large amount of charge flows into the input / output pad 301, the trigger 305 raises the base potential of the BJT transistors B1 and B4 of the HHVSCR to determine the HHVSCR. Reduce the turn on voltage.

Hereinafter, the case will be described in detail by dividing the case when a large amount of charge and a large amount of negative charge flows through the input / output pad 301 of the HHVSCR.

First, when a large amount of positive charge flows through the input / output pad 301, the MOS transistor M2 is turned on by the large amount of charge introduced. The potential of the base of the BJT transistor B4 rises and is turned on by the turned-on MOS transistor M2. As a result, the BJT transistors B3 and B4 perform a PNPN SCR operation to transfer charges introduced into the anode 302 through the input / output pad 301 to the cathode 304 for discharge.

Next, when a large amount of negative charge is introduced through the input / output pad 301, the MOS transistor M1 is turned on by the introduced large amount of charge. The turned-on MOS transistor M1 lowers the potential of the base of the BJT transistor B1 and turns it on. As a result, the BJT transistors B2 and B1 perform NPNP SCR operation to transfer charges introduced into the anode 302 through the input / output pad 301 to the cathode 303 for discharge.

However, conventional HHVSCRs require high turn-on voltages. In order to reduce such a high turn-on voltage, the conventional HHVSCR reduces a turn-on voltage by installing a separate trigger, especially a MOS transistor, externally. However, the conventional semiconductor rectifier controller which reduces the turn-on voltage of the HHVSCR through external means is difficult to secure and maintain the characteristics (discharge ability of the charged charge, linearity, etc.) important for the device for electrostatic discharge. As a result, a problem may arise when the conventional semiconductor control rectifier is integrated in a recent high density and applied to a semiconductor integrated circuit requiring high speed operation.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and provides a semiconductor controlled rectifier for an electrostatic discharge protection device applicable to an integrated circuit of high density integrated and high speed operation.

In particular, the present invention is to ensure protection against ESD with a certain linearity in reducing the turn-on voltage through transistors present therein.

The semiconductor controlled rectifier for an electrostatic discharge protection device according to an embodiment of the present invention includes a first conductive type low concentration semiconductor substrate; A second well-concentrated first well region formed in the semiconductor substrate; First, second, and tenth regions of the first conductivity type high concentration formed in the semiconductor substrate; The second conductive high concentration third, eighth and ninth regions formed in the semiconductor substrate; The second conductive high concentration fourth region formed to overlap the first well region in the semiconductor substrate; The first conductive high concentration fifth and sixth regions formed in the first well region; A seventh region of the second conductivity type high concentration formed in the first well region; A first gate electrode formed on the semiconductor substrate between the third region and the fourth region; A second gate electrode formed on the first well between the fifth region and the sixth region; A third gate electrode formed on the semiconductor substrate between the eighth region and the ninth region; A first insulating region formed in the semiconductor substrate between the first region and the second region; A second insulating region formed in the semiconductor substrate to overlap the first well region between the seventh region and the eighth region; And a third insulating region formed in the semiconductor substrate between the ninth region and the tenth region. The fourth region and the fifth region are bonded to each other, the sixth region and the seventh region are bonded to each other, and the first region is electrically connected to the third region and the first gate electrode. An area is electrically connected to the eighth area and the third gate electrode, the sixth, seventh and ninth areas are electrically connected to a node, and the node is connected to an input / output pad.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 shows a plane of a semiconductor controlled rectifier according to the invention, in particular HHVSCR (High Holding Voltage SCR).

FIG. 5A shows a cross section of the HHVSCR applied to pull down in the HHVSCR of FIG. 4.

As shown in FIG. 5A, the pull-down HHVSCR is a p-type semiconductor substrate (P-sub, 501), an n-type well (Nwell) region 502, and a high concentration of p-type (hereinafter referred to as P +). Regions 503, 505, 509, 511, 518 and n-type high concentration (hereinafter referred to as N +) regions 506, 508, 512, 514, 516, insulating regions 504, 513, 517, Gate electrodes 507, 510, 515 and input / output pads 519 are provided.                     

P + regions 503, 505, 518, N + regions 506, 514, 516 and insulating regions 504, 517 are formed in the semiconductor substrate 501, and P + regions 509, 511 are formed in the well region 502. And N + region 512 is formed. In addition, the N + region 508 and the insulating region 513 are formed in the semiconductor substrate 501 by bonding to the well region 502.

Insulating regions 504, 513, and 517 are formed between two P + regions 503 and 505, two N + regions 512 and 514, and N + region 516 and P + region 518, respectively. Shut off electrically. Three N + regions 506, 508, 512 are formed with three P + regions 505, 509, 511, respectively, by PN junctions.

An NMOS transistor is formed by a gate electrode 507 formed between two N + regions 506 and 508, and a PMOS transistor is formed by a gate electrode 510 formed between two P + regions 509 and 511. In addition, an NMOS transistor is formed by the gate electrode 515 formed between two N + regions 514 and 516. N + region 506, semiconductor substrate 501, well region 502, and N + region 512 form NPN BJT transistors, and P + region 511, well region 502, and semiconductor substrate 501 are PNPs. Form a BJT transistor.

The P + region 503 is electrically connected to the N + region 506 and the gate electrode 507, and the P + region 505 is electrically connected to the N + region 514 and the gate electrode 515. The P + region 511 is electrically connected to the N + regions 512 and 516 and is connected to the input / output pad 519 through the node 520.

Hereinafter, the input / output pad 519 will be described in detail by dividing the case where a large amount of positive charge is introduced and a case where negative charge is introduced.                     

First, when a large amount of positive charge flows through the input / output pad 519, charges introduced through the input / output pad 519 flow into the N + region 516 and the P + region 511. NMOS transistors formed by the N + regions 514 and 516 and the gate electrode 515 are quickly turned on by the charges introduced into the N + region 516, and the turned-on transistors introduce charges into the P + region 505. The charge introduced into the P + region 505 causes the base potential of the BJT transistor 523 formed by the N + region 506, the semiconductor substrate 501, the well region 502, and the N + region 512 to rise, thereby increasing the BJT transistor. Is turned on. That is, when a positive charge flows into the P + region 511 through the input / output pad 519, the HHVSCR is divided into PNPN by the P + region 511, the well region 502, the semiconductor substrate 501, and the N + region 506. It works quickly with SCR to quickly discharge the amount of charge that is introduced.

Next, when a large amount of negative charge flows through the input / output pad 519, that is, when negative charge flows into the N + region 512 through the input / output pad 519, the HHVSCR is N + region 512. Negative electric charges are discharged by the NP forward diode operation by the region 502, the semiconductor substrate 501, and the P + region 518. In addition, when flowing into the N + region 516 through the input / output pad 519, the HHVSCR discharges charges introduced by the NP forward diode operation by the N + region 516, the semiconductor substrate 501, and the P + region 518. Occupy.

FIG. 5B shows a cross section of the HHVSCR applied to the pull down of FIG. 4.

As shown, FIG. 5B is identical in structure to the same components as in FIG. 5A. However, the capacitor C1 and the resistor R1 are further provided. The capacitor C1 connects the node 575 and the input / output pad 569. The resistor R1 connects the terminal 572 electrically connected to the P + region 555, the N + region 564, the gate electrode 565, and the terminal 577 electrically connected to the P + region 568.

Since the operation of FIG. 5B is the same as that of FIG. 5A, a detailed description thereof will be omitted. However, when a large amount of charge flows through the input / output pad 569, the N + region 556, the semiconductor substrate 551, the well region 552, and the N + region are formed by the capacitor C1 and the resistor R1. The base potential of the BJT transistor formed by 562 rises rapidly and quickly turns on. As a result, the HHVSCR performs a PNPN SCR operation rapidly to discharge the charged charges faster than the HHVSCR of FIG. 5A.

FIG. 6A shows a cross section of the HHVSCR applied to the pull up of FIG. 4.

As shown, the HHVSCR includes a p-type semiconductor substrate 601, an n-type deepwell (DNwell) region 602, a p-type pwell region 603, an n-type well region ( 604, 605, N + regions 606, 608, 612, 614, 621, P + regions 609, 611, 615, 617, 619, insulation regions 607, 616, 620, input / output pads 622. do.

The deep well region 602 is formed in the semiconductor substrate 601 to prevent a short circuit between the semiconductor substrate 601 and the well region 603. Well regions 603, 604, and 605 are formed in the deep well region 602, and N + regions 606 and 608, insulating regions 607, and P + regions 609 are formed in the well region 604. P + region 611 is formed to overlap within two well regions 603 and 604. N + regions 612 and 614 are formed in the well region 603, and the P + region 615 is formed to overlap within the two well regions 603 and 605. Insulating regions 616 and 620, P + regions 617 and 619, and N + regions 621 are formed in the well region 605.                     

Insulating regions 607, 616, and 620 are formed between two N + regions 606 and 608, two P + regions 615 and 617, and a P + region 619 and an N + region 621, respectively. Shut off electrically. Three N + regions 608, 612, 614 are formed with PN junctions with three P + regions 609, 611, 615, respectively.

The PMOS transistor is formed by the gate electrode 610 formed between the two P + regions 609 and 611, and the NMOS transistor is formed by the gate electrode 613 formed between the two N + regions 612 and 614. In addition, a PMOS transistor is formed by the gate electrode 618 formed between two P + regions 617 and 619. P + regions 609, well regions 604 and 603, and P + regions 615 form PNP BJT transistors, and N + regions 614 and well regions 603 and 602 form NPN BJT transistors.

The N + region 606 is electrically connected to the P + region 609 and the gate electrode 610, and the N + region 608 is electrically connected to the P + region 617 and the gate electrode 618. The N + region 614 is electrically connected to the P + regions 615 and 619 and connected to the input / output pad 622 through the node 628.

Hereinafter, a case in which a large amount of positive charge is introduced through the input / output pad 622 and a case where negative charge is introduced will be described in detail.

First, when a large amount of positive charge flows in through the input / output pad 622, that is, when charge flows into the P + region 615 through the input / output pad 622, the HHVSCR is a P + region 615 and a well region 605. ), The PN forward diode is operated by the N + region 621 to discharge the positive charge introduced therein. In addition, when charge flows into the P + region 619 through the input / output pad 622, the HHVSCR is negatively introduced by the PN forward diode operation by the P + region 619, the well region 605, and the N + region 621. Discharges the charge.

Next, when a large amount of negative charge flows through the input / output pad 622, charges introduced through the input / output pad 622 flow into the N + region 614 and the P + region 619. The PMOS transistor 625 formed of the P + regions 617 and 619 and the gate electrode 618 is quickly turned on by the charge introduced into the P + region 619, and the turned-on transistor 625 is charged to the N + region 608. Inflow. The charge introduced into the N + region 608 causes the base potential of the BJT transistor formed by the P + region 609, the well regions 604 and 603, and the P + region 615 to drop, thereby turning on the BJT transistor. That is, when negative charge flows into the N + region 614 through the input / output pad 622, the HHVSCR operates quickly as the NPNP SCR by the N + region 614, the well regions 603 and 604, and the P + region 609. Discharges negative charge quickly.

FIG. 6B illustrates a cross section of the HHVSCR applied to the pull up of FIG. 4.

As shown, FIG. 6B has the same structure as the same components as FIG. 6A. However, the capacitor C1 and the resistor R1 are further provided. The capacitor C1 connects the node 688 and the input / output pad 682. The resistor R1 connects the terminal 689 electrically connected to the N + region 668, the P + region 677, and the gate electrode 678, and the terminal 690 electrically connected to the N + region 681.

Since the operation of FIG. 6B is the same as that of FIG. 6A, a detailed description thereof will be omitted. However, when a large amount of negative charge flows through the input / output pad 682, the capacitor C1 and the resistor R1 may be formed by the P + regions 669, the well regions 654 and 653, and the P + regions 675. The base potential of the formed BJT transistor is rapidly lowered to turn on quickly. As a result, the HHVSCR speeds up NPNP SCR operation and discharges the introduced charges faster than the HHVSCR of FIG. 6A.

7 is a view showing a plane of a bad layout (bad layout) when manufacturing the HHVSCR according to the present invention.

8 is a cross-sectional view of the HHVSCR applied to the pull-down of FIG.

As shown, a PMOS transistor is formed by a gate electrode 807 formed between two P + regions 806 and 808, and an NMOS is formed by a gate electrode 810 formed between two N + regions 809 and 811. Form a transistor. In addition, an NMOS transistor is formed by the gate electrode 815 formed between two N + regions 814 and 816. PNP BJT transistors are formed from the P + region 806, the well region 802, and the semiconductor substrate 801, and NPN BJT transistors are formed from the well region 802, the semiconductor substrate 801, and the N + region 811. do.

The operation of the HHVSCR shown in FIG. 8 is the same as the operation of the HHVSCR shown in FIG. 5A. That is, when a large amount of positive charge flows through the input / output pad 819, the HHVSCR performs a PNPN SCR operation by the P + region 806, the well region 802, the semiconductor substrate 801, and the N + region 811. Discharge the incoming charge. However, when the charge is discharged through the PNPN SCR operation, the discharge of the charge occurs in the well region 802 and the semiconductor substrate 801 which are inside the HHVSCR. As a result, the HHVSCR is difficult to secure important characteristics for the device for electrostatic discharge (discharge ability of the charged charge, the utility of the protective device, etc.).

9A to 9C are graphs of current-voltage comparing the discharge capability of the introduced charges and the effectiveness of the protection device when the HHVSCR is fabricated by the layout of FIGS. 5A and 8.

FIG. 9A is a current-voltage graph showing the discharge capability of charges introduced from the outside by the HHVSCR when the HHVSCR is manufactured with FIGS. 5A and 8.

As shown in FIG. 9A, a graph 901 in the case of producing HHVSCR by laying out through FIG. 5A shows a larger amount of current than the graph 902 in the case of producing HHVSCR by laying out through FIG. 8. . That is, the HHVSCR according to FIG. 5A has a greater charge discharge capability than the HHVSCR according to FIG. 8.

9B and 9C are current-voltage graphs showing the discharge capability of charges introduced from the outside when the HHVSCR linearly increases the width of the HHVSCR fabricated through FIGS. 5A and 8.

As shown in FIG. 9B, the discharge capability of the HHVSCR is doubled by doubling the width of the HHVSCR through the graph 911 when the width of the HHVSCR manufactured through FIG. 5A is 50 μm and the graph 912 when the width is 50 μm. Almost doubled.

On the other hand, as shown in Figure 9c, even if the width of the HHHVSCR produced through Figure 8 50㎛ 921 and 100㎛ when the width of the HHVSCR through the graph 922, even if the width of the HHVSCR doubled The charge capacity is almost unchanged.

That is, when the HHVSCR is manufactured by laying out through FIG. 5A, the discharge capability linearly changes with respect to the width change of the HHVSCR.

10 shows a cross section of an HHVSCR showing yet another embodiment according to the present invention.

As shown, the HHVSCR has the same components and the same structure as the HHVSCR of FIG. 5A. However, p-type low concentration (P−) regions 1011, 1012, 1015, 1016, and 1020 are formed by joining the P + regions 1001, 1002, 1005, 1006, and 1010. Further, n-type low concentration (N-) regions 1013, 1014, 1017, 1018, and 1019 are formed by joining the N + regions 1003, 1004, 1007, 1008, and 1009.

The HHVSCR has the same effect through the same operation as the HHVSCR of FIG. 5A. (Detailed description of the operation of the HHVSCR shown in FIG. 10 is omitted.)

Next, after examining the difference between FIG. 5A, FIG. 2A, and FIG. 8, the superiority of the present invention will be described. FIG.

First, since the conventional HHVSCR shown in FIG. 2A requires a high turn-on voltage, a separate trigger, particularly a MOS transistor, is installed outside to apply the semiconductor integrated circuit to reduce the high turn-on voltage. However, since the HHHVSCR of the present invention shown in FIG. 5A fabricates a MOS transistor and is applied to a semiconductor integrated circuit, the HHHVSCR of the present invention can operate at a high speed through a reduced turn-on voltage, and performs an improved protection against static discharge.

Next, in the HHVSCR illustrated in FIG. 8, a sub tap is positioned at an intermediate position of the HHVSCR. In contrast, in the HHVSCR illustrated in FIG. 5A, a sub tab is positioned at an edge of the HHVSCR. As a result, as shown in Figs. 9A to 9C, the HHVSCR shown in Fig. 5A can secure important characteristics of SCR (discharge capacity of inflowed charge, linearity). In addition, as the number of sub taps increases, securing of characteristics of the SCR increases.

As can be seen above, when the semiconductor controlled rectifier for an electrostatic discharge protection device according to the present invention is used, the semiconductor controlled rectifier can be operated at high speed by reducing the turn-on voltage of the semiconductor controlled rectifier. Such an apparatus of the present invention is applicable to next generation semiconductor integrated circuits requiring high speed operation.

Claims (7)

In a semiconductor controlled rectifier for an electrostatic discharge protection device, A first conductivity type low concentration semiconductor substrate; A second well-concentrated first well region formed in the semiconductor substrate; First, second, and third regions of the first conductivity type high concentration formed in the semiconductor substrate; The second conductive high concentration fourth, fifth and sixth regions formed in the semiconductor substrate; A seventh region of the second conductivity type high concentration formed to overlap the first well region in the semiconductor substrate; The eighth and ninth regions of the first conductivity type high concentration formed in the first well region; The second conductivity type high concentration tenth region formed in the first well region; A first gate electrode formed on the semiconductor substrate between the fourth region and the seventh region; A second gate electrode formed on the first well between the eighth and ninth regions; A third gate electrode formed on the semiconductor substrate between the fifth region and the sixth region; A first insulating region formed in the semiconductor substrate between the first region and the second region; A second insulating region formed in the semiconductor substrate to overlap with the first well region between the tenth and fifth regions; A third insulating region formed in the semiconductor substrate between the sixth region and the third region, The second region and the fourth region are bonded; The seventh region and the eighth region are joined; The ninth region and the tenth region are joined; The first region is electrically connected to the fourth region and the first gate electrode, The second region is electrically connected to the fifth region and the third gate electrode, The ninth, tenth and sixth regions are electrically connected to the node, And the node is connected to an input / output pad. According to claim 1, The first gate electrode, the fourth region and the seventh region form a first MOS transistor, The second gate electrode, the eighth region and the ninth region form a second MOS transistor; And the third gate electrode, the fifth region and the sixth region form a third MOS transistor. According to claim 1, And when the positive voltage flows through the input / output pad, the internal potential of the semiconductor substrate is increased by the third MOS transistor to discharge the charge introduced at a high speed. According to claim 1, A capacitor connecting the input / output pad and the node; Further comprising a resistor for electrically connecting the third gate electrode and the third region, And a positive voltage flows through the input / output pad to discharge charges introduced at a higher speed. According to claim 1, Inserting a second well region of the second conductivity type between the semiconductor substrate and the first to seventh regions, the first to third insulating regions, and the well region; Inserting a third well region of higher conductivity than the second well region between the second well region and the first, second, fourth, seventh region, and the first insulating region, Inserting the same fourth well region as the third well region between the second well region, the second and third insulating regions, and the fifth, sixth and third regions, The first to third regions and the eighth and ninth regions are replaced with the second conductive type high concentration region, When the first well region, the fourth to seventh region and the tenth region are replaced with the first conductivity type high concentration region, And a negative voltage is introduced through the input / output pad to discharge an electric charge introduced at a high speed by the internal potential of the semiconductor substrate being lowered by the third MOS transistor. The method according to claim 1 or 5 above, A capacitor connecting the input / output pad and the node; Further comprising a resistor for electrically connecting the third gate electrode and the third region, And a negative voltage flows through the input / output pad to discharge charges introduced at a higher speed. According to claim 1, And said first conductivity type is p-type, and said second conductivity type is n-type.

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