KR100996173B1 - Electrostatic discharge protection circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the design of a protection circuit for discharging static electricity flowing into an input / output pad from a semiconductor circuit. The invention relates to an electrostatic discharge circuit of a semiconductor circuit which is highly integrated and operates at high speed by providing a structure that can be reduced.

Description

Electrostatic Discharge Protection Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to an electrostatic discharge circuit having a low SCR trigger voltage comprised of SCR elements.

In general, SCR (Silicon Controlled Rectifier) is more than twice the current discharge capacity per unit area than bipolar transistors, and thus, it is possible to implement an electrostatic discharge circuit more efficiently than using a bipolar transistor with a small junction area.

1 is a cross-sectional view of a basic PNPN structure according to an embodiment of the prior art.

Referring to FIG. 1, N wells in which low concentrations of impurities are implanted are formed in a predetermined region of a P-type substrate, and high concentration first and second junction regions 100 and 102 are formed in the N wells, respectively. . The third junction region 110 and the fourth junction region 112 are formed in predetermined regions of the P-type substrate other than the N well.

The first junction region 100 and the fourth junction region 112 are doped with P-type impurities having a higher concentration than the P-type substrate, and the second junction region 102 and the third junction region 110 have a higher concentration than the N well. Doping with N-type impurities.

Such an electrostatic discharge circuit is shown in FIG. 2 as an equivalent circuit.

Referring to Figures 1 and 2 will be described the principle that the SCR is formed.

In the electrostatic discharge circuit shown in FIG. 1, when static electricity is applied to the input / output pad 14, breakdown occurs in the N well, thereby causing a PNP type bipolar transistor.

(Q1) is opened, through which the carrier is injected into the P-type substrate, and when the injected carrier is injected into the P-type substrate, the NPN type bipolar transistor Q2 is operated by the forward bias between the emitter-base, and finally The PNPN path is formed so that carriers applied by the static electricity exit the ground voltage pad 12.

Hereinafter, the present invention will be described in detail with reference to FIG. 2.

Rnwell is a parasitic resistance of the N well, Rpwell is a parasitic resistance of the P-type substrate, and Q1 represents a PNP type bipolar transistor.

In the PNP type bipolar transistor Q1, the first junction region 100 connected to the input / output pad 14 is an emitter, the N well is a base, and the P type substrate is a collector. (Collector).

In the NPN type bipolar transistor Q2, the third junction region 110 connected to the ground voltage pad 12 is an emitter, the P type substrate is a base, and the N well is a collector. Collector).

If the PNP type bipolar transistor Q1 and the NPN type bipolar transistor Q2 operate in a forward active region, if only a slight current flow occurs inside the SCR, the collector and base may be caused by a positive feedback operation. The current will gradually increase.

This increases the base current of the PNP type bipolar transistor Q1 when the collector current of the NPN type bipolar transistor Q2 flows. As a result, the collector current of the PNP type bipolar transistor Q1 is increased to increase the base current of the NPN type bipolar transistor Q2, thereby causing a positive feedback phenomenon to increase the collector current of the NPN type bipolar transistor Q2.

Through this, excessive current caused by static electricity can escape through the SCR before destroying the internal circuit. In the structure shown in FIG. 1, the trigger point for operating the SCR when the stress caused by static electricity is an NPN type bipolar transistor (Q2). Is the point at which collector current starts to flow.

The trigger voltage in the electrostatic discharge circuit using the basic SCR as described above is the breakdown voltage of the PN junction between the N well and the P-type substrate, which has a fairly high voltage level. The high trigger voltage does not affect the static electricity protection element, but may cause the gate insulating film or the junction of the internal circuit to be destroyed.

Therefore, to solve this problem, the trigger voltage of the SCR should be low. In order to lower the trigger voltage of an electrostatic discharge SCR, an NMOS or a capacitor is added to the SCR. However, in this case, there is a problem that the layout area is increased, which is an obstacle to high integration of the semiconductor circuit.

The present invention provides a circuit for discharging static electricity to protect the semiconductor internal circuit from static electricity flowing into the input / output pad.

The present invention also provides an electrostatic discharge circuit having a small layout area and operating an SCR at a low trigger voltage to provide an electrostatic discharge path.

An electrostatic discharge protection circuit having a silicon controlled rectifier driven with a low trigger voltage includes a first junction region of a first impurity type, a first device isolation film, a second junction region of a second impurity type, a first gate and a second impurity type. A first impurity type substrate formed by sequentially contacting the third junction region; And a fourth junction region of a first impurity type, a second gate, a fifth junction region of a first impurity type, a second device isolation layer, and a sixth junction region of a first impurity type are sequentially contacted with each other. And a second impurity type well formed thereon, wherein the fourth junction region is electrically connected to an input / output pad, and the second gate and the sixth junction region are electrically connected to a power supply voltage pad. The first junction region, the first gate and the third junction region may be electrically connected to a ground voltage pad, and the second junction region and the fifth junction region may be electrically connected to each other.

The first impurity type is characterized in that the P-type impurities, the second impurity type is characterized in that the N-type impurities.

The first device isolation layer and the second device isolation layer may be formed of an STI structure or a gate poly.

Preferably, the second junction region and the fifth junction region are formed of metal lines to be electrically connected to each other.

In another embodiment, a first junction region of a first impurity type, a first device isolation layer, a second junction region of a second impurity type, a first gate and a third junction region of a second impurity type are sequentially formed in contact with each other. An impurity type substrate; And a fourth junction region of a first impurity type, a second gate, a fifth junction region of a first impurity type, a second device isolation layer, and a sixth junction region of a first impurity type are sequentially contacted with each other. And a second impurity type well formed thereon, wherein the fourth junction region, the second gate, and the sixth junction region are electrically connected to an input / output pad, and the first junction region and the first junction region. The first gate and the third junction region are electrically connected to the ground voltage pad, and the second junction region and the fifth junction region are electrically connected to each other.

The first impurity type is characterized in that the P-type impurities, the second impurity type is characterized in that the N-type impurities.

The first device isolation layer and the second device isolation layer may be formed of an STI structure or a gate poly.

The layout of an electrostatic discharge protection circuit having a silicon-controlled rectifier driven with a low trigger voltage includes a first MOS transistor region and a first junction region separated from the element on a P-type substrate, and a well formed on the P-type substrate. A second MOS transistor region and a second junction region separated from the element are disposed, and the first junction region and the second junction region are formed to face each other, and to supply a power voltage to the second MOS transistor region. A power supply voltage pattern is formed to electrically connect a gate and the second junction region to a power supply voltage pad. The gate, the first voltage terminal, and the first junction region of the first MOS transistor region are grounded to supply a ground voltage. A ground voltage pattern electrically connected to the voltage pad is formed, and the first voltage terminal and the first MOS transistor of the second MOS transistor region. A first conductive pattern electrically connected to the second voltage terminal of the station is formed, wherein the second conductive pattern for connecting the second end and the voltage input / output pad of the second MOS transistor region is formed.

The first MOS transistor region is formed of NMOS, the second MOS transistor region is formed of PMOS, and the first conductive pattern is formed of metal line.

According to another embodiment of the present invention, a first MOS transistor region and a first junction region separated from the element are disposed on the P-type substrate, and the second MOS transistor region and the element separated from the second MOS transistor region are formed in a well formed on the P-type substrate. Two junction regions are disposed, and the first junction region and the second junction region are formed to face each other, and the gate, the first voltage terminal, and the first junction region of the first MOS transistor region are supplied to supply a ground voltage. A ground voltage pattern is formed to be electrically connected to the ground voltage pad, and a first conductive pattern is formed to electrically connect the first voltage terminal of the second MOS transistor region to the second voltage terminal of the first MOS transistor region. A second conductive pattern for connecting the second voltage terminal of the second MOS transistor region, the gate of the second MOS transistor region, and the second junction region and an input / output pad; Is formed.

The first MOS transistor region includes an NMOS transistor, the second MOS transistor region includes a PMOS transistor, and the first conductive pattern includes a metal line.

According to the present invention, it is possible to design a highly integrated, high performance semiconductor circuit by having a low SCR trigger voltage without increasing a large layout area.

The present invention proposes an electrostatic discharge circuit having an SCR with a low trigger voltage used as an electrostatic protection element.

3 illustrates a preferred embodiment of the present invention.

3 illustrates a power supply voltage pad 10, a ground voltage pad 12, an input / output pad 14, a metal line 16, a first device isolation film S31, a second device isolation film S32, and the like. P-type substrate, N well, first junction area

300, the second junction region 302, the third junction region 304, the fourth junction region 310, and the fifth junction region 312.

The sixth junction region 314, the first gate G31, and the second gate G32 are formed.

The first junction region 300, the fourth junction region 310, and the fifth junction region 312 are doped with P-type impurities having a higher concentration than the P-type substrate, and the second junction region 302 and the third junction region ( 304), 6th junction area

314 is doped with a higher concentration of N-type impurities than the N well.

The first junction region 300, the first device isolation layer S31, the second junction region 302, the first gate G31, and the third junction region 304 are sequentially formed on the P-type substrate.

The fourth junction region 310 and the second gate in the N well formed in the predetermined region of the P-type substrate.

(G32), the fifth junction region 312, the second device isolation film S32, and the sixth junction region 314 are sequentially formed in contact with each other.

Preferably, the first junction region 300 and the sixth junction region 314 are adjacent to each other.

Do.

The first junction region 300, the first gate G31, and the third junction region 304 are electrically connected to the ground voltage pad 12, and the second junction region 302 is the fifth junction region 312. And are electrically connected to each other by the metal line 16.

The first junction region 300 and the second junction region 302 are separated by the first device isolation layer S31, and the fifth junction region 312 and the sixth junction region 314 are the second device isolation layer S32. Separated by).

In some cases, the first junction region 300 and the sixth junction region 314 may be designed not to be adjacent to each other. If the first junction region 300 and the sixth junction region 314 are not adjacent to each other, the first device isolation layer S31 may be formed between the first junction region 300 and the third junction region 304. Alternatively, a second device isolation layer S32 may be formed between the fourth junction region 310 and the sixth junction region 314.

In this way, the arrangement of the first junction region 300 and the sixth junction region 314 is the same as the invention and the technical idea of the invention shown in FIG. Those skilled in the art can be easily implemented through the embodiment of Figure 3, a detailed description thereof will be omitted.

The operation principle will be described with reference to FIG. 3.

First, the case of electrostatic discharge with the power voltage pad 10 will be described.

When positive static electricity flows into the input / output pad 14, a forward bias is applied to the PN diode formed between the fourth junction region 310 and the sixth junction region 314 so that the static electricity is applied to the power supply voltage pad 10. Discharged.

Next, a case in which static electricity is discharged to the ground voltage pad 12 will be described.

When positive static electricity flows into the input / output pad 14, an electrostatic discharge path is formed to the ground voltage pad 12.

In more detail, since a forward bias is applied to the PN diode formed between the fourth junction region 310 and the N well, an electrostatic discharge path is formed, and the voltage level of the N well increases.

When the voltage level of the N well rises, since a reverse bias is applied to the PN diode formed between the N well and the fifth junction region 312, a first breakdown occurs and thus static electricity is generated from the N well to the fifth junction region 312. Discharge path is formed.

Since the fifth junction region 312 is connected to the second junction region 302 by the metal line 16, the voltage level of the second junction region 302 increases.

When the voltage level of the second junction region 302 rises, since a reverse bias is applied to the PN diode formed between the second junction region 302 and the P-type substrate, a second breakdown occurs and the second junction region 302 ), An electrostatic discharge path is formed into the P-type substrate, and the voltage level of the P-type substrate increases.

When the voltage level of the P-type substrate increases, a forward bias is applied to the PN diode formed between the P-type substrate and the third junction region 304, so that an electrostatic discharge path is formed of the ground voltage pad 12.

3 allows the SCR to operate at a lower trigger voltage than in the prior art.

In more detail, when an electrostatic discharge path is formed between the input / output pad 14 and the ground voltage pad 12, a first breakdown occurs between the N well and the fifth junction region 312. A second breakdown occurs between the two junction regions 302 and the P-type substrate.

The voltage levels of the first breakdown and the second breakdown become the trigger voltage levels of the SCR operation operating in the forward active region between the parasitic bipolar transistors.

N-type bipolar transistor occurs due to first breakdown and second breakdown

When the collector current of Q2 flows, the base current of the PNP type bipolar transistor Q1 is increased. As a result, the current of the collector of the PNP type bipolar transistor Q1 is increased to increase the base current of the NPN type bipolar transistor Q2, thereby causing a positive feedback phenomenon to increase the collector current of the NPN type bipolar transistor Q2. The SCR operates at low trigger voltage levels.

Since the junction area of the second junction region 302 and the fifth junction region 312 is small, the voltages of the first breakdown and the second breakdown are lower than the third breakdown described later.

If the second junction region 302 and the fifth junction region 312 are not connected to the metal line 16, the SCR operates at a conventional trigger voltage level.

In this case, the reverse bias is applied to the PN diode formed between the N well and the P-type substrate so that the voltage level when the third breakdown occurs is the trigger voltage.

Since the N well has a large junction area, the voltage of the third breakdown is higher than the voltages of the first and second breakdown described above.

The embodiment of FIG. 3 connects the second junction region 302 and the fifth junction region 312 to the metal line 16 to provide a path having a low breakdown voltage, thereby lowering the trigger voltage for the SCR to operate. give.

Accordingly, the SCR operates at a low trigger voltage in response to the static electricity input to the input / output pad 14 to provide an electrostatic discharge path.

4 shows a planar layout structure of an SCR for the embodiment of FIG. 3.

A plan layout structure of a specific SCR will be described with reference to FIG. 4.

The NMOS transistor region T41 and the first junction region 400 separated from the element are disposed on the P-type substrate.

A PMOS transistor region T42 and a second junction region 402 separated from the element are disposed in an N well formed on the P-type substrate.

The first junction region 400 and the second junction region 402 are formed to face each other,

In order to supply a ground voltage, a ground voltage pattern 410 is formed to electrically connect the gate G42 and the first voltage terminal of the NMOS transistor region T41 and the first junction region 400 with a ground voltage pad. Become,

In order to supply a power supply voltage, a power supply voltage pattern 412 electrically connecting the gate G42 and the second junction region 402 of the PMOS transistor region T42 to a power supply voltage pad is formed.

A first conductive pattern 414 is formed to electrically connect the second voltage terminal of the NMOS transistor region T41 and the second voltage terminal of the PMOS transistor region T2.

A second conductive pattern 416 for connecting the first voltage terminal and the input / output pad of the PMOS transistor region T42 is laid out.

The NMOS transistor region T41 and the PMOS transistor region T42 are formed to face each other.

5 presents another embodiment of the present invention.

5 illustrates a ground voltage pad 12, an input / output pad 14, a metal line 16, a first device isolation layer S51, a second device isolation layer S52, a P-type substrate, an N well, First junction region 500, second junction region 502, third junction region 504, fourth junction region 510, fifth junction region 512, sixth junction region

514, a first gate G51, and a second gate G52 are formed.

In FIG. 5, the second gate G52 and the sixth junction region 514 are connected to the input / output pad 14 because the power voltage pads are in a floating state compared to FIG. 3.

Looking at the operation process with reference to Figure 5 as follows.

When positive static electricity flows into the input / output pad 14, an electrostatic discharge path is formed to the ground voltage pad 12.

In more detail, since a forward bias is applied to the PN diode formed between the fourth junction region 510 and the N well, an electrostatic discharge path is formed, and the voltage level of the N well is increased.

When the voltage level of the N well rises, since a reverse bias is applied to the PN diode formed between the N well and the fifth junction region 512, a first breakdown occurs to form an electrostatic discharge path, and the fifth junction region 512. ), The voltage level rises.

Since the fifth junction region 512 is connected to the second junction region 502 through the metal line 16, the voltage level of the second junction region 502 increases.

When the voltage level of the second junction region 502 rises, since a reverse bias is applied to the PN diode formed between the second junction region 502 and the P-type substrate, a second breakdown occurs to form an electrostatic discharge path. The voltage level of the P-type substrate rises.

When the voltage level of the P-type substrate rises, forward bias is applied to the PN diode formed between the P-type substrate and the third junction region 504 and thus is electrostatically discharged to the ground voltage pad 12.

5 provides a lower trigger voltage than the trigger voltage for a conventional SCR operation.

In more detail, when an electrostatic discharge path is formed between the input / output pad 14 and the ground voltage pad 12, a first breakdown occurs between the N well and the fifth junction region 512. A second breakdown occurs between the fifth junction region 512 and the P-type substrate.

The voltages of the first breakdown and the second breakdown become trigger voltages of the SCR operation of the parasitic bipolar transistor. Since the junction area of the fifth junction region 512 and the second junction region 502 is small, the voltages of the first breakdown and the second breakdown are the third breakdown described later.

Lower voltage level.

If the second junction region 502 and the fifth junction region 512 are not connected to the metal line 16, the parasitic bipolar transistor performs a conventional SCR operation.

In this case, a third breakdown occurs between the N well and the P-type substrate, and since the N well has a large junction area, the voltage of the third breakdown is higher than that of the first and second breakdown voltages described above. The level is high.

5, the second junction region 502 and the fifth junction region 512 are connected to the metal line 16 to provide a path having a low breakdown voltage, thereby lowering the trigger voltage for the SCR operation.

Therefore, in response to the static electricity applied to the input / output pad 14, the SCR operation is performed faster to provide an electrostatic discharge path.

6 shows a planar layout structure for the embodiment of FIG. 5.

The NMOS transistor region T61 and the first junction region 600 separated from each other are disposed on the P-type substrate.

A PMOS transistor region T62 and a second junction region 602 separated from the element are disposed in an N well formed on the P-type substrate.

The first junction region 600 and the second junction region 602 are formed to face each other,

In order to supply a ground voltage, a ground voltage pattern 610 electrically connecting the gate G62 and the first voltage terminal of the NMOS transistor region T61 and the first junction region 600 with a ground voltage pad is formed. Become,

A first conductive pattern 612 is formed to electrically connect the second voltage terminal of the NMOS transistor region T61 and the second voltage terminal of the PMOS transistor region T62.

A second conductive pattern for connecting an input / output pad of the gate G62 of the PMOS transistor region T62, the second junction region 602, and the first voltage terminal of the former and the PMOS transistor region T2. Layout 614 is formed.

The NMOS transistor region T61 and the PMOS transistor region T62 are laid out side by side.

The first conductive pattern 614 is laid out to be formed of metal lines.

Referring to FIG. 7, it can be seen that the embodiment of FIG. 5 reduces the trigger voltage by about 7 volts compared to the conventional SCR structure.

However, in the embodiment of FIG. 5, since the N well bias may be shaken during normal operation, leakage current may occur. On the other hand, in the embodiment of FIG. 3, since the gate G31 and the N well of the PMOS transistor are connected to the power supply voltage pad 10, no leakage current occurs during normal operation.

Therefore, the SCR structure shown in FIG. 3 has a lower trigger voltage than the conventional SCR structure, and no leakage current is generated during normal operation.

1 is a cross-sectional view of a conventional SCR

2 is a circuit diagram of a conventional SCR

3 is a cross-sectional view of the SCR of the present invention

4 is a plan layout diagram of an SCR of the present invention;

5 is another embodiment of FIG.

6 is a plan layout diagram of FIG.

7 is simulation of trigger voltage comparison

Claims (17)

A first impurity type substrate formed by sequentially contacting a first junction region of a first impurity type, a first device isolation film, a second junction region of a second impurity type, and a first gate and a third junction region of a second impurity type ; And A fourth junction region of a first impurity type, a second gate, a fifth junction region of a first impurity type, a second device isolation layer, and a sixth junction region of a first impurity type are sequentially formed in contact with each other. And a second impurity type well formed in the The fourth junction region is electrically connected to an input / output pad, The second gate and the sixth junction region are electrically connected to a power supply voltage pad, The first junction region, the first gate and the third junction region are electrically connected to a ground voltage pad, And the second junction region and the fifth junction region are electrically connected to each other. The method of claim 1, The first impurity type is an electrostatic discharge device, characterized in that the P-type impurities.  The method of claim 1, And the second impurity type is an N-type impurity. The method of claim 1, The first device isolation film and the second device isolation film is an electrostatic discharge device, characterized in that consisting of STI structure or gate poly. The method of claim 1, And the second junction region and the fifth junction region are formed of metal lines to be electrically connected to each other. A first impurity type substrate formed by sequentially contacting a first junction region of a first impurity type, a first device isolation film, a second junction region of a second impurity type, and a first gate and a third junction region of a second impurity type ; And A fourth junction region of a first impurity type, a second gate, a fifth junction region of a first impurity type, a second device isolation layer, and a sixth junction region of a first impurity type are sequentially formed in contact with each other. And a second impurity type well formed in the The fourth junction region, the second gate, and the sixth junction region are electrically connected to an input / output pad, The first junction region, the first gate and the third junction region are electrically connected to a ground voltage pad, And the second junction region and the fifth junction region are electrically connected to each other. The method of claim 6, And wherein the first impurity type is a p-type impurity. The method of claim 6, And the second impurity type is an N-type impurity. The method of claim 6, The first device isolation film and the second device isolation film is an electrostatic discharge device, characterized in that consisting of STI structure or gate poly. A first MOS transistor region and a first junction region separated from the element are disposed on the P-type substrate, A second MOS transistor region and a second junction region separated from the element are disposed in a well formed on the P-type substrate, The first junction region and the second junction region are formed to face each other, In order to supply a power supply voltage, a power supply voltage pattern is formed to electrically connect the gate of the second MOS transistor region and the second junction region to a power supply voltage pad. In order to supply a ground voltage, a ground voltage pattern electrically connecting the gate and the first voltage terminal of the first MOS transistor region and the first junction region to a ground voltage pad is formed. A first conductive pattern is formed to electrically connect the first voltage terminal of the second MOS transistor region to the second voltage terminal of the first MOS transistor region. And a second conductive pattern for connecting the second voltage terminal and the input / output pad of the second MOS transistor region. The method of claim 10, And the first MOS transistor region is formed of an NMOS transistor. The method of claim 10, And the second MOS transistor region is formed of a PMOS transistor. The method of claim 10, And the first conductive pattern is formed of metal lines. The first MOS transistor region and the first junction region separated from the element is disposed on the P-type substrate, A second MOS transistor region and a second junction region separated from the element are disposed in a well formed on the P-type substrate, The first junction region and the second junction region are formed to face each other, In order to supply a ground voltage, a ground voltage pattern electrically connecting the gate and the first voltage terminal of the first MOS transistor region and the first junction region to a ground voltage pad is formed. A first conductive pattern is formed to electrically connect the first voltage terminal of the second MOS transistor region to the second voltage terminal of the first MOS transistor region. And a second conductive pattern for connecting the second voltage terminal of the second MOS transistor region, the gate of the second MOS transistor region, and the second junction region and an input / output pad. Way. The method of claim 14, And the first MOS transistor region is formed of an NMOS transistor. The method of claim 14, And the second MOS transistor region is formed of a PMOS transistor. 15. The method of claim 14, And the first conductive pattern is formed of metal lines.

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