CN102760731B - Electrostatic protection structure - Google Patents

Electrostatic protection structure Download PDF

Info

Publication number
CN102760731B
CN102760731B CN201110103518.4A CN201110103518A CN102760731B CN 102760731 B CN102760731 B CN 102760731B CN 201110103518 A CN201110103518 A CN 201110103518A CN 102760731 B CN102760731 B CN 102760731B
Authority
CN
China
Prior art keywords
diffusion region
well
diffusion
regions
region
Prior art date
Application number
CN201110103518.4A
Other languages
Chinese (zh)
Other versions
CN102760731A (en
Inventor
苏庆
Original Assignee
上海华虹宏力半导体制造有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海华虹宏力半导体制造有限公司 filed Critical 上海华虹宏力半导体制造有限公司
Priority to CN201110103518.4A priority Critical patent/CN102760731B/en
Publication of CN102760731A publication Critical patent/CN102760731A/en
Application granted granted Critical
Publication of CN102760731B publication Critical patent/CN102760731B/en

Links

Abstract

本发明公开了一种静电保护结构,包含一N阱,一P阱;N阱中形成有第一P+扩散区、第二P+扩散区、第一N+扩散区、第二N+扩散区,第一P+扩散区、第二P+扩散区构成一PMOS管;N阱中的二P+扩散区之一、二N+扩散区之一同所述PMOS管的栅极短接用于接静电端;P阱中形成有第三P+扩散区、第四P+扩散区、第三N+扩散区、第四N+扩散区,第三N+扩散区、第四N+扩散区构成一NMOS管;P阱中的二N+扩散区之一、二P+扩散区之一同所述NMOS管的栅极短接用于接地端;N阱中的另外一个N+扩散区同P阱中的另外一个N+扩散区短接;N阱中的另外一个P+扩散区同P阱中的另外一个P+扩散区短接。 The present invention discloses an electrostatic protection structure comprising an N-well, a P-well; N-well formed in a first P + diffusion region, a second P + diffusion region, a first N + diffusion region, a second N + diffusion regions, a first P + diffusion region, a second P + diffusion region constituting a PMOS transistor; one gate shorting one of the two N-well P + diffusion region, with the two N + diffusion region of said PMOS transistor for receiving an electrostatic end; P-well is formed a third P + diffusion region, the fourth P + diffusion region, a third N + diffusion region, a fourth N + diffusion region, a third N + diffusion region, a fourth N + diffusion regions form a NMOS transistor; two N + diffusion region of the P-well the gate shorting a, one of two P + diffusion region with the NMOS transistor for grounding terminal; another N + diffusion region in the N well with P-well as another N + diffusion region short; the other N wells P + diffusion region with a P-well of the P + diffusion region further short. 本发明能方便有效地调节静电保护的触发电压,能有效的避免拴锁效应,静电放电能力强。 The present invention can easily and effectively adjust the trigger voltage of the electrostatic protection, can effectively prevent latch effects, strong electrostatic discharge capability.

Description

静电保护结构 Electrostatic protection structure

技术领域 FIELD

[0001 ] 本发明涉及半导体静电保护技术,特别涉及一种静电保护结构。 [0001] The present invention relates to semiconductor ESD protection technology, particularly relates to an electrostatic protection structure.

背景技术 Background technique

[0002] 作为静电保护结构,硅控整流器(SCR)中寄生的三极管比金属-氧化物-半导体场效应管(MOSFET)有着更强的静电泄放能力,一般硅控整流器的静电泄放能力是MOSFET的5〜7倍。 [0002] As the electrostatic protection structure, a silicon controlled rectifier (SCR) of the parasitic transistor than the metal - oxide - semiconductor field effect transistor (MOSFET) has a stronger electrostatic discharge capacity, the electrostatic discharge capacity is generally SCR 5 ~ 7 times the MOSFET. 图1所示为现有高触发电压硅控整流器的剖面结构示意图。 A schematic cross-sectional structure shown in FIG. HVSCR 1 is a conventional high trigger. 在图1中,P+/高压N阱/高压P阱形成的寄生PNP管Vbp的集电极同时也是N+/高压P阱/高压N阱形成的寄生NPN管Vbn的基极;同样,N+/高压P阱/高压N阱形成的寄生NPN管Vbn的集电极也是P+/高压N阱/高压P阱形成的寄生PNP管Vbp的基极。 In Figure 1, the collector of the parasitic PNP transistor Vbp the P + / high-voltage N-well / high pressure P well formed but also the N + / high voltage P-well / parasitic NPN transistor Vbn base high-voltage N well formed electrode; Similarly, N + / high pressure P the collector of the parasitic NPN transistor Vbn well / high-voltage N-well is formed by P + / N-well high-voltage / high-voltage P-well forming a parasitic PNP transistor base Vbp. 图1中的寄生NPN管Vbn和PNP管Vbp组成的等效电路如图2所示。 Vbn the parasitic NPN transistor in FIG. 1 and an equivalent circuit consisting of PNP transistor Vbp shown in FIG. 从图1和图2中可以看出,由P+/高压N阱/高压P阱形成的寄生PNP管Vbp和N+/高压P阱/高压N阱形成的寄生NPN管Vbn共同组成的硅控整流器的触发电压为高压N阱/高压P阱的反向击穿电压。 As can be seen from FIGS. 1 and 2, the parasitic NPN transistor Vbn parasitic PNP transistor Vbp formed by P + / high-voltage N-well / high voltage P-well and N + / high voltage P-well / high-voltage N-well is formed composed of a silicon controlled rectifier a high voltage trigger voltage N-well / P-well high pressure reverse breakdown voltage. 通常高压N阱/高压P阱结的反向击穿电压比较高,因此,这种结构的应用受到了很大的限制。 Typically high-voltage N-well / P-well junction of the high-pressure reverse breakdown voltage is relatively high, and therefore, the application of this structure has been greatly limited. 另外,由于硅控整流器本身开启后寄生NPN管和PNP管相互实现电流放大的正反馈,导致其导通电阻很低,放大倍数很大,发生骤回后的维持电压就会很低,一般在2〜5V之间。 Further, since the parasitic NPN transistor and the PNP transistor is turned on itself after the SCR current amplification with each other positive feedback, resulting in low on-resistance, a large amplification factor, after the sustain voltage snapback occurs will be very low, generally in between 2~5V. 而高压电路的正常工作电压远远在此之上,因此使用硅控整流器做高压静电保护电路,也易引发栓锁效应,且不易恢复。 Normal operating voltage and high-voltage circuit well above this, the use of silicon controlled rectifiers do high voltage electrostatic protection circuit, the latch can easily lead to the effect, and difficult to recover.

发明内容 SUMMARY

[0003] 本发明要解决的技术问题是提供一种静电保护结构,能方便有效地调节静电保护的触发电压,能有效的避免拴锁效应的发生而导致的拴锁测试失效问题,并且静电放电能力强。 [0003] The present invention is to solve the technical problem is to provide an electrostatic protection structure, can easily and effectively adjust the trigger voltage of the electrostatic protection, can effectively prevent the occurrence of latch-effects caused by the test latch failures, electrostatic discharge, and strong ability.

[0004] 为解决上述技术问题,本发明的静电保护结构,包含一N阱,一P阱,此两个阱相邻; [0004] In order to solve the above problems, the electrostatic protection structure of the present invention, comprises an N-well, a P-well, the two adjacent wells;

[0005] 所述N阱中,形成有第一P+扩散区、第二P+扩散区、第一N+扩散区、第二N+扩散区,所述第一N+扩散区和第二N+扩散区位于第一P+扩散区和第二P+扩散区两边,所述第一 P+扩散区、第二P+扩散区构成一PMOS管,第一P+扩散区、第二P+扩散区分别作为该PMOS管的漏和源极,第一P+扩散区、第二P+扩散区之间的沟道区上方形成有该PMOS管的栅极;N阱中所述二P+扩散区其中之一、所述二N+扩散区其中之一同所述PMOS管的栅极短接用于接静电端; [0005] The N-well, is formed with a first P + diffusion region, a second P + diffusion region, a first N + diffusion region, a second N + diffusion region of said first N + diffusion region and a second region located on the N + diffusion a P + diffusion region and a second P + sides diffusion region of said first P + diffusion region, a second P + diffusion region constituting a PMOS transistor, a first P + diffusion region, a second P + diffusion region respectively as drain and source of the PMOS transistor electrode, over the channel region between the first diffusion region P +, P + diffusion regions formed in the second gate of the PMOS transistor; one-P + diffusion region where the N-well, the two N + diffusion region of which the gate of PMOS transistor with a short access terminal for receiving an electrostatic;

[0006] 所述P阱中,形成有第三P+扩散区、第四P+扩散区、第三N+扩散区、第四N+扩散区,所述第三P+扩散区和第四P+扩散区位于第三N+扩散区和第四N+扩散区两边,所述第三N+扩散区、第四N+扩散区构成一NMOS管,第三N+扩散区、第四N+扩散区分别作为该NMOS管的漏和源极,第三N+扩散区、第四N+扩散区之间的沟道区上方形成有该NMOS管的栅极;P阱中所述二N+扩散区其中之一、所述二P+扩散区其中之一同所述NMOS管的栅极短接用于接地端; [0006] The P-well is formed a third diffusion region P +, P + diffusion region of the fourth, third N + diffusion region, a fourth N + diffusion region, said third and fourth P + diffusion region P + diffusion region located on both sides of the three N + diffusion region and a fourth N + diffusion region, a third N + diffusion region, a fourth N + diffusion region constituting an NMOS transistor, a third N + diffusion region, a fourth N + diffusion region respectively as drain and source of the NMOS transistor electrode, the third N + diffusion region, the fourth over the channel region between N + diffusion region forming the gate of the NMOS transistor; one of two N + diffusion region where the P-well, the two regions where the P + diffusion the gate of NMOS transistor with a short access to ground;

[0007] 所述N阱中的另外一个N+扩散区同所述P阱中的另外一个N+扩散区短接; [0007] The another N + diffusion region in the N well in the P-well with the other N + diffusion region shorted;

[0008] 所述N阱中的另外一个P+扩散区同所述P阱中的另外一个P+扩散区短接。 [0008] The other diffusion region P + P + diffusion region a further shorting with the P-well of the N wells.

[0009] 所述N阱中的四个扩散区,到所述P阱的距离由近到远依次是:第二N+扩散区,第二 P+扩散区,第一P+扩散区,第一N+扩散区;所述P阱中的四个扩散区,到所述N阱的距离由近到远依次是:第三P+扩散区,第三N+扩散区,第四N+扩散区,第四P+扩散区。 [0009] The four diffusion regions in the N well, P-well to the distance from near to far followed by: a second N + diffusion region, a second P + diffusion region, a first P + diffusion region, a first N + diffusion region; four diffusion regions in the P-well, N-well to a distance of the order from near to far are: a third P + diffusion region, a third N + diffusion region, a fourth N + diffusion region, a fourth diffusion region P + .

[0010] 所述N阱和P阱整体置于一N型埋层中。 [0010] The P-well and N-well disposed integrally an N-type buried layer.

[0011] 本发明的静电保护结构,整个结构形成在N型埋层上,在N型埋层中形成PMOS管和NMOS管,利用其寄生的PNP管和NPN管作为触发硅控整流器的开关。 [0011] The electrostatic protection structure of the present invention, the entire structure is formed on the N-type buried layer, forming PMOS transistor and NMOS transistor in the N-type buried layer, with its parasitic PNP transistor and the NPN transistor as a switch triggered silicon controlled rectifier. 而此PMOS管和NMOS管寄生的PNP管和NPN管的触发电压可由工艺的杂质注入进行调整,且达到P+/N阱的结击穿电压和N+/P阱的结击穿电压相同,能方便有效地调节静电保护的触发电压。 And this PMOS transistor and NMOS transistor parasitic trigger voltage PNP transistor and the NPN transistor may be an impurity implantation process is adjusted, and reaches a P + N-well junction / breakdown voltage and N + / P-well junction breakdown same voltage, can be easily effectively adjust the trigger voltage electrostatic protection. 本发明的静电保护结构整体的触发电压由PMOS管和NMOS管双重控制静电保护结构的触发,相对于单通过一种结进行触发的方式来说,本发明的静电保护结构由于用于触发的结面积增大,所需达到的触发电流会更大,一旦此触发电流高于进行拴锁测试时的电流,则可有效的避免拴锁效应的发生而导致的拴锁测试失效问题,同时由于用于触发的结面积的增大,其结所能承受的极限电流也相应提高,这对于一些具有上升速度更快而且峰值电流更高特点的静电电流的防护来说,相比较于通常的静电保护结构,静电放电能力强,其防护效果更好。 Trigger voltage of the electrostatic protection overall structure of the present invention is composed of the NMOS and PMOS transistors trigger electrostatic protection dual control structure, with respect to the single trigger mode is achieved by a junction, the electrostatic protection structure of the present invention for triggering due junction area increases, the current required to achieve the trigger will be greater, once this trigger current is greater than when the latch tests, can effectively prevent the occurrence of latch-effects caused by latch test failures, and because use the junction area is increased to a trigger, which junction can bear a corresponding increase in the current limit, which for some speed and having a faster rise to electrostatic discharge protection features for higher peak currents, compared to the conventional electrostatic protection structure, strong electrostatic discharge capacity, the better protection.

附图说明 BRIEF DESCRIPTION

[0012] 下面结合附图及具体实施方式对本发明作进一步详细说明。 [0012] Hereinafter, the present invention is described in further detail in conjunction with accompanying drawings and specific embodiments.

[0013] 图1是常见的硅控整流器的剖面结构示意图; [0013] FIG. 1 is a schematic cross-sectional structure of a common silicon controlled rectifier;

[0014] 图2是图1中的硅控整流器的寄生NPN和PNP管组成的等效电路图; [0014] FIG. 2 is an equivalent circuit diagram of the parasitic PNP transistor and the NPN silicon controlled rectifier in FIG. 1 thereof;

[0015]图3是本发明的静电保护结构的等效电路; [0015] FIG. 3 is an equivalent circuit of the electrostatic protection structure according to the present invention;

[0016]图4是本发明的静电保护结构第一实施例剖面结构示意图; [0016] FIG. 4 is a schematic cross-sectional structure of the electrostatic protection structure of a first embodiment of the present invention;

[0017]图5是本发明的静电保护结构第二实施例剖面结构示意图。 [0017] FIG. 5 is a schematic cross-sectional structure of a second embodiment of the electrostatic protection structure of the present invention.

具体实施方式 Detailed ways

[0018] 本发明的静电保护结构,其等效电路如图3所示。 [0018] The electrostatic protection structure of the present invention, the equivalent circuit shown in Figure 3.

[0019] 本发明的静电保护结构,包含一N讲,一P阱,此两个阱相邻; [0019] The electrostatic protection structure of the present invention, comprises an N-speaking, a P-well, the two adjacent wells;

[0020] 所述N阱中,形成有第一P+扩散区、第二P+扩散区、第一N+扩散区、第二N+扩散区,所述第一N+扩散区和第二N+扩散区位于第一P+扩散区和第二P+扩散区两边,所述第一 P+扩散区、第二P+扩散区构成一PMOS管,第一P+扩散区、第二P+扩散区分别作为该PMOS管的漏和源极,第一P+扩散区、第二P+扩散区之间的沟道区上方形成有该PMOS管的栅极;N阱中所述二P+扩散区其中之一、所述二N+扩散区其中之一同所述PMOS管的栅极短接用于接静电端; [0020] The N-well, is formed with a first P + diffusion region, a second P + diffusion region, a first N + diffusion region, a second N + diffusion region of said first N + diffusion region and a second region located on the N + diffusion a P + diffusion region and a second P + sides diffusion region of said first P + diffusion region, a second P + diffusion region constituting a PMOS transistor, a first P + diffusion region, a second P + diffusion region respectively as drain and source of the PMOS transistor electrode, over the channel region between the first diffusion region P +, P + diffusion regions formed in the second gate of the PMOS transistor; one-P + diffusion region where the N-well, the two N + diffusion region of which the gate of PMOS transistor with a short access terminal for receiving an electrostatic;

[0021 ] 所述P阱中,形成有第三P+扩散区、第四P+扩散区、第三N+扩散区、第四N+扩散区,所述第三P+扩散区和第四P+扩散区位于第三N+扩散区和第四N+扩散区两边,所述第三N+扩散区、第四N+扩散区构成一NMOS管,第三N+扩散区、第四N+扩散区分别作为该NMOS管的漏和源极,第三N+扩散区、第四N+扩散区之间的沟道区上方形成有该NMOS管的栅极;P阱中所述二N+扩散区其中之一、所述二P+扩散区其中之一同所述NMOS管的栅极短接用于接地端; [0021] The P-well is formed a third diffusion region P +, P + diffusion region of the fourth, third N + diffusion region, a fourth N + diffusion region, said third and fourth P + diffusion region P + diffusion region located on both sides of the three N + diffusion region and a fourth N + diffusion region, a third N + diffusion region, a fourth N + diffusion region constituting an NMOS transistor, a third N + diffusion region, a fourth N + diffusion region respectively as drain and source of the NMOS transistor electrode, the third N + diffusion region, the fourth over the channel region between N + diffusion region forming the gate of the NMOS transistor; one of two N + diffusion region where the P-well, the two regions where the P + diffusion the gate of NMOS transistor with a short access to ground;

[0022] 所述N阱中的另外一个N+扩散区同所述P阱中的另外一个N+扩散区短接; [0022] The another N + diffusion region in the N well in the P-well with the other N + diffusion region shorted;

[0023] 所述N阱中的另外一个P+扩散区同所述P阱中的另外一个P+扩散区短接。 [0023] The N-well in a P + diffusion region further another P + diffusion region with the P-well short of.

[0024] 所述N阱中的四个扩散区,到所述P阱的距离由近到远依次是:第二N+扩散区,第二 P+扩散区,第一P+扩散区,第一N+扩散区;所述P阱中的四个扩散区,到所述N阱的距离由近到远依次是:第三P+扩散区,第三N+扩散区,第四N+扩散区,第四P+扩散区。 [0024] The four diffusion regions in the N well, P-well to the distance from near to far followed by: a second N + diffusion region, a second P + diffusion region, a first P + diffusion region, a first N + diffusion region; four diffusion regions in the P-well, N-well to a distance of the order from near to far are: a third P + diffusion region, a third N + diffusion region, a fourth N + diffusion region, a fourth diffusion region P + .

[0025] 第一实施例,如图4所示,N阱中所述第二P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第四P+扩散区短接。 [0025] The first embodiment, as shown in FIG, N-well of said second P + diffusion region, the second gate shorting with N + diffusion region of said PMOS transistor for receiving an end electrostatic FIG 4; P-well said third N + diffusion region, said third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with a fourth N + short diffusion region; N-well of the first P + diffusion region with said fourth P-well regions short-circuited P + diffusion.

[0026] 第二实施例,如图5所示,N阱中所述第一P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第三P+扩散区短接。 [0026] The second embodiment, shown in Figure 5, N-well of the first P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end; P-well said fourth N + diffusion region, said fourth P + diffusion region with the gate shorted to the ground terminal of the NMOS transistor; N-well N + diffusion region of said second P-well with the third N + short diffusion region; N-well of said second P + diffusion region with said third P-well regions short-circuited P + diffusion.

[0027] 第三实施例,N阱中所述第二P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第三P+扩散区短接。 [0027] The third embodiment, N-well of said second P + diffusion region, said second N + diffusion region with a gate short-circuited to said PMOS transistor for receiving an electrostatic end; P-well in the fourth N + diffusion region, said fourth P + diffusion region with the gate shorted to the ground terminal of the NMOS transistor; N-well N + diffusion region of said first P-well with the third N + diffusion region shorted; N the first well with P + diffusion region of said third P-well regions short-circuited P + diffusion.

[0028] 第四实施例,N阱中所述第一P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第四P+扩散区短接。 [0028] The fourth embodiment, N-well of the first P + diffusion region, the first N + diffusion region with a gate short-circuited to said PMOS transistor for receiving an electrostatic end; P-well of the third N + diffusion region, said third P + diffusion region with the gate shorted to the ground terminal of the NMOS transistor; N-well N + diffusion region of said second P-well with a fourth N + diffusion region of the short-circuited; N the second well with P + diffusion region of said fourth P-well regions short-circuited P + diffusion.

[0029] 第五实施例,N阱中所述第二P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第四P+扩散区短接。 [0029] The fifth embodiment, N-well of said second P + diffusion region, the first N + diffusion region with a gate short-circuited to said PMOS transistor for receiving an electrostatic end; P-well of the third N + diffusion region, said third P + diffusion region with the gate shorted to the ground terminal of the NMOS transistor; N-well N + diffusion region of said second P-well with a fourth N + diffusion region of the short-circuited; N the first well with P + diffusion region of said fourth P-well regions short-circuited P + diffusion.

[0030] 第六实施例,N阱中所述第二P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第三P+扩散区短接。 [0030] The sixth embodiment, N-well of said second P + diffusion region, the first N + diffusion region with a gate short-circuited to said PMOS transistor for receiving an electrostatic end; P-well in the fourth N + diffusion region, said fourth P + diffusion region with the gate shorted to the ground terminal of the NMOS transistor; N-well N + diffusion region of said second P-well with the third N + diffusion region shorted; N the first well with P + diffusion region of said third P-well regions short-circuited P + diffusion.

[0031] 第七实施例,N阱中所述第二P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第四P+扩散区短接。 [0031] the seventh embodiment, N-well of said second P + diffusion region, the first N + diffusion region with a gate short-circuited to said PMOS transistor for receiving an electrostatic end; P-well in the fourth N + diffusion region, said third P + diffusion region with the gate shorted to the ground terminal of the NMOS transistor; N-well N + diffusion region of said second P-well with the third N + diffusion region shorted; N the first well with P + diffusion region of said fourth P-well regions short-circuited P + diffusion.

[0032] 第八实施例,N阱中所述第二P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第三P+扩散区短接。 [0032] The eighth embodiment, N-well of said second P + diffusion region, the first N + diffusion region with a gate short-circuited to said PMOS transistor for receiving an electrostatic end; P-well of the third N + diffusion region, said fourth P + diffusion region with the gate shorted to the ground terminal of the NMOS transistor; N-well N + diffusion region of said second P-well with a fourth N + diffusion region of the short-circuited; N the first well with P + diffusion region of said third P-well regions short-circuited P + diffusion.

[0033] 第九实施例,N阱中所述第一P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第四P+扩散区短接。 [0033] The ninth embodiment, N-well of the first P + diffusion region, said second N + diffusion region with a gate short-circuited to said PMOS transistor for receiving an electrostatic end; P-well of the third N + diffusion region, said third P + diffusion region with the gate shorted to the ground terminal of the NMOS transistor; N-well N + diffusion region of said first P-well with a fourth N + diffusion region of the short-circuited; N the second well with P + diffusion region of said fourth P-well regions short-circuited P + diffusion.

[0034] 第十实施例,N阱中所述第一P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第三P+扩散区短接。 [0034] The tenth embodiment, N-well of the first P + diffusion region, said second N + diffusion region with a gate short-circuited to said PMOS transistor for receiving an electrostatic end; P-well in the fourth N + diffusion region, said fourth P + diffusion region with the gate shorted to the ground terminal of the NMOS transistor; N-well N + diffusion region of said first P-well with the third N + diffusion region shorted; N the second well with P + diffusion region of said third P-well regions short-circuited P + diffusion.

[0035] 第十一实施例,N阱中所述第一P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第四P+扩散区短接。 [0035] In the eleventh embodiment, N-well of the first P + diffusion region, said second N + diffusion region to the gate of the PMOS transistor is shorted to ground electrostatic end; P-well in the fourth N + diffusion region, said third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the third N + diffusion region short-circuited; said second N-well with the P + diffusion region of said fourth P-well regions short-circuited P + diffusion.

[0036] 第十二实施例,N阱中所述第一P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第三P+扩散区短接。 [0036] The twelfth embodiment, N-well of the first P + diffusion region, said second N + diffusion region to the gate of the PMOS transistor is shorted to ground electrostatic end; said third P-well N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with a fourth N + diffusion region of the short-circuited; said second N-well with the P + diffusion region of said third P-well regions short-circuited P + diffusion.

[0037] 第十三实施例,N阱中所述第二P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第三P+扩散区短接。 [0037] The thirteenth embodiment, N-well of said second P + diffusion region, the second gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end; said third P-well N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with a fourth N + diffusion region of the short-circuited; said first N-well with the P + diffusion region of said third P-well regions short-circuited P + diffusion.

[0038] 第十四实施例,N阱中所述第一P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第三P+扩散区短接。 [0038] The fourteenth embodiment, N-well of the first P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end; said third P-well N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with a fourth N + diffusion region of the short-circuited; said second N-well with the P + diffusion region of said third P-well regions short-circuited P + diffusion.

[0039] 第十五实施例,N阱中所述第二P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第四P+扩散区短接。 [0039] In the fifteenth embodiment, N-well of said second P + diffusion region, the second gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end; P-well in the fourth N + diffusion region, said third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the third N + diffusion region short-circuited; N-well of the first P + diffusion region with said fourth P-well regions short-circuited P + diffusion.

[0040] 第十六实施例,N阱中所述第一P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第四P+扩散区短接。 [0040] The sixteenth embodiment, N-well of the first P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end; P-well in the fourth N + diffusion region, said third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with the third N + diffusion region short-circuited; said second N-well with the P + diffusion region of said fourth P-well regions short-circuited P + diffusion.

[0041] 本发明的静电保护结构,可运用于B⑶工艺,整个结构形成在N型埋层上,在N型埋层中形成PMOS管和NMOS管,利用其寄生的PNP管和NPN管作为触发硅控整流器的开关。 [0041] The electrostatic protection structure of the present invention can be applied B⑶ process, the entire structure is formed on the N-type buried layer is formed in the PMOS transistor and NMOS transistor N-type buried layer, with its parasitic PNP transistor and the NPN transistor as a trigger silicon controlled rectifier switch. 当此PNP管和NPN管随着静电放电(ESD)电流的冲击而被触发开启后,也会同时触发由N阱中的P+/N阱/P阱中的P+扩散区组成的PNP三极管以及由N阱/P阱/P阱中的N+扩散区组成的NPN三极管,进入正反馈的电流放大状态泻放电流,而此PMOS管和NMOS管寄生的PNP管和NPN管的触发电压可由工艺的杂质注入进行调整,且达到P+/N阱的结击穿电压和N+/P阱的结击穿电压相同,能方便有效地调节静电保护的触发电压。 When this PNP transistor and the NPN transistor with impact of static electricity (ESD) current is triggered on, will also trigger PNP transistor by the P + diffusion regions in the N well P + / N-well / P-well in the composition and the NPN transistor N-well / P-well / P N + diffusion regions trap consisting of current into positive feedback amplifying state bleed current, and this PMOS transistor and NMOS transistor parasitic trigger voltage PNP transistor and the NPN transistor may be process impurities injection to adjust and achieve the P + N-well junction / breakdown voltage and N + / P-well junction breakdown voltage of the same, can easily and effectively adjust the trigger voltage of the electrostatic protection. 本发明的静电保护结构整体的触发电压由PMOS管和NMOS管双重控制静电保护结构的触发,相对于单通过一种结进行触发的方式来说,本发明的静电保护结构由于用于触发的结面积增大,所需达到的触发电流会更大,一旦此触发电流高于进行拴锁测试时的电流,则可有效的避免拴锁效应的发生而导致的拴锁测试失效问题,同时由于用于触发的结面积的增大,其结所能承受的极限电流也相应提高,这对于一些具有上升速度更快而且峰值电流更高特点的静电电流的防护来说,相比较于通常的静电保护结构,静电放电能力强,其防护效果更好。 Trigger voltage of the electrostatic protection overall structure of the present invention is composed of the NMOS and PMOS transistors trigger electrostatic protection dual control structure, with respect to the single trigger mode is achieved by a junction, the electrostatic protection structure of the present invention for triggering due junction area increases, the current required to achieve the trigger will be greater, once this trigger current is greater than when the latch tests, can effectively prevent the occurrence of latch-effects caused by latch test failures, and because use the junction area is increased to a trigger, which junction can bear a corresponding increase in the current limit, which for some speed and having a faster rise to electrostatic discharge protection features for higher peak currents, compared to the conventional electrostatic protection structure, strong electrostatic discharge capacity, the better protection.

Claims (18)

1.一种静电保护结构,包含一N阱,一P阱,此两个阱相邻;其特征在于, 所述N阱中,形成有第一P+扩散区、第二P+扩散区、第一N+扩散区、第二N+扩散区,所述第一N+扩散区和第二N+扩散区位于第一P+扩散区和第二P+扩散区两边,所述第一P+扩散区、第二P+扩散区构成一PMOS管,第一P+扩散区、第二P+扩散区分别作为该PMOS管的漏和源极,第一P+扩散区、第二P+扩散区之间的沟道区上方形成有该PMOS管的栅极;N阱中所述二P+扩散区其中之一、所述二N+扩散区其中之一同所述PMOS管的栅极短接用于接静电端; 所述P阱中,形成有第三P+扩散区、第四P+扩散区、第三N+扩散区、第四N+扩散区,所述第三P+扩散区和第四P+扩散区位于第三N+扩散区和第四N+扩散区两边,所述第三N+扩散区、第四N+扩散区构成一NMOS管,第三N+扩散区、第四N+扩散区分别作为该NMOS管的漏和源极,第三N+ An electrostatic protection structure comprising an N-well, a P-well, the two adjacent wells; wherein, in said N-well, is formed with a first P + diffusion region, a second P + diffusion region, a first N + diffusion region, a second N + diffusion region, said first and second N + diffusion regions N + diffusion region located on both sides of the first P + P + diffusion region and the second diffusion region, a first P + diffusion region, a second P + diffusion region constituting a PMOS transistor, a first P + diffusion region, a second P + diffusion regions are pole, a first P + diffusion region, over the second channel region between P + diffusion region of the PMOS transistor is formed as the drain and source of the PMOS transistor gate; one-P + diffusion region where the N-well, wherein one of the two N + diffusion regions to the gate of the PMOS transistor is shorted to ground electrostatic end; the P-well, is formed with a first three P + diffusion region, the fourth P + diffusion region, a third N + diffusion region, a fourth N + diffusion region, said third P + diffusion region and a fourth P + diffusion regions at the third N + sides diffusion region and the fourth N + diffusion region, the third N + diffusion region, a fourth N + diffusion region constituting an NMOS transistor, a third N + diffusion region, a fourth N + diffusion region respectively as drain and source electrode of the NMOS transistor, a third N + 扩散区、第四N+扩散区之间的沟道区上方形成有该NMOS管的栅极;P阱中所述二N+扩散区其中之一、所述二P+扩散区其中之一同所述NMOS管的栅极短接用于接地端; 所述N阱中的另外一个N+扩散区同所述P阱中的另外一个N+扩散区短接; 所述N阱中的另外一个P+扩散区同所述P阱中的另外一个P+扩散区短接; 所述N阱和P阱整体置于一N型埋层中。 Diffusion region of the fourth over the channel region between N + diffusion region forming the gate of the NMOS transistor; one of two N + diffusion region where the P-well, wherein one of the two P + diffusion regions of the NMOS transistor with gate shorted to ground; the other N + diffusion region in said N-well with the P-well in a N + diffusion region further short; another P + diffusion regions in said N-well with the another P-well regions short-circuited P + diffusion; the P-well and N-well disposed integrally an N-type buried layer.
2.根据权利要求1所述的静电保护结构,其特征在于,所述N阱中的四个扩散区,到所述P阱的距离由近到远依次是:第二N+扩散区,第二P+扩散区,第一P+扩散区,第一N+扩散区;所述P阱中的四个扩散区,到所述N阱的距离由近到远依次是:第三P+扩散区,第三N+扩散区,第四N+扩散区,第四P+扩散区。 2. The electrostatic protection structure according to claim 1, characterized in that the four diffusion regions N wells, the P-well to a distance from near to far are: a second N + diffusion regions, a second P + diffusion region, a first P + diffusion region, a first N + diffusion region; four diffusion regions in the P-well, N-well to a distance of the order from near to far are: a third P + diffusion region, a third N + diffusion region of the fourth N + diffusion region, the fourth P + diffusion region.
3.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第二 P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第四P+扩散区短接。 3. The electrostatic protection structure according to claim 2, characterized in that the short gate N-well region of the second P + diffusion, N + diffusion region of said second PMOS transistor with the terminal for receiving an electrostatic ; P-well of the third N + diffusion region, said third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the a fourth N + diffusion region shorted; N-well of the first P + diffusion region with said fourth P-well regions short-circuited P + diffusion.
4.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第一 P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第三P+扩散区短接。 4. The electrostatic protection structure according to claim 2, characterized in that, N-well of the first P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well of the fourth N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with the the third N + diffusion region shorted; N-well of said second P + diffusion region with said third P-well regions short-circuited P + diffusion.
5.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第二 P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第三P+扩散区短接。 The electrostatic protection structure according to claim 2, characterized in that the short gate N-well region of the second P + diffusion, N + diffusion region of said second PMOS transistor with the terminal for receiving an electrostatic ; P-well of the fourth N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the the third N + diffusion region shorted; N-well of the first P + diffusion region with said third P-well regions short-circuited P + diffusion.
6.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第一 P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第四P+扩散区短接。 6. The electrostatic protection structure according to claim 2, characterized in that, N-well of the first P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well of the third N + diffusion region, said third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with the a fourth N + diffusion region shorted; N-well of said second P + diffusion region with said fourth P-well regions short-circuited P + diffusion.
7.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第二 P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第四P+扩散区短接。 7. The electrostatic protection structure according to claim 2, characterized in that, N-well of said second P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well of the third N + diffusion region, said third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with the a fourth N + diffusion region shorted; N-well of the first P + diffusion region with said fourth P-well regions short-circuited P + diffusion.
8.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第二 P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第三P+扩散区短接。 8. The electrostatic protection structure according to claim 2, characterized in that, N-well of said second P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well of the fourth N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with the the third N + diffusion region shorted; N-well of the first P + diffusion region with said third P-well regions short-circuited P + diffusion.
9.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第二 P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第四P+扩散区短接。 9. The electrostatic protection structure according to claim 2, characterized in that, N-well of said second P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well N + diffusion region of the fourth, the third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with the the third N + diffusion region shorted; N-well of the first P + diffusion region with said fourth P-well regions short-circuited P + diffusion.
10.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第二 P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第三P+扩散区短接。 10. The electrostatic protection structure according to claim 2, characterized in that, N-well of said second P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well of the third N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with the a fourth N + diffusion region shorted; N-well of the first P + diffusion region with said third P-well regions short-circuited P + diffusion.
11.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第一 P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第四P+扩散区短接。 11. The electrostatic protection structure according to claim 2, characterized in that, N-well of the first P + diffusion region, the second gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well of the third N + diffusion region, said third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the a fourth N + diffusion region shorted; N-well of said second P + diffusion region with said fourth P-well regions short-circuited P + diffusion.
12.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第一 P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第三P+扩散区短接。 12. The electrostatic protection structure according to claim 2, characterized in that, N-well of the first P + diffusion region, the second gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well of the fourth N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the the third N + diffusion region shorted; N-well of said second P + diffusion region with said third P-well regions short-circuited P + diffusion.
13.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第一 P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第四P+扩散区短接。 13. The electrostatic protection structure according to claim 2, characterized in that, N-well of the first P + diffusion region, the second gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well N + diffusion region of the fourth, the third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the the third N + diffusion region shorted; N-well of said second P + diffusion region with said fourth P-well regions short-circuited P + diffusion.
14.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第一 P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第三P+扩散区短接。 14. The electrostatic protection structure according to claim 2, characterized in that, N-well of the first P + diffusion region, the second gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well of the third N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the a fourth N + diffusion region shorted; N-well of said second P + diffusion region with said third P-well regions short-circuited P + diffusion.
15.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第二 P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第三P+扩散区短接。 15. The electrostatic protection structure according to claim 2, characterized in that the short gate N-well region of the second P + diffusion, N + diffusion region of said second PMOS transistor with the terminal for receiving an electrostatic ; P-well of the third N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the a fourth N + diffusion region shorted; N-well of the first P + diffusion region with said third P-well regions short-circuited P + diffusion.
16.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第一 P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第三N+扩散区、所述第四P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第四N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第三P+扩散区短接。 16. The electrostatic protection structure according to claim 2, characterized in that, N-well of the first P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well of the third N + diffusion region, said fourth P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with the a fourth N + diffusion region shorted; N-well of said second P + diffusion region with said third P-well regions short-circuited P + diffusion.
17.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第二 P+扩散区、所述第二N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第一N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第一P+扩散区同P阱中所述第四P+扩散区短接。 17. The electrostatic protection structure according to claim 2, characterized in that the short gate N-well region of the second P + diffusion, N + diffusion region of said second PMOS transistor with the terminal for receiving an electrostatic ; P-well N + diffusion region of the fourth, the third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said first P-well with the the third N + diffusion region shorted; N-well of the first P + diffusion region with said fourth P-well regions short-circuited P + diffusion.
18.根据权利要求2所述的静电保护结构,其特征在于,N阱中所述第一P+扩散区、所述第一N+扩散区同所述PMOS管的栅极短接用于接静电端;P阱中所述第四N+扩散区、所述第三P+扩散区同所述NMOS管的栅极短接用于接地端;N阱中所述第二N+扩散区同P阱中所述第三N+扩散区短接;N阱中所述第二P+扩散区同P阱中所述第四P+扩散区短接。 18. The electrostatic protection structure according to claim 2, characterized in that, N-well of the first P + diffusion region, said first gate shorting with N + diffusion region of said PMOS transistor for receiving an electrostatic end ; P-well N + diffusion region of the fourth, the third P + diffusion regions to the gate of the NMOS transistor shorted to ground; N-well N + diffusion region of said second P-well with the the third N + diffusion region shorted; N-well of said second P + diffusion region with said fourth P-well regions short-circuited P + diffusion.
CN201110103518.4A 2011-04-25 2011-04-25 Electrostatic protection structure CN102760731B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110103518.4A CN102760731B (en) 2011-04-25 2011-04-25 Electrostatic protection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110103518.4A CN102760731B (en) 2011-04-25 2011-04-25 Electrostatic protection structure

Publications (2)

Publication Number Publication Date
CN102760731A CN102760731A (en) 2012-10-31
CN102760731B true CN102760731B (en) 2015-12-02

Family

ID=47055124

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110103518.4A CN102760731B (en) 2011-04-25 2011-04-25 Electrostatic protection structure

Country Status (1)

Country Link
CN (1) CN102760731B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103745973B (en) * 2013-12-26 2016-06-01 中国科学院微电子研究所 And one kind esd protection device for battery management circuit chip esd

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6015992A (en) * 1997-01-03 2000-01-18 Texas Instruments Incorporated Bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits
CN1445849A (en) * 2002-03-17 2003-10-01 联华电子股份有限公司 Electrostatic discharge protection circuit
CN101442047A (en) * 2007-11-23 2009-05-27 上海华虹Nec电子有限公司 Electrostatic protection structure for low trigger voltage thyristor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101006514B1 (en) * 2004-04-28 2011-01-07 매그나칩 반도체 유한회사 A silicon controlled rectifier for protecting the device in a electrostatic discharge

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6015992A (en) * 1997-01-03 2000-01-18 Texas Instruments Incorporated Bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits
CN1445849A (en) * 2002-03-17 2003-10-01 联华电子股份有限公司 Electrostatic discharge protection circuit
CN101442047A (en) * 2007-11-23 2009-05-27 上海华虹Nec电子有限公司 Electrostatic protection structure for low trigger voltage thyristor

Also Published As

Publication number Publication date
CN102760731A (en) 2012-10-31

Similar Documents

Publication Publication Date Title
US6498357B2 (en) Lateral SCR device for on-chip ESD protection in shallow-trench-isolation CMOS process
Ker et al. Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
US8044457B2 (en) Transient over-voltage clamp
US6690067B2 (en) ESD protection circuit sustaining high ESD stress
US7196887B2 (en) PMOS electrostatic discharge (ESD) protection device
KR101162124B1 (en) Stacked esd protection circuit having reduced trigger voltage
US20100090283A1 (en) Electro Static Discharge Protection Device
US7554839B2 (en) Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch
KR20120081830A (en) Semiconductor device and fabricating method thereof
KR20080025507A (en) Device of protecting an electro static discharge for high voltage and manufacturing method thereof
CN1277311C (en) Electrostatic discharge protection device and IC
US20040251502A1 (en) Efficient pMOS ESD protection circuit
US6433979B1 (en) Electrostatic discharge protection device using semiconductor controlled rectifier
US9035375B2 (en) Field-effect device and manufacturing method thereof
US20050270710A1 (en) Silicon controlled rectifier for the electrostatic discharge protection
CN101587894A (en) Electrostatic discharge (esd) protection applying high voltage lightly doped drain (ldd) cmos technologies
US9129805B2 (en) Diode biased ESD protection device and method
US20100109043A1 (en) Methods and structures for electrostatic discharge protection
US20040052020A1 (en) Devices without current crowding effect at the finger's ends
US9209265B2 (en) ESD devices comprising semiconductor fins
CN101930974B (en) Bottom source NMOS triggered zener clamp for configuring ultra-low voltage transient voltage suppressor (TVS)
JP4746346B2 (en) Semiconductor device
US8890259B2 (en) SCR apparatus and method for adjusting the sustaining voltage
US7763940B2 (en) Device having a low-voltage trigger element
US6646840B1 (en) Internally triggered electrostatic device clamp with stand-off voltage

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
C53 Correction of patent for invention or patent application
COR Change of bibliographic data

Free format text: CORRECT: APPLICANT; FROM: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI TO: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION

C14 Grant of patent or utility model