CN102760731B - Electrostatic preventing structure - Google Patents
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- CN102760731B CN102760731B CN201110103518.4A CN201110103518A CN102760731B CN 102760731 B CN102760731 B CN 102760731B CN 201110103518 A CN201110103518 A CN 201110103518A CN 102760731 B CN102760731 B CN 102760731B
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Abstract
The invention discloses a kind of electrostatic preventing structure, comprise a N trap, a P trap; Be formed with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region, the 2nd N+ diffusion region in N trap, a P+ diffusion region, the 2nd P+ diffusion region form a PMOS; The grid short circuit of the together described PMOS of one of two P+ diffusion regions in N trap, two N+ diffusion regions is used for connecing electrostatic end; Be formed with the 3rd P+ diffusion region, the 4th P+ diffusion region, the 3rd N+ diffusion region, the 4th N+ diffusion region in P trap, the 3rd N+ diffusion region, the 4th N+ diffusion region form a NMOS tube; The grid short circuit of the together described NMOS tube of one of two N+ diffusion regions in P trap, two P+ diffusion regions is used for earth terminal; Another one N+ diffusion region in N trap is with the another one N+ diffusion region short circuit in P trap; Another one P+ diffusion region in N trap is with the another one P+ diffusion region short circuit in P trap.The present invention easily and effectively can regulate the trigger voltage of electrostatic protection, can effectively avoid fastening lock effect, and electrostatic discharge capacity is strong.
Description
Technical field
The present invention relates to semiconductor electrostatic resist technology, particularly a kind of electrostatic preventing structure.
Background technology
As electrostatic preventing structure; triode parasitic in thyristor (SCR) has stronger electrostatic leakage ability than Metal-oxide-semicondutor field effect transistor (MOSFET), and the electrostatic leakage ability of general thyristor is 5 ~ 7 times of MOSFET.Figure 1 shows that the cross-sectional view of existing high trigger voltage thyristor.In FIG, the collector electrode of the parasitic PNP pipe Vbp that P+/high pressure N trap/high pressure P trap is formed also is the base stage of the parasitic NPN pipe Vbn that N+/high pressure P trap/high pressure N trap is formed simultaneously; Equally, the collector electrode of the parasitic NPN pipe Vbn that N+/high pressure P trap/high pressure N trap is formed also is the base stage of the parasitic PNP pipe Vbp that P+/high pressure N trap/high pressure P trap is formed.The equivalent electric circuit of the parasitic NPN pipe Vbn in Fig. 1 and PNP pipe Vbp composition as shown in Figure 2.As can be seen from Fig. 1 and Fig. 2, the trigger voltage of the thyristor that the parasitic NPN pipe Vbn that the parasitic PNP pipe Vbp formed by P+/high pressure N trap/high pressure P trap and N+/high pressure P trap/high pressure N trap is formed forms jointly is the reverse breakdown voltage of high pressure N trap/high pressure P trap.The reverse breakdown voltage of usual high pressure N trap/high pressure P trap knot is higher, and therefore, the application of this structure is limited by very large.In addition, because parasitic NPN pipe and PNP pipe realize the positive feedback of Current amplifier mutually after thyristor unlatching itself, cause its conducting resistance very low, multiplication factor is very large, and the ME for maintenance occurred after rapid time will be very low, generally between 2 ~ 5V.And the normal working voltage of high-tension circuit is far away on this, therefore uses thyristor to do high-pressure electrostatic protective circuit, also easily cause bolt-lock effect, and not easily recover.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of electrostatic preventing structure, easily and effectively can regulate the trigger voltage of electrostatic protection, effectively can avoid fastening the generation of lock effect and the lock test failure problem of fastening that causes, and electrostatic discharge capacity is strong.
For solving the problems of the technologies described above, electrostatic preventing structure of the present invention, comprises a N trap, a P trap, and these two traps are adjacent;
In described N trap, be formed with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region, the 2nd N+ diffusion region, a described N+ diffusion region and the 2nd N+ diffusion region are positioned at a P+ diffusion region and the 2nd both sides, P+ diffusion region, a described P+ diffusion region, the 2nd P+ diffusion region form a PMOS, one P+ diffusion region, the 2nd P+ diffusion region, respectively as the leakage of this PMOS and source electrode, are formed with the grid of this PMOS above the channel region between a P+ diffusion region, the 2nd P+ diffusion region; Two P+ diffusion regions described in N trap one of them, one of them grid short circuit with described PMOS of described two N+ diffusion regions is used for connecing electrostatic end;
In described P trap, be formed with the 3rd P+ diffusion region, the 4th P+ diffusion region, the 3rd N+ diffusion region, the 4th N+ diffusion region, described 3rd P+ diffusion region and the 4th P+ diffusion region are positioned at the 3rd N+ diffusion region and the 4th both sides, N+ diffusion region, described 3rd N+ diffusion region, the 4th N+ diffusion region form a NMOS tube, 3rd N+ diffusion region, the 4th N+ diffusion region, respectively as the leakage of this NMOS tube and source electrode, are formed with the grid of this NMOS tube above the channel region between the 3rd N+ diffusion region, the 4th N+ diffusion region; Two N+ diffusion regions described in P trap one of them, one of them grid short circuit with described NMOS tube of described two P+ diffusion regions be used for earth terminal;
Another one N+ diffusion region in described N trap is with the another one N+ diffusion region short circuit in described P trap;
Another one P+ diffusion region in described N trap is with the another one P+ diffusion region short circuit in described P trap.
Four diffusion regions in described N trap, to described P trap distance from the near to the remote successively: the 2nd N+ diffusion region, the 2nd P+ diffusion region, a P+ diffusion region, a N+ diffusion region; Four diffusion regions in described P trap, to described N trap distance from the near to the remote successively: the 3rd P+ diffusion region, the 3rd N+ diffusion region, the 4th N+ diffusion region, the 4th P+ diffusion region.
Described N trap and P trap entirety are placed in a n type buried layer.
Electrostatic preventing structure of the present invention, total is formed on n type buried layer, forms PMOS and NMOS tube in n type buried layer, utilizes the PNP pipe of its parasitism and NPN pipe as the switch triggering thyristor.And the trigger voltage of the PNP pipe of this PMOS and NMOS tube parasitism and NPN pipe can be adjusted by the impurity injection of technique, and the junction breakdown voltage reaching P+/N trap is identical with the junction breakdown voltage of N+/P trap, easily and effectively can regulate the trigger voltage of electrostatic protection.The trigger voltage of electrostatic preventing structure entirety of the present invention is by the triggering of PMOS and NMOS tube two ore control electrostatic preventing structure, the mode triggered is carried out relative to a kind of knot of single pass-through, electrostatic preventing structure of the present invention is due to the junction area increase for triggering, needed for the trigger current that reaches can be larger, once this trigger current higher than carrying out the electric current of fastening lock test, then effectively can avoid fastening the generation of lock effect and the lock test failure problem of fastening that causes, simultaneously due to the increase of the junction area for triggering, it ties the limiting current also corresponding raising that can bear, this has the protection of the electrostatic induced current of the faster and higher feature of peak current of the rate of climb for some, be compared to common electrostatic preventing structure, electrostatic discharge capacity is strong, its better protecting effect.
Accompanying drawing explanation
Below in conjunction with the drawings and the specific embodiments, the present invention is described in further detail.
Fig. 1 is the cross-sectional view of common thyristor;
Fig. 2 is the parasitic NPN of thyristor in Fig. 1 and the equivalent circuit diagram of PNP pipe composition;
Fig. 3 is the equivalent electric circuit of electrostatic preventing structure of the present invention;
Fig. 4 is electrostatic preventing structure first embodiment cross-sectional view of the present invention;
Fig. 5 is electrostatic preventing structure second embodiment cross-sectional view of the present invention.
Embodiment
Electrostatic preventing structure of the present invention, its equivalent electric circuit as shown in Figure 3.
Electrostatic preventing structure of the present invention, comprises a N trap, a P trap, and these two traps are adjacent;
In described N trap, be formed with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region, the 2nd N+ diffusion region, a described N+ diffusion region and the 2nd N+ diffusion region are positioned at a P+ diffusion region and the 2nd both sides, P+ diffusion region, a described P+ diffusion region, the 2nd P+ diffusion region form a PMOS, one P+ diffusion region, the 2nd P+ diffusion region, respectively as the leakage of this PMOS and source electrode, are formed with the grid of this PMOS above the channel region between a P+ diffusion region, the 2nd P+ diffusion region; Two P+ diffusion regions described in N trap one of them, one of them grid short circuit with described PMOS of described two N+ diffusion regions is used for connecing electrostatic end;
In described P trap, be formed with the 3rd P+ diffusion region, the 4th P+ diffusion region, the 3rd N+ diffusion region, the 4th N+ diffusion region, described 3rd P+ diffusion region and the 4th P+ diffusion region are positioned at the 3rd N+ diffusion region and the 4th both sides, N+ diffusion region, described 3rd N+ diffusion region, the 4th N+ diffusion region form a NMOS tube, 3rd N+ diffusion region, the 4th N+ diffusion region, respectively as the leakage of this NMOS tube and source electrode, are formed with the grid of this NMOS tube above the channel region between the 3rd N+ diffusion region, the 4th N+ diffusion region; Two N+ diffusion regions described in P trap one of them, one of them grid short circuit with described NMOS tube of described two P+ diffusion regions be used for earth terminal;
Another one N+ diffusion region in described N trap is with the another one N+ diffusion region short circuit in described P trap;
Another one P+ diffusion region in described N trap is with the another one P+ diffusion region short circuit in described P trap.
Four diffusion regions in described N trap, to described P trap distance from the near to the remote successively: the 2nd N+ diffusion region, the 2nd P+ diffusion region, a P+ diffusion region, a N+ diffusion region; Four diffusion regions in described P trap, to described N trap distance from the near to the remote successively: the 3rd P+ diffusion region, the 3rd N+ diffusion region, the 4th N+ diffusion region, the 4th P+ diffusion region.
First embodiment, as shown in Figure 4, the 2nd P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
Second embodiment, as shown in Figure 5, a P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
3rd embodiment, the 2nd P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
4th embodiment, a P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
5th embodiment, the 2nd P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
6th embodiment, the 2nd P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
7th embodiment, the 2nd P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
8th embodiment, the 2nd P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
9th embodiment, a P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
Tenth embodiment, a P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
11 embodiment, a P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
12 embodiment, a P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
13 embodiment, the 2nd P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
14 embodiment, a P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
15 embodiment, the 2nd P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
16 embodiment, a P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
Electrostatic preventing structure of the present invention, can apply to BCD technique, and total is formed on n type buried layer, forms PMOS and NMOS tube in n type buried layer, utilizes the PNP pipe of its parasitism and NPN pipe as the switch triggering thyristor.After this PNP pipe and NPN pipe are triggered unlatching along with the impact of static discharge (ESD) electric current, also can trigger the PNP triode be made up of the P+ diffusion region in the P+/N trap/P trap in N trap and the NPN triode be made up of the N+ diffusion region in N trap/P trap/P trap simultaneously, enter the Current amplifier state bleed off electric current of positive feedback, and the trigger voltage of the PNP pipe of this PMOS and NMOS tube parasitism and NPN pipe can be adjusted by the impurity injection of technique, and the junction breakdown voltage reaching P+/N trap is identical with the junction breakdown voltage of N+/P trap, easily and effectively can regulate the trigger voltage of electrostatic protection.The trigger voltage of electrostatic preventing structure entirety of the present invention is by the triggering of PMOS and NMOS tube two ore control electrostatic preventing structure, the mode triggered is carried out relative to a kind of knot of single pass-through, electrostatic preventing structure of the present invention is due to the junction area increase for triggering, needed for the trigger current that reaches can be larger, once this trigger current higher than carrying out the electric current of fastening lock test, then effectively can avoid fastening the generation of lock effect and the lock test failure problem of fastening that causes, simultaneously due to the increase of the junction area for triggering, it ties the limiting current also corresponding raising that can bear, this has the protection of the electrostatic induced current of the faster and higher feature of peak current of the rate of climb for some, be compared to common electrostatic preventing structure, electrostatic discharge capacity is strong, its better protecting effect.
Claims (18)
1. an electrostatic preventing structure, comprises a N trap, a P trap, and these two traps are adjacent; It is characterized in that,
In described N trap, be formed with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region, the 2nd N+ diffusion region, a described N+ diffusion region and the 2nd N+ diffusion region are positioned at a P+ diffusion region and the 2nd both sides, P+ diffusion region, a described P+ diffusion region, the 2nd P+ diffusion region form a PMOS, one P+ diffusion region, the 2nd P+ diffusion region, respectively as the leakage of this PMOS and source electrode, are formed with the grid of this PMOS above the channel region between a P+ diffusion region, the 2nd P+ diffusion region; Two P+ diffusion regions described in N trap one of them, one of them grid short circuit with described PMOS of described two N+ diffusion regions is used for connecing electrostatic end;
In described P trap, be formed with the 3rd P+ diffusion region, the 4th P+ diffusion region, the 3rd N+ diffusion region, the 4th N+ diffusion region, described 3rd P+ diffusion region and the 4th P+ diffusion region are positioned at the 3rd N+ diffusion region and the 4th both sides, N+ diffusion region, described 3rd N+ diffusion region, the 4th N+ diffusion region form a NMOS tube, 3rd N+ diffusion region, the 4th N+ diffusion region, respectively as the leakage of this NMOS tube and source electrode, are formed with the grid of this NMOS tube above the channel region between the 3rd N+ diffusion region, the 4th N+ diffusion region; Two N+ diffusion regions described in P trap one of them, one of them grid short circuit with described NMOS tube of described two P+ diffusion regions be used for earth terminal;
Another one N+ diffusion region in described N trap is with the another one N+ diffusion region short circuit in described P trap;
Another one P+ diffusion region in described N trap is with the another one P+ diffusion region short circuit in described P trap;
Described N trap and P trap entirety are placed in a n type buried layer.
2. electrostatic preventing structure according to claim 1, is characterized in that, four diffusion regions in described N trap, to described P trap distance from the near to the remote successively: the 2nd N+ diffusion region, the 2nd P+ diffusion region, a P+ diffusion region, a N+ diffusion region; Four diffusion regions in described P trap, to described N trap distance from the near to the remote successively: the 3rd P+ diffusion region, the 3rd N+ diffusion region, the 4th N+ diffusion region, the 4th P+ diffusion region.
3. electrostatic preventing structure according to claim 2, is characterized in that, the 2nd P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
4. electrostatic preventing structure according to claim 2, is characterized in that, a P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
5. electrostatic preventing structure according to claim 2, is characterized in that, the 2nd P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
6. electrostatic preventing structure according to claim 2, is characterized in that, a P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
7. electrostatic preventing structure according to claim 2, is characterized in that, the 2nd P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
8. electrostatic preventing structure according to claim 2, is characterized in that, the 2nd P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
9. electrostatic preventing structure according to claim 2, is characterized in that, the 2nd P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
10. electrostatic preventing structure according to claim 2, is characterized in that, the 2nd P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
11. electrostatic preventing structures according to claim 2, is characterized in that, a P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
12. electrostatic preventing structures according to claim 2, is characterized in that, a P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
13. electrostatic preventing structures according to claim 2, is characterized in that, a P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
14. electrostatic preventing structures according to claim 2, is characterized in that, a P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
15. electrostatic preventing structures according to claim 2, is characterized in that, the 2nd P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
16. electrostatic preventing structures according to claim 2, is characterized in that, a P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 3rd N+ diffusion region described in P trap, described 4th P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 4th N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 3rd P+ diffusion region short circuit described in P trap.
17. electrostatic preventing structures according to claim 2, is characterized in that, the 2nd P+ diffusion region described in N trap, described 2nd N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; A N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; A P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
18. electrostatic preventing structures according to claim 2, is characterized in that, a P+ diffusion region described in N trap, a described N+ diffusion region are used for connecing electrostatic end with the grid short circuit of described PMOS; 4th N+ diffusion region described in P trap, described 3rd P+ diffusion region are used for earth terminal with the grid short circuit of described NMOS tube; 2nd N+ diffusion region described in N trap is with the 3rd N+ diffusion region short circuit described in P trap; 2nd P+ diffusion region described in N trap is with the 4th P+ diffusion region short circuit described in P trap.
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| CN201110103518.4A CN102760731B (en) | 2011-04-25 | 2011-04-25 | Electrostatic preventing structure |
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| CN201110103518.4A CN102760731B (en) | 2011-04-25 | 2011-04-25 | Electrostatic preventing structure |
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| CN102760731A CN102760731A (en) | 2012-10-31 |
| CN102760731B true CN102760731B (en) | 2015-12-02 |
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| CN201110103518.4A Active CN102760731B (en) | 2011-04-25 | 2011-04-25 | Electrostatic preventing structure |
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| CN103745973B (en) * | 2013-12-26 | 2016-06-01 | 中国科学院微电子研究所 | A kind of ESD protective device and be applicable to the ESD circuit of battery management chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6015992A (en) * | 1997-01-03 | 2000-01-18 | Texas Instruments Incorporated | Bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits |
| CN1445849A (en) * | 2002-03-17 | 2003-10-01 | 联华电子股份有限公司 | Electrostatic discharge protection circuit |
| CN101442047A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Electrostatic protection structure for low trigger voltage thyristor |
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| KR101006514B1 (en) * | 2004-04-28 | 2011-01-07 | 매그나칩 반도체 유한회사 | A silicon controlled rectifier for protecting the device in a electrostatic discharge |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6015992A (en) * | 1997-01-03 | 2000-01-18 | Texas Instruments Incorporated | Bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits |
| CN1445849A (en) * | 2002-03-17 | 2003-10-01 | 联华电子股份有限公司 | Electrostatic discharge protection circuit |
| CN101442047A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Electrostatic protection structure for low trigger voltage thyristor |
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