CN103745973B - A kind of ESD protective device and be applicable to the ESD circuit of battery management chip - Google Patents
A kind of ESD protective device and be applicable to the ESD circuit of battery management chip Download PDFInfo
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- CN103745973B CN103745973B CN201310733250.1A CN201310733250A CN103745973B CN 103745973 B CN103745973 B CN 103745973B CN 201310733250 A CN201310733250 A CN 201310733250A CN 103745973 B CN103745973 B CN 103745973B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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Abstract
The present invention relates to ESD technical field, disclose a kind of ESD protective device and be applicable to the ESD circuit of battery management chip. Wherein, ESD protective device comprises: substrate, embedding layer, high pressure N trap district, high pressure P trap district, low pressure p-well region and low pressure NMOS tube; Embedding layer is on substrate; High pressure P trap district is on embedding layer; Low pressure p-well region is in high pressure P trap district; Low pressure NMOS tube is in low pressure p-well region; High pressure N trap district is in the outside in high pressure P trap district, and contacts with embedding layer; The grid of low pressure NMOS tube is connected with source electrode, and the positive pole being connected in high pressure P trap district as protection device; The drain electrode of low pressure NMOS tube is connected with high pressure N trap district, as the negative pole of protection device. The two ends of the ESD protective device in the present invention all can connect high level, and the ESD protective device in ESD circuit is connected with the two ends of battery correspondingly, it is achieved that to the esd protection of battery management chip.
Description
Technical field
The present invention relates to ESD technical field, mainly it is applicable to ESD protective device and is applicable to the ESD circuit of battery management chip.
Background technology
Static discharge (ElectrostaticDischarge, ESD) is one of important factor causing wafer damage. The generation of static discharge, is caused by artificial origin mostly, but is difficult to avoid again. Chip is in the process manufacturing, produce, test, deposit and carrying, and electrostatic can be accumulated in human body, instrument and storage equipment, and even chip itself also can gather electrostatic. And people are in unwitting situation, these objects contacted with each other, defines discharge path, make chip suffer excessive electric stress
(ElectricalOverstress, EOS) and damage. In order to avoid chip to damage because of static discharge, it is necessary to increase ESD circuit in chip, for rushing down of static electric charge puts offer low-resistance path.
The design of ESD circuit needs to consider more factor. Basic demand effective electric charge can be provided to rush down put path, and can not affect the normal operation of circuit. In addition, also to be considered circuit area, the need of increasing the factors such as technique mask layer, the time delay problem of speed sensitive pin and latchup.
See Fig. 1, the input pin (Inputpad) of existing simulating signal pin ESD circuit comprises ESDpmos1, ESDnmos1 and the resistance R that grid is connected with source electrode. Output pin (Outputpad) comprises ESDpmos2, ESDnmos2 that grid is connected with source electrode. Can when there is ESD in the Powerclamp circuit being connected between VDDrail and GNDrail, a large amount of electric current of conducting, and within maintaining the maximum voltage value that the voltage between VDDrail and GNDrail can bear at device. If there is static discharge between Inputpad and Outputpad, rushing down of electric current puts path as shown in Fig. 1 direction of arrow, Inputpad inflow current, the parasitic diode forward conducting of ESDpmos1, performance low-resistance characteristic. R selects 1K resistance usually, and therefore electric current can't flow into inner circuit, and electric current flows into Powerclamp circuit along VDDrail, and the parasitic diode eventually passing through ESDnmos2 flows out from Outputpad.
A battery management chip needs management multiple batteries usually, and as shown in Figure 2, the maximum voltage of series-connected cell is as the power supply VH of chip, and the minimum voltage of series-connected cell is as the ground of chip in the connection of chip pin and battery. Owing to be detected the voltage of every batteries, therefore the positive and negative electrode of every batteries is all connected with chip pin. Calculating according to a batteries 3V pressure drop, for pin Ch2, if there being 6 batteries below Ch2 pin, voltage is exactly 18V, and the voltage of pin adjacent with it downwards is 15V, and usually has a pin withstand high pressures due to existing high pressure ESD device; Another pin ground connection, can not withstand high pressures, can both the ESD protective device of withstand high pressures it is thus desirable to design a kind of any two ends. In addition, when there is static discharge, the voltage that pressure reduction can not exceed chip internal circuits, device can bear between arbitrary neighborhood two battery pin.
In sum, it is necessary to design a kind of ESD structure being applicable to battery management chip.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of ESD protective device and is applicable to the ESD circuit of battery management chip, and battery management chip can be carried out esd protection by it.
For solving the problems of the technologies described above, the present invention provides a kind of ESD protective device, comprising: substrate, embedding layer, high pressure N trap district, high pressure P trap district, low pressure p-well region and low pressure NMOS tube; Described embedding layer is over the substrate; Described high pressure P trap district is on described embedding layer; Described low pressure p-well region is in described high pressure P trap district; Described low pressure NMOS tube is in described low pressure p-well region; Described high pressure N trap district is in the outside in described high pressure P trap district, and contacts with described embedding layer; The grid of described low pressure NMOS tube is connected with source electrode, and the positive pole being connected in described high pressure P trap district as protection device; The drain electrode of described low pressure NMOS tube is connected with described high pressure N trap district, as the negative pole of protection device.
Present invention also offers a kind of ESD circuit being applicable to battery management chip, comprising: at least one ESD protective device as claimed in claim 1; The positive pole of ESD protective device separately respectively negative pole with battery to be detected be connected; The negative pole of ESD protective device separately respectively positive pole with described battery to be detected be connected; Described each ESD protective device is connected mutually, composition series circuit; One end of described series circuit is connected with the power pins of battery management chip; The other end ground connection of described series circuit, and be connected with described battery management chip.
Further, also comprise: the first diode and the 2nd diode; The positive pole of described battery to be detected is connected with the first power pins of described battery management chip and detection pin; Described first diode and described 2nd diode is positive and negative is connected in parallel between described first power pins and described detection pin.
Further, also comprise: a pmos pipe, the 2nd pmos pipe, a nmos pipe and the 2nd nmos manage; The grid of a described pmos pipe is connected with source electrode, and is connected with the first power pins of described battery management chip, and the drain electrode of a pmos pipe is connected with the 2nd power pins of described battery management chip; The grid of a described nmos pipe is connected with source electrode, and ground connection; The drain electrode of a described nmos pipe is connected with the 2nd power pins of described battery management chip; The grid of described 2nd pmos pipe and source electrode connect, and are connected with the 2nd power pins of described battery management chip, and the drain electrode of the 2nd pmos pipe is connected with the low-voltage signal pin of described battery management chip; The grid of described 2nd nmos pipe is connected with source electrode, and ground connection, the drain electrode of the 2nd nmos pipe is connected with the low-voltage signal pin of described battery management chip.
The useful effect of the present invention is:
ESD protective device provided by the invention and be applicable to the ESD circuit of battery management chip, connects high level by the N trap district of ESD protective device, and the ESD protective device in ESD circuit is connected with the two ends of battery correspondingly. When chip normal operation, the positive and negative terminal of ESD protective device is that reference voltage all can reach tens volts of high pressure taking ground; When there is static discharge, the voltage that pressure reduction can not exceed chip internal circuits, device can bear between the arbitrary neighborhood two-port of ESD protective device, it is achieved that to the esd protection of battery management chip.
Accompanying drawing explanation
Fig. 1 is the schematic circuit of existing ESD circuit;
Fig. 2 is the connection diagram of battery management chip and battery;
The section of structure of the ESD protective device that Fig. 3 provides for the embodiment of the present invention;
The structural representation of the NPN pipe that Fig. 4 goes out for the ESD protective device parasitism provided by the embodiment of the present invention;
The schematic circuit of the ESD circuit being applicable to battery management chip that Fig. 5 provides for the embodiment of the present invention;
Fig. 6 for the ESD circuit being applicable to battery management chip provided by the embodiment of the present invention carry out positive negative pulse stuffing between battery pin and VH power supply test time, rush down the path figure of discharge stream;
Fig. 7 for the ESD circuit being applicable to battery management chip provided by the embodiment of the present invention carry out positive negative pulse stuffing between battery pin and 5V power supply test time, rush down the path figure of discharge stream;
Fig. 8 for the ESD circuit being applicable to battery management chip provided by the embodiment of the present invention carry out positive negative pulse stuffing between battery pin and ground test time, rush down the path figure of discharge stream;
Fig. 9 for the ESD circuit being applicable to battery management chip provided by the embodiment of the present invention carry out positive negative pulse stuffing between battery pin and low-voltage signal pin Bn test time, rush down the path figure of discharge stream;
Figure 10 for the ESD circuit being applicable to battery management chip provided by the embodiment of the present invention carry out battery pin positive negative pulse stuffing each other test time, rush down the path figure of discharge stream.
Embodiment
Technique means and effect that predetermined goal of the invention is taked is reached for setting forth the present invention further; below in conjunction with accompanying drawing and better embodiment, ESD protective device foundation the present invention proposed and the embodiment and the principle of work that being applicable to the ESD circuit of battery management chip are described in detail.
See Fig. 3, the ESD protective device that the embodiment of the present invention provides, comprising: P type substrate (Psub), N-type embedding layer (BN), high pressure N trap district (HVnwell), high pressure P trap district (HVpwell), low pressure p-well region (pwell) and low pressure ESDNMOS pipe; N-type embedding layer is in P type substrate; High pressure P trap district is on N-type embedding layer; Low pressure p-well region is in high pressure P trap district; Low pressure ESDNMOS pipe is in low pressure p-well region; High pressure N trap district is in the outside in high pressure P trap district, and contacts with N-type embedding layer; High pressure N trap district and N-type embedding layer are completely isolated to P type substrate and high pressure P trap district. The grid (Gate) of the low pressure ESDNMOS pipe in low pressure p-well region is connected with source electrode (Source), and the positive pole being connected in high pressure P trap district as protection device; The drain electrode (drain) of the low pressure ESDNMOS pipe in low pressure p-well region is connected with high pressure N trap district, as the negative pole of protection device. In the present embodiment, high pressure N trap district connects the high level of 23V, and high pressure P trap district and low pressure p-well region connect the level of 20V.
When ESD protective device forward conduction, only there is the pressure drop (voltage drop value depends on the manufacture craft of device, such as material, doping content, hierarchical structure etc.) of several hundred millivolts; When ESD protective device reverse-conducting; (magnitude of voltage depends on the manufacture craft of device for voltage that the voltage at ESD protective device two ends generally can bear lower than chip internal circuits, device; such as material, doping content, hierarchical structure etc.), the electric current that conducting simultaneously is a large amount of. Owing to, between high pressure N trap district and ground, can bear high pressure between high pressure P trap district and ground, therefore the positive and negative two ends of ESD protective device all can be born taking ground is the high-voltage of datum.
Specifically, when the cathode voltage of ESD protective device is constant, when cathode voltage raises, the pn that pwell and drain electrode are formed ties forward conduction, it is provided that low resistance current path, positive and negative electrode pressure drop is about several hundred millivolts, and different process can change to some extent. When the cathode voltage of ESD protective device is constant, when cathode voltage raises, see Fig. 4, ESD protective device parasitism goes out NPN pipe. Diode reverse conducting between the collector electrode of NPN pipe and base stage, the electric current flowing through base stage makes base stage voltage raise. When being elevated to the pn knot can opened between base stage and emtting electrode when base stage voltage, parasitic NPN pipe conducting. If continuing to raise cathode voltage, being also exactly the collector voltage raising parasitic NPN pipe, the electric current now flowing through parasitic NPN pipe increases. The design manual that theres is provided according to technique manufacturer and need the esd protection grade that reaches, it is possible to reasonably design length and the width of the raceway groove of ESD protective device, thus ESD electric current is fully rushed down and puts and do not cause the damage of ESD protective device. Owing to not needing collector electrode to keep high-voltage to maintain the conducting state of device after parasitic NPN pipe conducting; therefore collector voltage can decline to some extent; this kind of reentry phenomenon (snapback) is that ESD device often has; this also makes ESD protective device when circulating a large amount of electric current; voltage maintains lower level, protects the circuit of chip internal.
See Fig. 5, the ESD circuit being applicable to battery management chip that the embodiment of the present invention provides, comprising: at least one above-mentioned ESD protective device A, the first diode, the 2nd diode, a HVESDpmos1 pipe, the 2nd ESDpmos2 pipe, an ESDnmos1 pipe and the 2nd ESDnmos2 manage; The negative pole of the battery that the positive pole of ESD protective device A is to be detected with single-unit correspondingly respectively separately is connected; The positive pole of the battery that the negative pole of ESD protective device A is to be detected with single-unit correspondingly respectively separately is connected. Each ESD protective device A connects mutually, composition series circuit; One end of series circuit is connected with first power pins (VH) of battery management chip; The other end ground connection (GND) of series circuit, and be connected with battery management chip. In the present embodiment, battery to be detected is series-connected cell. The positive pole (maximum voltage) of battery to be detected is connected with first power pins (VH) of battery management chip and detection pin (CH). Owing to the first power pins VH flowing through whole electric currents that chip consumes, it is contemplated that to the existence of dead resistance, the voltage of the first power pins VH is usually a little less than the maximum voltage of series-connected cell. Therefore, in order to improve accuracy of detection, using the CH pin of chip as detection pin. Owing to no current flows through from CH pin, therefore CH pin truly reflects the maximum voltage of series-connected cell, it is to increase accuracy of detection. First diode and the 2nd diode positive and negative be connected in parallel on the first power pins VH and detection pin CH between; The negative pole (minimum voltage) of battery to be detected is connected with the ground connection pin GND of battery management chip. Grid and the source electrode of the one HVESDpmos1 pipe link together, and are connected with first power pins (VH) of battery management chip. The drain electrode of the one HVESDpmos1 pipe is connected with the 2nd power pins (5V power pins) of battery management chip; Grid and the source electrode of the one ESDnmos1 pipe link together, and are connected to ground GND; The drain electrode of the one ESDnmos1 pipe is connected with the 5V power pins of battery management chip. Grid and the source electrode of the 2nd ESDpmos2 pipe link together, and are connected with the 5V power pins of battery management chip, and the drain electrode of the 2nd ESDpmos2 pipe is connected with the low-voltage signal pin Bn of battery management chip; Grid and the source electrode of the 2nd ESDnmos2 pipe link together, and are connected to ground GND, and the drain electrode of the 2nd ESDnmos2 pipe is connected to the low-voltage signal pin Bn of battery management chip.
Owing to static discharge phenomenon has randomness, therefore all need between any two pins of battery management chip ESD rush down put path could ensure chip manufacturing, produce, test, deposit, in the process such as carrying from infringement. In actual ESD tests, at least comprise the test of the positive negative pulse stuffing between battery pin and power supply, the positive negative pulse stuffing test between battery pin and ground, battery pin positive negative pulse stuffing test each other.
See Fig. 5, broken box internal representation chip, the peripheral circuit of broken box external representation chip and pin information. Power pins has two, i.e. VH pin and 5V pin (5V is for the low-voltage simulation circuit of chip internal provides power supply, is system design needs, also relevant with the low-voltage device selected). Owing to VH voltage is the maximum voltage of series-connected cell, when battery is load supplying or during discharge and recharge, VH voltage has change by a relatively large margin, and magnitude of voltage is higher, the mimic channel that discomfort is preferably chip internal is powered, and therefore utilizes VH voltage to produce the mimic channel that 5V voltage is chip internal and powers. Bn pin take 5V as the low-voltage signal pin of ESD power supply. The chip pin connected on series-connected cell node is as mentioned before.
For the arbitrary pin CHn on battery strings node, describe rushing down of ESD electric current and put path, comprise following situation: the positive and negative esd pulse between CHn pin and power supply, positive and negative esd pulse between CHn pin and ground, positive and negative esd pulse between CHn pin and low-voltage signal pin Bn, battery strings node pin positive and negative esd pulse each other.
The ESD circuit being applicable to battery management chip provided by the embodiment of the present invention carries out the test of the positive negative pulse stuffing between battery pin and power supply VH, as shown in Figure 6, and the said current dumping path between any battery strings node pin CHn and power supply VH. Solid line pulse meter on CHn pin is shown in CHn pin and adds just to esd pulse, VH pin ground connection, and ESD electric current path is as shown in solid line arrow, and ESD electric current positive flow crosses the ESD protective device A of series connection, flows out VH pin by forward diode D. Dashed pulse on CHn pin represents to add at CHn pin to be born to esd pulse, VH pin ground connection, and ESD electric current path is as the dotted line arrows; ESD electric current flows into from VH pin; positive flow crosses diode D, flows counterflow through the ESD protective device A of series connection, flows out by CHn pin.
The ESD circuit being applicable to battery management chip provided by the embodiment of the present invention carries out the test of the positive negative pulse stuffing between battery pin and power supply 5V, as shown in Figure 7, is the ESD said current dumping path between any battery strings node pin CHn and power supply 5V. Solid line pulse meter on CHn pin is shown on CHn pin to add ESD positive pulse; 5V pin ground connection; ESD current path is as shown in solid line arrow, and ESD electric current flows counterflow through the ESD protective device A of series connection to ground GND, then flows out pin 5V by the parasitic diode of low pressure ESDnmos1 on 5V pin. Dashed pulse on CHn pin represents and adds ESD negative pulse on CHn pin, and 5V pin ground connection, ESD electric current flows to CHn by 5V pin. ESD electric current path is by shown in dotted line arrow, and the parasitic diode that ESD electric current flows through high pressure ESD device HVESDpmos1 by 5V pin, to supply lead VH, flows through forward diode D, then flows counterflow through the ESD protective device A of series connection, and flow out by CHn pin.
The ESD circuit being applicable to battery management chip provided by the embodiment of the present invention carries out the test of the positive negative pulse stuffing between battery pin and ground, as shown in Figure 8, is the ESD said current dumping path between any battery strings node pin CHn and ground (GND). Solid line pulse meter on CHn pin is shown on CHn pin to add ESD positive pulse, GND pin ground connection, and ESD electric current flows to ground by CHn. As shown in solid line arrow in figure, ESD electric current reverse direction flow through series connection ESD protective device A arrive (GND) flow out; Dashed pulse on CHn pin represents and adds ESD negative pulse on CHn pin, GND pin ground connection, and ESD electric current flows to CHn by GND. As indicated by a dashed arrow in the figure, ESD electric current, is flowed out by CHn pin just to the ESD protective device A by series connection by GND pin.
The ESD circuit being applicable to battery management chip provided by the embodiment of the present invention carries out the test of the positive negative pulse stuffing between battery pin and low-voltage signal pin Bn, as shown in Figure 9, it is the ESD said current dumping path between any battery strings node pin CHn and low-voltage signal pin Bn. Solid line pulse meter on CHn pin is shown on CHn pin to add ESD positive pulse, and Bn pin ground connection, ESD electric current flows to Bn by CHn. As shown in solid line arrow in figure, the ESD protective device A that ESD electric current is flowed counterflow through series connection by CHn pin to (GND), then flow out Bn pin by the parasitic diode of the ESDnmos2 in Bn pin ESD structure. Dashed pulse on CHn pin represents and adds negative pulse on CHn pin, and Bn pin ground connection, ESD electric current flows to CHn by Bn. As indicated by a dashed arrow in the figure; ESD electric current is flowed into by Bn pin; flow through the parasitic diode of the ESDpmos2 in Bn pin ESD structure; flow through the parasitic diode of the HVESDpmos1 in 5V pin ESD structure again; arrive VH supply lead, then the ESD protective device A back through series connection is flowed out by CHn pin.
As shown in Figure 10, it is the ESD said current dumping path between any two battery strings node pins. Any two pins is respectively CHn1 and CHn2. When beating positive esd pulse between CHn1 and CHn2, ESD electric current flows to CHn2 by CHn1, and as shown in solid line arrow path, its reverse-conducting ESD protective device A, ESD electric current directly flows to CHn2 by CHn1. When beating negative esd pulse between CHn1 and CHn2, ESD electric current flows to CHn1 by CHn2. As indicated by a dashed arrow in the figure, ESD electric current crosses the ESD protective device A of series connection by CHn2 positive flow, flows out by CHn1 pin.
Here it should be noted that, although when there is static discharge, ESD electric current can be selected low-resistance path to rush down to put, but rush down that to put path be not unique usually, above content merely depict a kind of possible ESD said current dumping path, and rushing down of ESD electric current is put path and do not made concrete restriction by the embodiment of the present invention.
Also it should be noted that, the embodiment of the present invention take battery management chip as embodiment, but it is not limited to battery management chip, need to carry out high common mode at some, the circuit of difference signal detection is suitable for too, concrete circuit connecting relation is determined by respective circuit structure and detection demand, does not make concrete restriction here.
The ESD protective device that the embodiment of the present invention provides and be applicable to the ESD circuit of battery management chip, connects high level by the N trap district of ESD protective device A, and is connected with the two ends of single battery correspondingly by the ESD protective device A in ESD circuit. When chip normal operation, the positive and negative terminal of ESD protective device A is that reference voltage all can reach tens volts of high pressure taking ground; When there is static discharge, the voltage that pressure reduction can not exceed chip internal circuits, device can bear between the arbitrary neighborhood two-port of ESD protective device A, it is achieved that to the esd protection of battery management chip.
It should be noted last that, above embodiment is only in order to illustrate the technical scheme of the present invention and unrestricted, although with reference to example to invention has been detailed explanation, it will be understood by those within the art that, the technical scheme of the present invention can be modified or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the right of the present invention.
Claims (3)
1. one kind is applicable to the ESD circuit of battery management chip, it is characterised in that, comprising: at least one ESD protective device; Described ESD protective device, comprising: substrate, embedding layer, high pressure N trap district, high pressure P trap district, low pressure p-well region and low pressure NMOS tube; Described embedding layer is over the substrate; Described high pressure P trap district is on described embedding layer; Described low pressure p-well region is in described high pressure P trap district; Described low pressure NMOS tube is in described low pressure p-well region; Described high pressure N trap district is in the outside in described high pressure P trap district, and contacts with described embedding layer; The grid of described low pressure NMOS tube is connected with source electrode, and the positive pole being connected in described high pressure P trap district as protection device; The drain electrode of described low pressure NMOS tube is connected with described high pressure N trap district, as the negative pole of protection device; The positive pole of ESD protective device separately respectively negative pole with battery to be detected be connected; The negative pole of ESD protective device separately respectively positive pole with described battery to be detected be connected; Described each ESD protective device is connected mutually, composition series circuit; One end of described series circuit is connected with the power pins of battery management chip; The other end ground connection of described series circuit, and be connected with described battery management chip.
2. it is applicable to the ESD circuit of battery management chip as claimed in claim 1, it is characterised in that, also comprise: the first diode and the 2nd diode; The positive pole of described battery to be detected is connected with the first power pins of described battery management chip and detection pin; Described first diode and described 2nd diode is positive and negative is connected in parallel between described first power pins and described detection pin.
3. it is applicable to the ESD circuit of battery management chip as claimed in claim 2, it is characterised in that, also comprise: a pmos pipe, the 2nd pmos pipe, a nmos pipe and the 2nd nmos manage; The grid of a described pmos pipe is connected with source electrode, and is connected with the first power pins of described battery management chip, and the drain electrode of a pmos pipe is connected with the 2nd power pins of described battery management chip; The grid of a described nmos pipe is connected with source electrode, and ground connection; The drain electrode of a described nmos pipe is connected with the 2nd power pins of described battery management chip; The grid of described 2nd pmos pipe and source electrode connect, and are connected with the 2nd power pins of described battery management chip, and the drain electrode of the 2nd pmos pipe is connected with the low-voltage signal pin of described battery management chip; The grid of described 2nd nmos pipe is connected with source electrode, and ground connection, the drain electrode of the 2nd nmos pipe is connected with the low-voltage signal pin of described battery management chip.
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| CN201310733250.1A CN103745973B (en) | 2013-12-26 | 2013-12-26 | A kind of ESD protective device and be applicable to the ESD circuit of battery management chip |
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| US5760448A (en) * | 1993-12-27 | 1998-06-02 | Sharp Kabushiki Kaisha | Semiconductor device and a method for manufacturing the same |
| CN1455454A (en) * | 2002-04-29 | 2003-11-12 | 联华电子股份有限公司 | Electrostatic discharge protective circuit structure and manufacturing method thereof |
| CN101399264A (en) * | 2007-05-17 | 2009-04-01 | 沙诺夫公司 | Cdm ESD protection for integrated circuits |
| CN102760731A (en) * | 2011-04-25 | 2012-10-31 | 上海华虹Nec电子有限公司 | Static protective structure |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5760448A (en) * | 1993-12-27 | 1998-06-02 | Sharp Kabushiki Kaisha | Semiconductor device and a method for manufacturing the same |
| CN1455454A (en) * | 2002-04-29 | 2003-11-12 | 联华电子股份有限公司 | Electrostatic discharge protective circuit structure and manufacturing method thereof |
| CN101399264A (en) * | 2007-05-17 | 2009-04-01 | 沙诺夫公司 | Cdm ESD protection for integrated circuits |
| CN102760731A (en) * | 2011-04-25 | 2012-10-31 | 上海华虹Nec电子有限公司 | Static protective structure |
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Effective date of registration: 20171027 Address after: Beijing 100101 Chaoyang District Olympic Forest Park South Gate Patentee after: Zhongke era technology Co., Ltd. Address before: 100029 Beijing city Chaoyang District Beitucheng West Road No. 3 Institute of Microelectronics Patentee before: Institute of Microelectronics, Chinese Academy of Sciences |