CN104362606A - Electrostatic discharge power source clamping circuit for integrated circuit and control method thereof - Google Patents
Electrostatic discharge power source clamping circuit for integrated circuit and control method thereof Download PDFInfo
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- CN104362606A CN104362606A CN201410664096.1A CN201410664096A CN104362606A CN 104362606 A CN104362606 A CN 104362606A CN 201410664096 A CN201410664096 A CN 201410664096A CN 104362606 A CN104362606 A CN 104362606A
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- nmos pass
- pass transistor
- inverter
- transistor
- nmos
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Abstract
The invention discloses an electrostatic discharge power source clamping circuit for an integrated circuit and a control method of the electrostatic discharge power source clamping circuit. A design circuit with an NMOS transistor, a BigFET, a resistor and phase inverters combined is adopted, the NMOS transistor is used for replacing a traditional resistor and capacitor, the BigFET is used for releasing electrostatic discharge (ESD) currents, it is guaranteed that the electrostatic discharge (ESD) currents can be effectively discharged, meanwhile, the design territory area is greatly reduced, the chip area is saved, the two phase inverters are adopted in the circuit to form positive feedback, and the circuit cannot generate electric leakage in the normal work and use process.
Description
Technical field
The present invention relates to a kind of power clamping circuit and control method thereof, especially a kind of static discharge power clamping circuit for integrated circuit and control method thereof.
Background technology
At present, the power clamping circuit that general RC triggers, in order to can effectively static electricity discharge electric discharge (ESD) electric current, RC time constant needs to be designed to 0.5us-1us, so large RC time constant needs larger electric capacity and resistance, so when IC Layout, resistance and electric capacity need larger chip area, cause the waste of chip area.
Summary of the invention
In order to solve the problems of the technologies described above, the invention provides a kind of static discharge power clamping circuit for integrated circuit and control method thereof, by arranging the inverter, BigFET transistor, nmos pass transistor and the resistance that are made up of NOMS transistor and PMOS transistor in circuit, solve the technical problem of the waste chip area existed in prior art.
To achieve these goals, the technical solution used in the present invention is: for the static discharge power clamping circuit of integrated circuit, the inverter including nmos pass transistor, PMOS transistor, resistance and be made up of nmos pass transistor and PMOS transistor, is characterized in that:
Nmos pass transistor
grid be connected on power supply, source electrode with drain electrode be connected;
Nmos pass transistor
grid and drain electrode be connected to nmos pass transistor
source electrode and drain electrode tie point on, nmos pass transistor
source electrode has been connected to nmos pass transistor
drain electrode on, nmos pass transistor
source ground;
PMOS transistor
with nmos pass transistor
composition inverter
, PMOS transistor
with nmos pass transistor
composition inverter
, inverter
input be connected to nmos pass transistor
grid, output connect inverter
input, PMOS transistor
and PMOS transistor
connect power supply, nmos pass transistor
and nmos pass transistor
ground connection;
Nmos pass transistor
drain electrode be connected to inverter
input, nmos pass transistor
grid and nmos pass transistor
grid be connected to device anyway together
output, nmos pass transistor
source ground;
PMOS transistor
grid be connected on inverter
output, drain electrode connect power supply, source electrode is connected to inverter
output;
Nmos pass transistor
grid be connected to inverter
output, drain electrode connect power supply, source ground;
Resistance one end is connected to nmos pass transistor
grid, one end ground connection.
Described nmos pass transistor
for BigFET transistor.For the control method of the static discharge power clamping circuit of integrated circuit, it is characterized in that:
When there is static discharge in circuit:
Electrostatic Discharge pulse applies between vdd and vss, has the nmos pass transistor of electric capacity effect
1 makes circuit transient voltage not suddenly change, NMOS
2 and NMOS
3 are in closed condition, infinite, NMOS
the gate voltage of 3 is low level, NMOS
the source and drain level resistance effect of 3 makes inverter
the charge discharging resisting of the input of 11 is slow, keeps inverter
the input terminal voltage of 11 is high level, inverter
the output of 11 is low-voltage, inverter
the output of 12 is high voltage, nmos pass transistor
the grid node of 10 is high voltage, nmos pass transistor
10 open conducting, static electricity discharge electric discharge (ESD) electric current;
When circuit normally works:
Inverter
the input of 12 is high level, and output is low level, PMOS transistor
7 open, and make inverter
the output of 11 is forced to draw high into high level, nmos pass transistor
4 open, and make inverter
the input terminal voltage of 11 is forced to low level, and form positive feedback, resistance 13 makes nmos pass transistor
the gate voltage of 10 is low level, nmos pass transistor
10 close, and do not produce electric leakage.
Beneficial effect of the present invention is: the present invention adopts said structure and control method thereof, nmos pass transistor is used to replace traditional resistance and electric capacity, use BigFET transistor release electrostatic electric discharge (ESD) electric current, guarantee effective static electricity discharge electric discharge (ESD) electric current while, substantially reduce design layout area, save chip area, applied two inverters in circuit and form positive feedback, made circuit can not produce electric leakage when normal work uses.
Accompanying drawing explanation
Fig. 1: be structural representation of the present invention.
Fig. 2: be result of use analogous diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail.
As shown in Figure 1 for the static discharge power clamping circuit of integrated circuit, the inverter including nmos pass transistor, PMOS transistor, resistance and be made up of nmos pass transistor and PMOS transistor, its structure is:
Nmos pass transistor
the grid of 1 is connected on power supply, and source electrode is connected with drain electrode;
Nmos pass transistor
grid and the drain electrode of 2 are connected to nmos pass transistor
on the source electrode of 1 and the tie point of drain electrode, nmos pass transistor
2 source electrodes have been connected to nmos pass transistor
in the drain electrode of 3, nmos pass transistor
the source ground of 3;
PMOS transistor
5 and nmos pass transistor
6 composition inverters
11, PMOS transistor
8 and nmos pass transistor
9 composition inverters
12, inverter
the input of 11 is connected to nmos pass transistor
the grid of 2, output connects inverter
the input of 12, PMOS transistor
5 and PMOS transistor
8 connect power supply, nmos pass transistor
6 and nmos pass transistor
9 ground connection;
Nmos pass transistor
the drain electrode of 4 is connected to inverter
the input of 11, nmos pass transistor
the grid of 4 and nmos pass transistor
the grid of 3 is connected to inverter together
the output of 11, nmos pass transistor
the source ground of 4;
PMOS transistor
the grid of 7 is connected on inverter
the output of 12, drain electrode connects power supply, and source electrode is connected to inverter
the output of 11;
Nmos pass transistor
10 is BigFET transistor, and its grid is connected to inverter
the output of 12, drain electrode connects power supply, source ground;
Resistance 13 one end is connected to nmos pass transistor
the grid of 10, one end ground connection.
Electrostatic Discharge pulse applies between vdd and vss, nmos pass transistor
1 serves as electric capacity uses, and its transient voltage can not suddenly change, inverter
the input terminal voltage of 11 is high level, NMOS
2 and NMOS
3 all do not open, infinite, and this high level can keep a period of time, inverter
the output of 11 is low-voltage, inverter
the output of 12 is high voltage, nmos pass transistor
the grid node of 10 is high voltage, nmos pass transistor
10 open conducting Electrostatic Discharge electric current.When Electrostatic Discharge pulse just applies between vdd and vss, due to NMOS
the gate voltage of 3 is low level, NMOS
the source and drain resistance ratio of 3 is comparatively large, inverter
the charge discharging resisting of the input of 11 is slow, thus can maintain inverter
the time that the input high level of 11 is long, nmos pass transistor
10 can open long time static electricity discharge electric discharge (ESD) electric current.NMOS
2 and NMOS
3 larger source and drain resistance make nmos pass transistor
1 charge discharging resisting is slow, makes nmos pass transistor
10 open ON time is greater than HBM esd pulse width, ESD electric current of can all releasing.
The NMOS of grid leak short circuit
2 and NMOS
3 serve as the resistance in R-C testing circuit, maintain nmos pass transistor
10 conducting 0.5us-1us, thus can static electricity discharge electric discharge (ESD) all electric currents effectively.
Resistance 13 is used for, when circuit normally powers on, making nmos pass transistor
the gate voltage of 10 is low level, nmos pass transistor
10 close, and can not produce electric leakage.
PMOS transistor
the effect of 7 is when circuit normally powers on, inverter
the input of 12 is high level, and output is low level, PMOS transistor
7 open, and make inverter
the output of 11 is forced to draw high as high level, thus forms positive feedback, makes nmos pass transistor
10 more easily close, and can not produce electric leakage.
Nmos pass transistor
the effect of 4 is when circuit normally powers on, inverter
the output of 11 is high level, nmos pass transistor
4 open, and make inverter
the input terminal voltage of 11 is forced to low level, thus forms positive feedback, makes nmos pass transistor
10 more easily close, and can not produce electric leakage.
After HBM pulse enters circuit, inverter
the input of 11 exports positive voltage, inverter
the output voltage of 12 is high level, nmos pass transistor
10 open ESD electric current of releasing.
The NMOS of this circuit
2 and NMOS
3 adopt the less transistor of breadth length ratio to serve as larger resistance, nmos pass transistor
1 serves as electric capacity, thus can greatly reduce layout design area.
As shown in Figure 2, Cadence spectre is adopted to emulate the voltage and current situation of each node under the HBM2000V pulse of gained.Under HBM pulse, in the 0-0.6us time interval, nmos pass transistor
the gate voltage of 10 is the high level being greater than 0.5V, nmos pass transistor
10 open ESD electric current of releasing, and can find nmos pass transistor from simulation result
the 10 Electrostatic Discharge electric currents of releasing are along with the time steadily declines from 1.25A, and the after-current arriving 750us is 0A, can find out nmos pass transistor
10 have released whole Electrostatic Discharge electric current.
Claims (3)
1., for the static discharge power clamping circuit of integrated circuit, the inverter including nmos pass transistor, PMOS transistor, resistance and be made up of nmos pass transistor and PMOS transistor, is characterized in that:
Nmos pass transistor
(1) grid is connected on power supply, and source electrode is connected with drain electrode;
Nmos pass transistor
(2) grid and drain electrode are connected to nmos pass transistor
(1) on source electrode and the tie point of drain electrode, nmos pass transistor
(2) source electrode has been connected to nmos pass transistor
(3) in drain electrode, nmos pass transistor
(3) source ground;
PMOS transistor
and nmos pass transistor (5)
(6) inverter is formed
(11), PMOS transistor
and nmos pass transistor (8)
(9) inverter is formed
(12), inverter
(11) input is connected to nmos pass transistor
(2) grid, output connects inverter
(12) input, PMOS transistor
and PMOS transistor (5)
(8) power supply is connect, nmos pass transistor
and nmos pass transistor (6)
(9) ground connection;
Nmos pass transistor
(4) drain electrode is connected to inverter
(11) input, nmos pass transistor
(4) grid and nmos pass transistor
(3) grid is connected to device anyway together
(11) output, nmos pass transistor
(4) source ground;
PMOS transistor
(7) grid is connected on inverter
(12) output, drain electrode connects power supply, and source electrode is connected to inverter
(11) output;
Nmos pass transistor
(10) grid is connected to inverter
(12) output, drain electrode connects power supply, source ground;
Resistance (13) one end is connected to nmos pass transistor
(10) grid, one end ground connection.
2. the static discharge power clamping circuit for integrated circuit according to claim 1, is characterized in that: described nmos pass transistor
(10) be BigFET transistor.
3., for the control method of the static discharge power clamping circuit of integrated circuit, it is characterized in that:
When there is static discharge in circuit:
Electrostatic Discharge pulse applies between vdd and vss, has the nmos pass transistor of electric capacity effect
1 makes circuit transient voltage not suddenly change, NMOS
and NMOS (2)
(3) closed condition is in, infinite, NMOS
(3) gate voltage is low level, NMOS
(3) source and drain level resistance effect makes inverter
(11) charge discharging resisting of input is slow, keeps inverter
(11) input terminal voltage is high level, inverter
(11) output is low-voltage, inverter
(12) output is high voltage, nmos pass transistor
(10) grid node is high voltage, nmos pass transistor
(10) conducting is opened, static electricity discharge discharging current;
When circuit normally works:
Inverter
(12) input is high level, and output is low level, PMOS transistor
(7) open, make inverter
(11) output is forced to draw high into high level, nmos pass transistor
(4) open, make inverter
(11) input terminal voltage is forced to low level, and form positive feedback, resistance (13) makes nmos pass transistor
(10) gate voltage is low level, nmos pass transistor
(10) close, do not produce electric leakage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410664096.1A CN104362606B (en) | 2014-11-20 | 2014-11-20 | For the static discharge power clamping circuit and its control method of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410664096.1A CN104362606B (en) | 2014-11-20 | 2014-11-20 | For the static discharge power clamping circuit and its control method of integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104362606A true CN104362606A (en) | 2015-02-18 |
| CN104362606B CN104362606B (en) | 2018-06-26 |
Family
ID=52529844
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410664096.1A Active CN104362606B (en) | 2014-11-20 | 2014-11-20 | For the static discharge power clamping circuit and its control method of integrated circuit |
Country Status (1)
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108134367A (en) * | 2017-12-27 | 2018-06-08 | 湘潭芯力特电子科技有限公司 | One kind prevents leakage circuit after chip power-down |
| CN111277260A (en) * | 2018-12-04 | 2020-06-12 | 三星电子株式会社 | Method for protecting integrated circuit, Schmitt trigger and electrostatic protection circuit |
| CN112103932A (en) * | 2020-09-07 | 2020-12-18 | 海光信息技术股份有限公司 | Electrostatic clamping circuit and chip structure |
| CN112218513A (en) * | 2020-10-13 | 2021-01-12 | Oppo广东移动通信有限公司 | Chip, antenna module and terminal |
| CN113452004A (en) * | 2020-03-26 | 2021-09-28 | 长鑫存储技术有限公司 | Electrostatic protection circuit and full-chip electrostatic protection circuit |
| WO2022095509A1 (en) * | 2020-11-05 | 2022-05-12 | 长鑫存储技术有限公司 | Electrostatic protection circuit, integrated circuit, and electrostatic discharge method |
| WO2023279486A1 (en) * | 2021-07-08 | 2023-01-12 | 长鑫存储技术有限公司 | Electrostatic protection circuit and chip |
| US11929610B2 (en) | 2020-11-05 | 2024-03-12 | Changxin Memory Technologies, Inc. | Electrostatic discharge (ESD) protection circuit, integrated circuit, and electrostatic discharge method |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108134367A (en) * | 2017-12-27 | 2018-06-08 | 湘潭芯力特电子科技有限公司 | One kind prevents leakage circuit after chip power-down |
| CN111277260A (en) * | 2018-12-04 | 2020-06-12 | 三星电子株式会社 | Method for protecting integrated circuit, Schmitt trigger and electrostatic protection circuit |
| CN111277260B (en) * | 2018-12-04 | 2024-03-19 | 三星电子株式会社 | Method for protecting integrated circuit, schmitt trigger and electrostatic protection circuit |
| CN113452004A (en) * | 2020-03-26 | 2021-09-28 | 长鑫存储技术有限公司 | Electrostatic protection circuit and full-chip electrostatic protection circuit |
| CN112103932A (en) * | 2020-09-07 | 2020-12-18 | 海光信息技术股份有限公司 | Electrostatic clamping circuit and chip structure |
| CN112218513A (en) * | 2020-10-13 | 2021-01-12 | Oppo广东移动通信有限公司 | Chip, antenna module and terminal |
| CN112218513B (en) * | 2020-10-13 | 2023-08-22 | Oppo广东移动通信有限公司 | Chip, antenna module and terminal |
| WO2022095509A1 (en) * | 2020-11-05 | 2022-05-12 | 长鑫存储技术有限公司 | Electrostatic protection circuit, integrated circuit, and electrostatic discharge method |
| US11929610B2 (en) | 2020-11-05 | 2024-03-12 | Changxin Memory Technologies, Inc. | Electrostatic discharge (ESD) protection circuit, integrated circuit, and electrostatic discharge method |
| WO2023279486A1 (en) * | 2021-07-08 | 2023-01-12 | 长鑫存储技术有限公司 | Electrostatic protection circuit and chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104362606B (en) | 2018-06-26 |
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