CN112218513A - Chip, antenna module and terminal - Google Patents
Chip, antenna module and terminal Download PDFInfo
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- CN112218513A CN112218513A CN202011091831.6A CN202011091831A CN112218513A CN 112218513 A CN112218513 A CN 112218513A CN 202011091831 A CN202011091831 A CN 202011091831A CN 112218513 A CN112218513 A CN 112218513A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0067—Devices for protecting against damage from electrostatic discharge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q23/00—Antennas with active circuits or circuit elements integrated within them or attached to them
Abstract
The application discloses chip, antenna module and terminal belongs to chip technical field. The chip includes: a signal circuit, a transistor unit and an inverter unit; the grid electrode of the transistor unit is electrically connected to the signal circuit; the input end of the inverter unit is electrically connected with the grid electrode of the transistor unit, and the inverter unit is used for discharging the electrostatic charges in the signal circuit. In the chip of the application, through the input with the phase inverter unit with the grid electric connection of transistor unit, by the static charge in the signal circuit of the grid electric connection of phase inverter unit bleeder transistor unit, need not carry out the layer change to the metal line and antenna unit's design alright with releasing the static charge in the signal circuit, also need not just can realize solving the breakdown problem of transistor in the chip through calculating antenna efficiency, reduced the complexity of chip design, improved the production efficiency of chip.
Description
Technical Field
The application relates to the technical field of chips, in particular to a chip, an antenna module and a terminal.
Background
With the rapid development of scientific technology, in the daily life of people, various terminals have appeared, wherein the terminals can realize data transmission and the like through chips, and the chips of the terminals also become indispensable devices of the terminals.
At present, in the manufacturing process of a chip, different chips have respective design schemes, wherein, as the number of transistors included in the chip is more and more, and the size requirement of the transistors in the chip is smaller and smaller in the chip with a uniform size, wherein the smaller the size of the transistors in the chip is, the higher the integration level of the chip is, and the problem of transistor breakdown caused by electric leakage and charge accumulation is more and more serious. In order to avoid the breakdown of the transistor, in the related art, the metal wire is usually replaced with an upper layer and an antenna unit is usually used, so that the charge accumulation on the metal wire of the chip is reduced, and the breakdown of the transistor inside the chip is avoided.
For the scheme of changing the layers upwards according to the metal connecting wires and adopting the antenna units, the antenna ratio needs to be calculated when the antenna units are designed in the chip, and the problem of avoiding breakdown of transistors is solved according to the antenna ratio, so that the problems of complex chip design process, long production period and the like are solved.
Disclosure of Invention
The embodiment of the application provides a chip, an antenna module and a terminal, and can improve the space utilization rate inside the chip. The technical scheme is as follows:
in one aspect, an embodiment of the present application provides a chip, including: a signal circuit, a transistor unit and an inverter unit;
the grid electrode of the transistor unit is electrically connected to the signal circuit;
the input end of the inverter unit is electrically connected with the grid electrode of the transistor unit, and the inverter unit is used for discharging the electrostatic charges in the signal circuit.
In another aspect, an embodiment of the present application provides an antenna module, where the antenna module includes the chip according to the above aspect.
In another aspect, an embodiment of the present application provides a terminal, where the terminal includes the antenna module according to the above aspect.
The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:
in the chip of the application, through the input with the phase inverter unit with the grid electric connection of transistor unit, by the static charge in the signal circuit of the grid electric connection of phase inverter unit bleeder transistor unit, need not carry out the layer change to the metal line and antenna unit's design alright with releasing the static charge in the signal circuit, need not just can realize solving the breakdown problem of transistor in the chip through calculating antenna efficiency, reduced the complexity of chip design, improved the production efficiency of chip.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a signal circuit inside a chip according to an exemplary embodiment of the present application;
FIG. 2 is a schematic diagram of an exemplary embodiment of the present application, which relates to a signal circuit inside a chip of FIG. 1;
FIG. 3 is a schematic diagram of a signal circuit within another chip related to FIG. 1 according to an exemplary embodiment of the present application;
FIG. 4 is a schematic diagram of a signal circuit within a chip according to an exemplary embodiment of the present application, referring to FIG. 1;
FIG. 5 is a schematic diagram illustrating a partial structure of a chip according to an exemplary embodiment of the present application;
fig. 6 is a schematic circuit diagram of an inverter unit according to an exemplary embodiment of the present application;
FIG. 7 is a schematic diagram illustrating a partial structure of a chip according to an exemplary embodiment of the present application;
FIG. 8 is a schematic diagram of a circuit configuration of an inverter cell of FIG. 7 according to an exemplary embodiment of the present application;
FIG. 9 is a schematic diagram illustrating a partial structure of a chip according to an exemplary embodiment of the present application;
fig. 10 is a schematic structural diagram of a terminal according to an exemplary embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The scheme provided by the application can be used in a real scene of designing a signal circuit inside a chip in a chip production process, and for convenience of understanding, some terms and application scenes related to the embodiment of the application are briefly introduced below.
Complementary Metal Oxide Semiconductor (CMOS): the technology for manufacturing large scale integrated circuit chips or chips manufactured by the technology is a Random Access Memory (RAM) chip on a computer mainboard.
Semiconductor (Semiconductor) refers to a material having a conductive property between a Conductor (Semiconductor) and an insulator (insulator) at normal temperature.
Standard cell library: including a version library, a symbol library, a circuit logic library, etc. The standard cell library comprises combinational logic, sequential logic, functional units and special type units. The standard cell library is a fundamental part of the integrated circuit chip back-end design process. The automatic logic synthesis and layout wiring are carried out by using the optimized library unit which is designed in advance, so that the design efficiency can be improved, and the time for the product to enter the market is shortened. Each process manufacturer typically provides a corresponding standard cell under each process.
Transistor (Transistor): is a solid semiconductor device that can be used for detection, rectification, amplification, switching, voltage regulation, signal modulation, and many other functions. The transistor acts as a variable Switch to control the current flowing out based on the voltage inputted, so the transistor can be used as a current Switch, unlike a general mechanical Switch (such as Relay, Switch) in that the transistor is controlled by an electric signal and the switching speed can be very fast, and the switching speed in a laboratory can reach more than 100 GHz. Transistors can be classified as diodes, triodes, field effect transistors, thyristors, and the like.
Clamping: a measure for limiting the potential at a certain point to a level higher than a prescribed potential is called clamping, and circuits for generating this measure are called clamping circuits. The purpose of the clamp is to keep the top or bottom of the periodically varying waveform at a certain dc level.
With the rapid development of scientific technology and the continuous evolution of semiconductor technology, the chips in the terminal are also continuously updated. Among them, one of the most important components in a chip is a transistor, and as the requirement for the integration degree of the chip is higher and higher, the size of the transistor in the chip is required to be smaller and smaller, the size of the transistor has already entered into a 7nm and 5nm process node at present, and even a chip product containing a 3nm transistor will come into the market soon.
Among them, the problem of leakage current due to the smaller size of the transistor and the problem of breakdown of the transistor due to charge accumulation are becoming more and more serious. The problem that the transistor is broken down may be that a gradual accumulation of charges on a signal circuit inside the chip may be caused during the production and manufacturing process of the chip, and when the charges accumulated on the signal circuit exceed a threshold, the transistor connected to the signal circuit may be broken down, so that a breakdown phenomenon may occur, and the transistor may be permanently disabled.
Referring to fig. 1, a schematic diagram of a signal circuit inside a chip according to an exemplary embodiment of the present application is shown. As shown in fig. 1, a chip 100 includes a signal circuit 101 and a transistor 102. During the manufacturing process of the chip 100, since the signal circuit 101 generates the corresponding charges 103 due to the charge accumulation, wherein the moving direction of the charges can be as shown by the arrow in fig. 1, when the charges 103 are accumulated to exceed the tolerance range of the transistor 102, a breakdown phenomenon occurs, which causes the transistor 102 to fail, and thus the signal circuit cannot operate normally.
At present, in order to avoid the breakdown of the transistors connected to the signal circuit in the chip, before the chip is mounted, the Antenna protection (Antenna isolation) needs to be detected (Check) and mounted (Fix), and in order to achieve the effect of less charge accumulation on the signal circuit 101 shown in fig. 1, a metal wire layer-up switching manner may be adopted.
Referring to fig. 2, a schematic diagram of a signal circuit inside a chip related to fig. 1 according to an exemplary embodiment of the present application is shown. As shown in fig. 2, a chip 200 includes a signal circuit 201, a transistor 202, and a layer-changing line 203. Similarly, during the manufacturing process of the chip 200, since the corresponding charges 204 are generated on the signal circuit 201 due to the charge accumulation, due to the existence of the layer-changing line 203, the length of the signal circuit 201 can be made shorter by the layer-changing line 203, so that the charges accumulated on the signal circuit 201 are less, and the charge accumulation on the signal circuit is reduced. However, the corresponding electrostatic charges 205 still occur on the layer-changing line 203, and when the charges 205 on the layer-changing line 203 accumulate to exceed the tolerance range of the transistor 202, they still enter the transistor 202 according to the arrow direction shown in fig. 2, so that a breakdown phenomenon occurs, which causes the failure of the transistor 202, and results in the abnormal operation of the signal circuit.
With the scheme shown in fig. 2, the layer-changing line can reduce the accumulation of charges by changing layers upwards, and due to the existence of the layer-changing line, not only the extra space inside the chip needs to be occupied, but also static charges can be generated on the layer-changing line, and when the static charges are accumulated to exceed the bearing range of the transistor, the breakdown phenomenon can also occur in the transistor.
In order to solve the technical problems caused by the layer-changing circuit, another solution exists in the related art. The electrostatic charge on the signal circuit in fig. 1 or fig. 2 described above is discharged by using the Antenna Cell (Antenna Cell) in the standard Cell library.
Referring to fig. 3, a schematic diagram of a signal circuit inside another chip related to fig. 1 according to an exemplary embodiment of the present application is shown. As shown in fig. 3, a chip 300 includes a signal circuit 301, a transistor 302, and an antenna element 303. Similarly, in the manufacturing process of the chip 300, since the signal circuit 301 generates the corresponding charges 304 due to the charge accumulation, but due to the existence of the antenna unit 203, when the charges accumulated on the signal circuit 301 want to enter the transistor 302 according to the arrow direction in fig. 3, the antenna unit 203 can introduce and discharge the static charges into itself, so as to prevent the static charges from directly entering the transistor 302, thereby avoiding the breakdown of the transistor 202 and avoiding the design of multiple layer-changing lines.
In practical applications, the antenna unit shown in fig. 3 has limited charges that can be discharged by the antenna unit due to its area size, and when one antenna unit cannot discharge electrostatic charges in a signal circuit, a plurality of antenna units are usually required to be designed for discharging. For example, for the problem of transistor breakdown caused by similar metal wires in Mesh Net (Mesh Net), it is usually necessary to use 10 or even 20 antenna elements as shown in fig. 3 above to satisfy the discharge requirement of electrostatic charge on the metal wires in the chip.
Referring to fig. 4, a schematic diagram of a signal circuit inside a chip related to fig. 1 according to an exemplary embodiment of the present application is shown. As shown in fig. 4, a chip 400 includes a signal circuit 401, a transistor 402, an antenna element array 403, and a layer-changing line 404. Similarly, during the manufacturing process of the chip 400, due to the signal circuit 401 and the layer-change line 404, corresponding charges 405 may be generated due to charge accumulation, wherein due to the existence of the layer-change line 404, the length of the signal circuit 401 may be shorter due to the layer-change line 404, so that the charges accumulated on the signal circuit 401 are less, and the charge accumulation on the signal circuit may be mitigated. In addition, due to the existence of the antenna unit array 403, when charges accumulated on the signal circuit 401 and the layer change line 404 want to enter the transistor 402 according to the arrow direction in fig. 4, the antenna unit array 403 can introduce and discharge the electrostatic charges into itself, so as to prevent the electrostatic charges from directly entering the transistor 302, thereby avoiding the phenomenon of breakdown on the transistor 402. By combining the two modes, the transistor 402 can be protected, and the breakdown phenomenon of the transistor can be avoided.
Wherein, to above-mentioned content, the antenna element array not only needs extra area and wire winding resource, cause the complicated problem of line of chip inner circuit, and each antenna element is connected to the load that can increase this circuit on the trigger point of same circuit, cause the increase of electrostatic capacity (Capacitance), and because the antenna element who adopts need calculate the antenna ratio when chip internal design, how to solve the problem of avoiding the transistor to puncture according to the antenna ratio, make the chip design process complicated, the production cycle that the chip was thrown the piece has been influenced.
In order to reduce the complexity of chip design and improve the production efficiency of chips, the application provides a solution, which can avoid the design of layer changing circuits and antenna units in the chips and reduce the calculation process of chip design in the related technology. Referring to fig. 5, a partial structure diagram of a chip according to an exemplary embodiment of the present disclosure is shown. As shown in fig. 5, a chip 500 includes a signal circuit 501, a transistor unit 502, and an inverter unit 503.
The gate of the transistor unit 502 is electrically connected to the signal circuit 501. Optionally, in this embodiment of the application, the signal circuit 501 may be any circuit designed by a developer for the inside of a chip, and the transistor unit 502 is electrically connected to the signal circuit 501, where a gate of the transistor unit is electrically connected to the signal circuit.
In this application, the signal circuit 501 is further electrically connected with an inverter unit 503, an input end of the inverter unit 503 is electrically connected with a gate of the transistor unit, and the inverter unit 503 is used for discharging electrostatic charges in the signal circuit 501.
Alternatively, in the present application, the input terminal of the inverter unit 503 may be electrically connected to the same connection point on the signal circuit 501 as the gate of the transistor unit 502, so as to electrically connect the inverter unit 503, the transistor unit 502 and the signal circuit 501, and when the electrostatic charge in the signal circuit 501 is accumulated to a certain extent, if the electrostatic charge is introduced into the transistor unit 502 according to the arrow direction in the figure, the electrostatic charge is introduced into itself and discharged by the inverter unit 503 in advance, so as to protect the transistor unit 502.
In summary, in the chip of the present application, the input end of the inverter unit is electrically connected to the gate of the transistor unit, and the inverter unit discharges the electrostatic charge in the signal circuit electrically connected to the gate of the transistor unit, so that the electrostatic charge in the signal circuit can be discharged without changing the layer of the metal circuit and designing the antenna unit, and the problem of breakdown of the transistor in the chip can be solved without calculating the antenna efficiency, thereby reducing the complexity of the chip design and improving the production efficiency of the chip.
In a possible implementation manner, the inverter unit includes an N-Metal Oxide Semiconductor (NMOS) transistor and a P-Metal Oxide Semiconductor (PMOS) transistor, that is, the inverter unit includes a PMOS transistor and an NMOS transistor, and when the inverter unit discharges the electrostatic charge in the signal circuit, the electrostatic charge in the signal circuit can be discharged through the N-Metal Oxide Semiconductor transistor and the P-Metal Oxide Semiconductor transistor of the inverter unit.
Referring to fig. 6, a schematic circuit diagram of an inverter unit according to an exemplary embodiment of the present application is shown. As shown in fig. 6, the inverter unit 600 includes an input terminal I601, an NMOS transistor 602, and a PMOS transistor 603. Alternatively, according to the connection relationship in fig. 5, the input terminal I601 of the inverter unit 600 in fig. 6 may be electrically connected to the gate of the transistor unit in fig. 5, or the input terminal I601 of the inverter unit 600 in fig. 6 may also be electrically connected to the signal circuit at the electrical connection position between the gate of the transistor unit in fig. 5 and the signal circuit.
In the Inverter unit (Inverter Cell) of the standard Cell library, because the input terminal I of the Inverter unit is connected with a PMOS transistor and an NMOS transistor at the same time, when the input terminal I of the Inverter unit is connected to a signal circuit which can cause the breakdown problem due to the charge accumulation of the signal circuit in the related art, that is, the input terminal I of the Inverter unit is electrically connected to the Gate of the signal circuit connected with the transistor unit, which is equivalent to the inserted PMOS transistor and NMOS transistor of the Inverter unit, all the Poly Gate transistors (Poly Gate) of the PMOS transistor and the NMOS transistor can participate in the discharge operation of the electrostatic charges in the signal circuit, thereby playing the role of protecting the target transistor. Therefore, in the related art, a chip with a large antenna ratio is required, and when the chip needs to use 10 or even 20 antenna units to discharge the electrostatic charges in the signal circuit, by adopting the scheme of the present application, it may be necessary to use one or two inverter units (as shown in fig. 5), so as to discharge the electrostatic charges. The model of the inverter unit mentioned in the present application may be INVD12 or INVD 16.
In summary, in the chip of the present application, the input end of the inverter unit is electrically connected to the gate of the transistor unit, and the inverter unit discharges the electrostatic charge in the signal circuit electrically connected to the gate of the transistor unit, so that the electrostatic charge in the signal circuit can be discharged without changing the layer of the metal circuit and designing the antenna unit, and the problem of breakdown of the transistor in the chip can be solved without calculating the antenna efficiency, thereby reducing the complexity of the chip design and improving the production efficiency of the chip.
In a possible implementation manner, the signal circuit in fig. 5 may further be electrically connected to at least two power sources, and if the operating states of at least two of the power sources in the signal circuit are different, for example, one power source operates in an on state, and the other power source operates in an off state, at this time, the signal circuit is connected to the gate of the transistor unit, the input terminal of the inverter unit may detect that one power source operates in the on state, and the other power source operates in the off state, so that an indeterminate state (X state) occurs at the input terminal of the inverter unit, which causes the inverter unit to fail to normally discharge electrostatic charges in the signal circuit, and an abnormal leakage condition exists.
Referring to fig. 7, a partial structural diagram of a chip according to an exemplary embodiment of the present disclosure is shown. As shown in fig. 7, a chip 700 includes a signal circuit 701, a transistor unit 702, and an inverter unit 703.
The gate of the transistor unit 702 is electrically connected to the signal circuit 701. Optionally, in this embodiment of the present application, the signal circuit 701 may be any circuit designed by a developer for the inside of a chip, and the signal circuit 701 is electrically connected to the transistor unit 702, where a gate of the transistor unit is electrically connected to the signal circuit.
In this application, the signal circuit 701 is further electrically connected to an inverter unit 703, an input terminal of the inverter unit 703 is electrically connected to a gate of the transistor unit, and the inverter unit 703 is used for discharging electrostatic charges in the signal circuit 701.
Alternatively, in the present application, the input terminal of the inverter unit 703 may be electrically connected to the same connection point on the signal circuit 701 as the gate of the transistor unit 702, so as to electrically connect the inverter unit 703, the transistor unit 702 and the signal circuit 701, and when the electrostatic charge in the signal circuit 701 is accumulated to a certain extent, if the electrostatic charge is introduced into the transistor unit 702 according to the arrow direction in the figure, the electrostatic charge is introduced into the transistor unit 703 in advance and discharged, so as to protect the transistor unit 702.
Optionally, fig. 7 further includes at least two power supplies 704, and respective operating states of the at least two power supplies include an on state and an off state, where the on state corresponds to providing the signal circuit 701 with the electric signal, and the off state corresponds to not providing the signal circuit 701 with the electric signal.
Optionally, the chip 700 in fig. 7 further includes an isolation unit 705, and the isolation unit 705 is used for clamping a connection position between the input end of the inverter unit and the gate of the transistor unit.
In order to solve the technical problem of the application of the scheme in fig. 5 to a signal circuit with at least two power supplies, the present application opens the circuit between the drains of two transistors included in the inverter unit in fig. 7, i.e. the circuit between the drains of two transistors included in the inverter unit in fig. 7 is in an open state. Referring to fig. 8, a schematic diagram of a circuit structure of an inverter unit related to fig. 7 according to an exemplary embodiment of the present application is shown. As shown in fig. 8, the inverter unit 800 includes an input terminal I801, an NMOS transistor 802, and a PMOS transistor 803. Alternatively, according to the connection relationship in fig. 8, the input terminal I801 of the inverter unit 800 in fig. 8 may be electrically connected to the gate of the transistor unit in fig. 7, or the input terminal I801 of the inverter unit 800 in fig. 8 may also be electrically connected to the signal circuit at the electrical connection position between the gate of the transistor unit in fig. 7 and the signal circuit.
By comparing fig. 6 and fig. 8, in the present application, the circuit between the drains of the two transistors included in the inverter unit is disconnected and connected to the signal circuit in fig. 7, so that the problem of abnormal leakage power consumption caused when the input I terminal of the inverter unit is in the X state is solved.
Optionally, the signal circuit includes a signal input terminal and a signal output terminal, the signal input terminal is electrically connected to the first power supply, the source of the transistor unit is connected to the signal input terminal, and the signal output terminal is electrically connected to the second power supply. Wherein the first power source may be any one of the at least two power sources 704 and the second power source may be another one of the at least two power sources 704 other than the first power source.
In a possible implementation manner, the number of signal input terminals in fig. 7 may be at least two, the number of transistor units is the same as the number of signal input terminals, and the number of inverter units is at least the number of transistor units.
That is, in fig. 7, a signal circuit may include a plurality of input terminals and a plurality of output terminals, and a transistor unit may be disposed corresponding to each input terminal, so in actual protection, it is also necessary to prevent charge breakdown for the transistor unit connected to each input terminal, and an inverter unit may be disposed at a connection point between each input terminal of the signal circuit and each transistor unit to implement protection for the transistor units of each input terminal.
Optionally, for an example that the signal circuit is connected to two power supplies, please refer to fig. 9, which shows a schematic diagram of a partial structure of a chip according to an exemplary embodiment of the present application. As shown in fig. 9, a chip 900 includes a signal circuit 901, a transistor unit 902, an inverter unit 903, a first power supply 904, and a second power supply 905. The respective working states of the first power supply 904 and the second power supply 905 include an on state and an off state; the on state corresponds to supplying an electric signal to the signal circuit 901, and the off state corresponds to not supplying an electric signal to the signal circuit 901.
Alternatively, the respective operating states of the first power supply 904 and the second power supply 905 may be the same or different. The signal circuit may further include a signal input terminal and a signal output terminal according to a power source to which the signal circuit is connected. The signal input end is electrically connected with the first power supply, and the source electrode of the transistor unit is connected with the signal input end; the signal output end is electrically connected with the second power supply. The working state of the first power supply is in an on state, and the working state of the second power supply is in an off state; or the working state of the first power supply is in a closed state, and the working state of the second power supply is in an open state.
In summary, in the chip of the present application, the input end of the inverter unit is electrically connected to the gate of the transistor unit, and the inverter unit discharges the electrostatic charge in the signal circuit electrically connected to the gate of the transistor unit, so that the electrostatic charge in the signal circuit can be discharged without changing the layer of the metal circuit and designing the antenna unit, and the problem of breakdown of the transistor in the chip can be solved without calculating the antenna efficiency, thereby reducing the complexity of the chip design and improving the production efficiency of the chip.
In addition, in the application, by changing the circuit in the inverter unit, when the signal circuit is connected with a plurality of power supplies, the transistor unit can be protected across power supply domains, and the application scene of the inverter unit is expanded.
In a possible implementation manner, the present application further provides an antenna module, where the antenna module may include any one of the chips shown in fig. 5, fig. 7, or fig. 9.
In a possible implementation manner, the application further provides a terminal, and the terminal may include the at least one antenna module. Referring to fig. 10, a schematic structural diagram of a terminal according to an exemplary embodiment of the present application is shown. As shown in fig. 10, the terminal 1000 includes a first antenna module 1001, a second antenna module 1002, a third antenna module 1003 and a fourth antenna module 1004. The first antenna module 1001, the second antenna module 1002, the third antenna module 1003 and the fourth antenna module 1004 may all adopt the chips provided in fig. 5, fig. 7 or fig. 9.
In summary, in the chip of the present application, the input end of the inverter unit is electrically connected to the gate of the transistor unit, and the inverter unit discharges the electrostatic charge in the signal circuit electrically connected to the gate of the transistor unit, so that the electrostatic charge in the signal circuit can be discharged without changing the layer of the metal circuit and designing the antenna unit, and the problem of breakdown of the transistor in the chip can be solved without calculating the antenna efficiency, thereby reducing the complexity of the chip design and improving the production efficiency of the chip.
It should be understood that reference herein to "and/or" describing an association of case objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A chip, wherein the chip comprises: a signal circuit, a transistor unit and an inverter unit;
the grid electrode of the transistor unit is electrically connected to the signal circuit;
the input end of the inverter unit is electrically connected with the grid electrode of the transistor unit, and the inverter unit is used for discharging the electrostatic charges in the signal circuit.
2. The chip of claim 1, wherein the inverter unit comprises an nmos transistor and a pmos transistor;
the inverter unit is used for discharging the electrostatic charges in the signal circuit through the N-type metal oxide semiconductor transistor and the P-type metal oxide semiconductor transistor.
3. The chip of claim 1, wherein the signal circuit is electrically connected to at least two power sources;
the circuit between the drains of the two transistors comprised in the inverter cell is open.
4. The chip of claim 3, wherein the respective operating states of the at least two power supplies include an on state and an off state;
the respective working states of the at least two power supplies are the same or different.
5. The chip of claim 3, wherein the signal circuit comprises a signal input and a signal output;
the signal input end is electrically connected with a first power supply, and the source electrode of the transistor unit is connected with the signal input end;
the signal output end is electrically connected with the second power supply.
6. The chip of claim 5, wherein the number of the signal input terminals is at least two, and the number of the transistor units is the same as the number of the signal input terminals;
the number of the inverter units is at least the number of the transistor units.
7. The chip of claim 5, wherein the operating state of the first power supply is in the on state, and the operating state of the second power supply is in the off state; alternatively, the first and second electrodes may be,
the working state of the first power supply is in the off state, and the working state of the second power supply is in the on state.
8. The chip according to any one of claims 1 to 7, wherein the chip further comprises an isolation unit for clamping a connection position between the input terminal of the inverter unit and the gate of the transistor unit.
9. An antenna module, characterized in that the antenna module comprises the chip according to any one of claims 1 to 8.
10. A terminal, characterized in that it comprises an antenna module according to claim 9.
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Citations (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745323A (en) * | 1995-06-30 | 1998-04-28 | Analog Devices, Inc. | Electrostatic discharge protection circuit for protecting CMOS transistors on integrated circuit processes |
| JP2000101419A (en) * | 1998-09-18 | 2000-04-07 | Nec Corp | Logic circuit |
| JP2004179268A (en) * | 2002-11-25 | 2004-06-24 | Sharp Corp | Semiconductor integrated circuit and its manufacturing method |
| US20050030688A1 (en) * | 2003-08-04 | 2005-02-10 | Kazuhisa Sakihama | ESD protection circuit having a control circuit |
| US20050237682A1 (en) * | 2004-04-26 | 2005-10-27 | Taiwan Semiconductor Manufacturing Co. | Novel ESD protection scheme for core devices |
| US20060114047A1 (en) * | 2004-11-26 | 2006-06-01 | Nec Electronics Corporation | Semiconductor unit |
| US20080106834A1 (en) * | 2006-11-07 | 2008-05-08 | Kenneth Wai Ming Hung | electrostatic discharge protection circuit |
| CN101707368A (en) * | 2009-05-15 | 2010-05-12 | 彩优微电子(昆山)有限公司 | Electrostatic damage protective device with noise immunologic function and control method thereof |
| CN103001200A (en) * | 2012-12-14 | 2013-03-27 | 北京大学 | Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit |
| CN103022996A (en) * | 2011-09-21 | 2013-04-03 | 中芯国际集成电路制造(北京)有限公司 | Electronic static discharge protection circuit and electronic static discharge protection method |
| CN103218003A (en) * | 2013-04-26 | 2013-07-24 | 无锡中星微电子有限公司 | Low-dropout voltage stabilizer with multiple power sources input |
| CN104283201A (en) * | 2014-09-11 | 2015-01-14 | 北京大学 | Input stage esd protection circuit |
| CN104362606A (en) * | 2014-11-20 | 2015-02-18 | 辽宁大学 | Electrostatic discharge power source clamping circuit for integrated circuit and control method thereof |
| CN204180038U (en) * | 2014-11-20 | 2015-02-25 | 辽宁大学 | For the electro-static discharge trigger circuit of integrated circuit |
| US9319045B1 (en) * | 2014-12-29 | 2016-04-19 | Texas Instruments Incorporated | Method and apparatus for reducing gate leakage of low threshold transistors during low power mode in a multi-power-domain chip |
| CN107278326A (en) * | 2017-05-26 | 2017-10-20 | 深圳市汇顶科技股份有限公司 | Esd protection circuit and ESD guard methods |
| CN109286181A (en) * | 2017-07-21 | 2019-01-29 | 上海韦玏微电子有限公司 | Power clamp ESD protective circuit |
| CN109684762A (en) * | 2018-12-28 | 2019-04-26 | 上海贝岭股份有限公司 | The setting circuit of chip and its pin |
| CN110308759A (en) * | 2018-03-27 | 2019-10-08 | 复旦大学 | A kind of novel level shifter circuit |
| CN110994574A (en) * | 2019-10-15 | 2020-04-10 | 珠海亿智电子科技有限公司 | High-voltage-resistant power supply clamping circuit |
-
2020
- 2020-10-13 CN CN202011091831.6A patent/CN112218513B/en active Active
Patent Citations (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745323A (en) * | 1995-06-30 | 1998-04-28 | Analog Devices, Inc. | Electrostatic discharge protection circuit for protecting CMOS transistors on integrated circuit processes |
| JP2000101419A (en) * | 1998-09-18 | 2000-04-07 | Nec Corp | Logic circuit |
| JP2004179268A (en) * | 2002-11-25 | 2004-06-24 | Sharp Corp | Semiconductor integrated circuit and its manufacturing method |
| US20040140483A1 (en) * | 2002-11-25 | 2004-07-22 | Sharp Kabushiki Kaisha | Semiconductor integrated circuit and fabrication method for same |
| US20050030688A1 (en) * | 2003-08-04 | 2005-02-10 | Kazuhisa Sakihama | ESD protection circuit having a control circuit |
| US20050237682A1 (en) * | 2004-04-26 | 2005-10-27 | Taiwan Semiconductor Manufacturing Co. | Novel ESD protection scheme for core devices |
| US20060114047A1 (en) * | 2004-11-26 | 2006-06-01 | Nec Electronics Corporation | Semiconductor unit |
| US20080106834A1 (en) * | 2006-11-07 | 2008-05-08 | Kenneth Wai Ming Hung | electrostatic discharge protection circuit |
| CN101707368A (en) * | 2009-05-15 | 2010-05-12 | 彩优微电子(昆山)有限公司 | Electrostatic damage protective device with noise immunologic function and control method thereof |
| CN103022996A (en) * | 2011-09-21 | 2013-04-03 | 中芯国际集成电路制造(北京)有限公司 | Electronic static discharge protection circuit and electronic static discharge protection method |
| CN103001200A (en) * | 2012-12-14 | 2013-03-27 | 北京大学 | Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit |
| CN103218003A (en) * | 2013-04-26 | 2013-07-24 | 无锡中星微电子有限公司 | Low-dropout voltage stabilizer with multiple power sources input |
| CN104283201A (en) * | 2014-09-11 | 2015-01-14 | 北京大学 | Input stage esd protection circuit |
| CN104362606A (en) * | 2014-11-20 | 2015-02-18 | 辽宁大学 | Electrostatic discharge power source clamping circuit for integrated circuit and control method thereof |
| CN204180038U (en) * | 2014-11-20 | 2015-02-25 | 辽宁大学 | For the electro-static discharge trigger circuit of integrated circuit |
| US9319045B1 (en) * | 2014-12-29 | 2016-04-19 | Texas Instruments Incorporated | Method and apparatus for reducing gate leakage of low threshold transistors during low power mode in a multi-power-domain chip |
| CN107278326A (en) * | 2017-05-26 | 2017-10-20 | 深圳市汇顶科技股份有限公司 | Esd protection circuit and ESD guard methods |
| CN109286181A (en) * | 2017-07-21 | 2019-01-29 | 上海韦玏微电子有限公司 | Power clamp ESD protective circuit |
| CN110308759A (en) * | 2018-03-27 | 2019-10-08 | 复旦大学 | A kind of novel level shifter circuit |
| CN109684762A (en) * | 2018-12-28 | 2019-04-26 | 上海贝岭股份有限公司 | The setting circuit of chip and its pin |
| CN110994574A (en) * | 2019-10-15 | 2020-04-10 | 珠海亿智电子科技有限公司 | High-voltage-resistant power supply clamping circuit |
Non-Patent Citations (7)
| Title |
|---|
| 张登军: "一种适用于纳米级存储器芯片的静电保护电路", 《福建电脑》 * |
| 张登军: "一种适用于纳米级存储器芯片的静电保护电路", 《福建电脑》, no. 10, 25 October 2018 (2018-10-25), pages 124 - 125 * |
| 张登军;: "一种适用于纳米级存储器芯片的静电保护电路", 福建电脑, no. 10, pages 124 - 125 * |
| 沈放;陈巍;黄灿英;陈艳;: "一种CMOS新型ESD保护电路设计" * |
| 沈放;陈巍;黄灿英;陈艳;: "一种CMOS新型ESD保护电路设计", no. 24, pages 136 - 139 * |
| 沈放等: "一种CMOS新型ESD保护电路设计", 《现代电子技术》, no. 24, 15 December 2015 (2015-12-15), pages 136 - 139 * |
| 陶永华: "功率MOSFET及其在逆变器中的应用", no. 01, pages 84 - 89 * |
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