CN103001200A - Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit - Google Patents
Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit Download PDFInfo
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Abstract
The invention relates to the technical field of integrated circuit chip electro-static discharge protection, in particular to a multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit. The circuit detects access of static pulses through an ESD impact detecting unit and sends response signals to a tapping transistor to open a passage, the tapping transistor releases electrostatic charges carried by impacts and then the tapping transistor close the passage, and small leakage during normal electrification is guaranteed. Furthermore, a CR structure is used for replacing an RC+ inverter structure to serve as the ESD impact detecting unit, a circuit structure is simplified, and opening time of the tapping transistor is prolonged to some extent. Further, passive capacitance of the tapping transistor for closing the passage uses a current mirror unit, and opening time of the tapping transistor can be effectively prolonged. Therefore, the protective circuit can effectively prolong opening time of the tapping transistor under the ESD impact in a reasonable domain area and guarantees that leakage of the protective circuit during normal electrification is small.
Description
Technical field
The present invention relates to integrated circuit (IC) chip static discharge (ESD, Electronic StaticDischarge) resist technology field, be specifically related to a kind of multiple RC and trigger power supply clamper esd protection circuit.
Background technology
The Electrostatic Protection Design of integrated circuit (IC) chip is to guarantee one of essential condition that chip can work, and effective antistatic impacts mechanism if chip does not have a cover, so, just probably loses efficacy because of electrostatic breakdown before it can be played effectiveness.Chip will face the electrostatic impact that much brings from plant equipment, human body or other electronic equipment in production, transportation, test and use procedure, therefore, electrostatic impact itself also has different genesis mechanism and pattern.All in all, electrostatic impact has the characteristics such as short, the instantaneous voltage that forms of time and electric current are large, and the logical circuit of chip internal is had very strong potential lethality.So the chip designer need to impact mechanism for effective antistatic of chip design, when ESD impacts generation, can release the electrostatic charge that impact brings, and guarantees the normal operation of inner function circuit.
The scope that the esd protection research of integrated circuit (IC) chip relates to is wide, needs the many factors of considering.Specifically, can optimize impact from device level and release device at the next interim relieving capacity of impact; Can design an effective trigger mechanism from circuit grade, allow and impact the device of releasing and in time open impacting temporarily, when normally powering on, keep turn-offing; Can also solve from the circuit layout rank and impact the device of releasing and face when impacting different units and open inconsistent problem.Above three aspects of ESD protectiving scheme complement each other, and outstanding ESD protectiving scheme all tries hard to find a best compromise point between barrier propterty and protection cost.
Effectively trigger mechanism can be realized by the designing power supply clamp circuit; Effectively trigger mechanism refers to: 1, ESD impacts temporarily, and the transistor opening time long enough of releasing can be released electrostatic charge fully.When 2, normally powering on, the transistor of releasing is closed enough well, avoids unnecessary electric leakage.3, clamp circuit self area that occupies chip is wanted suitably, guarantees that the cost that the protection strategy self brings is as far as possible little.
A kind of power supply clamper esd protection circuit of the prior art as shown in fig. 1, this power supply clamper esd protection circuit has adopted the unlatching path of the transistor (Mbig) of releasing and has turn-offed the design philosophy that path separates.Thus, the transistor of releasing is impacting the interim opening time mainly to be decided by the time delay of the transistor shutoff path of releasing, do little space so just for ESD impact detection electric capacity (R1) and resistance (C1), R1 and C1 do little after, the area natural energy of circuit layout accesses and reduces, and prevents that simultaneously protective circuit from also having been obtained reinforcement by the ability of fast powering-up voltage false triggering; Even and if the transistor of releasing is by the false triggering of a fast powering-up voltage, protective circuit also can break away from the false triggering state after postponing turn-offing the path regular hour, can effectively avoid class breech lock problem.Transistorized opening time of releasing is postponed to decide by the equivalent RC that the transistor of releasing turn-offs path, and when ESD impacts interim, the transistor opening time of releasing is longer, and is better to the reliability of protecting self.In the above-mentioned power supply clamper esd protection circuit, the resistance that the transistor of releasing turn-offs path is to realize with PMOS transistor (Mp5, Mp6), and in integrated circuit technology, the resistance that serves as with active device is difficult to realize larger resistance value usually.Therefore; the two-stage reinforced concrete structure of the transistor of releasing shutoff path wants to reach with the ESD impact surveys the onesize equivalent time constant of resistance capacitance structure; need to do capacitor C 2 and C3 very greatly; larger passive device so that the chip area of protective circuit greatly increase; therefore, above-mentioned power supply clamper esd protection circuit is the requirement that runs counter to designed reliability to a certain extent.
Summary of the invention
The technical problem that (one) will solve
The object of the present invention is to provide a kind of multiple RC to trigger power supply clamper esd protection circuit, be used for after ESD impacts generation, the electrostatic charge that impact brings being released; Further, the present invention has also solved how reasonably effectively to prolong the opening time of transistor under ESD impacts of releasing under the chip area, and guarantees the protective circuit very little problem of leaking electricity when normally powering on.
(2) technical scheme
Technical solution of the present invention is as follows:
A kind of multiple RC triggers power supply clamper esd protection circuit, comprise ESD impact probe unit and respectively the connected transistor of releasing open path and the transistor of releasing turn-offs path, the described transistor of releasing is opened path and the transistor of releasing and is turn-offed path and be connected with the transistor of releasing respectively;
Described ESD impacts probe unit, and whether be used for surveying has electrostatic pulse to access this circuit; If have, then send response signal to the described transistor of releasing and open path;
The described transistor of releasing is opened path, is used for opening the transistor of releasing according to described response signal;
The described transistor of releasing turn-offs path, is used under ESD impacts, and for the transistor of releasing provides enough opening times, then turn-offs the transistor of releasing;
The described transistor of releasing, the electrostatic charge that the described electrostatic pulse that is used for releasing is brought.
Preferably, described ESD impact probe unit comprises capacitor C 1 and resistance R 1; Described capacitor C 1 top crown is connected with circuit power pin VDD, and bottom crown is connected with described resistance R 1 one ends, described resistance R 1 other end ground connection.
Preferably, the described transistor of releasing is nmos pass transistor Mbig, and described nmos pass transistor Mbig grid opens path with the described transistor of releasing respectively and the transistor of releasing shutoff path is connected, source ground, and drain electrode is connected with circuit power pin VDD.
Preferably, the described transistor unlatching path of releasing comprises PMOS transistor Mp2, Mp3 and nmos pass transistor Mn2; The grid of described PMOS transistor Mp2 turn-offs path with the bottom crown of described capacitor C 1, the transistor of releasing respectively and nmos pass transistor Mn2 grid is connected, source electrode is connected with circuit power pin VDD, and drain electrode is connected with described PMOS transistor Mp3 grid and nmos pass transistor Mn2 drain electrode respectively; Described PMOS transistor Mp3 source electrode is connected with circuit power pin VDD, and drain electrode is turn-offed path with described nmos pass transistor Mbig grid and the transistor of releasing respectively and is connected; Described nmos pass transistor Mn2 source ground.
Preferably, the described transistor shutoff path of releasing comprises PMOS transistor Mp4, Mp5, Mp6, nmos pass transistor Mn3, Mn4, capacitor C 2, C3, the first current lens unit and the second current lens unit; Described PMOS transistor Mp4 grid is connected with described PMOS transistor Mp5 drain electrode, capacitor C 2 top crowns, nmos pass transistor Mn4 grid and the first current lens unit respectively, source electrode is connected with circuit power pin VDD, and drain electrode is connected with described PMOS transistor Mp6 grid and nmos pass transistor Mn4 drain electrode respectively; Described PMOS transistor Mp5 grid is connected with described capacitor C 1 bottom crown, and source electrode is connected with circuit power pin VDD; Described PMOS transistor Mp6 source electrode is connected with circuit power pin VDD, and drain electrode is connected with described nmos pass transistor Mn3 grid, capacitor C 3 top crowns and the second current lens unit respectively; Described nmos pass transistor Mn3 source ground, drain electrode is connected with described nmos pass transistor Mbig grid; Described nmos pass transistor Mn4 source ground.
Preferably, described the first current lens unit comprises nmos pass transistor Man1, Man2; Described nmos pass transistor Man1 grid is connected source ground with described capacitor C 2 bottom crowns, nmos pass transistor Man1 drain electrode and nmos pass transistor Man2 grid respectively; Described nmos pass transistor Man2 source ground, drain electrode is connected with the top crown of described capacitor C 2;
Described the second current lens unit comprises nmos pass transistor Mbn1, Mbn2; Described nmos pass transistor Mbn1 grid is connected source ground with described capacitor C 3 bottom crowns, nmos pass transistor Mbn1 drain electrode and nmos pass transistor Mbn2 grid respectively; Described nmos pass transistor Mbn2 source ground, drain electrode is connected with the top crown of described capacitor C 3.
(3) beneficial effect
A kind of multiple RC of the present invention triggers power supply clamper esd protection circuit, impacting probe unit by ESD surveys the access of electrostatic pulse and sends response signal to the transistor unlatching path of releasing, the electrostatic charge that the transistor of releasing brings impact discharges and turn-offs path by the transistor of releasing after complete and turn-off, and electric leakage is very little when guaranteeing normally to power on; Further, the present invention utilizes the CR structure to replace the RC+ inverter structure to impact probe unit as ESD, has simplified circuit structure on the one hand, has also prolonged to a certain extent the transistor opening time of releasing on the other hand; Further, the present invention uses current lens unit by the passive capacitive of the transistor of releasing being turn-offed path, has more effectively prolonged the transistorized opening time of releasing; Therefore, the present invention can reasonably effectively prolong the opening time of transistor under ESD impacts of releasing under the chip area, and the assurance protective circuit is leaked electricity very little when normally powering on.
Description of drawings
Fig. 1 is a kind of power supply clamper esd protection circuit structural representation in the prior art;
Fig. 2 is that a kind of multiple RC of the present invention triggers power supply clamper esd protection circuit structural representation;
Fig. 3 is under same ESD impacts, RC+ inverter structure output voltage temporal evolution schematic diagram among CR structure and Fig. 2 among Fig. 1;
Fig. 4 is under same ESD impacts, the transistor grid voltage of releasing among release among Fig. 1 transistor grid voltage and Fig. 2 temporal evolution schematic diagram;
Fig. 5 be same normal under the piezoelectric voltage, the transistor grid voltage of releasing among release among Fig. 1 transistor grid voltage and Fig. 2 temporal evolution schematic diagram.
Embodiment
Below in conjunction with drawings and Examples, the embodiment of inventing is described further.Following examples only are used for explanation the present invention, but are not used for limiting the scope of the invention.
A kind of multiple RC as shown in Figure 2 triggers power supply clamper esd protection circuit, comprise ESD impact probe unit and respectively the connected transistor of releasing open path and the transistor of releasing turn-offs path, the transistor of releasing is opened path and the transistor of releasing and is turn-offed path and be connected with the transistor of releasing respectively;
ESD impacts probe unit, and whether be used for surveying has electrostatic pulse to access this circuit, surveys namely whether the impact that is added between the power and ground is that ESD impacts; If ESD impacts, then send response signal to the transistor of releasing and open path; If normally power on, then do not open the transistor of releasing;
The transistor of releasing is opened path, and is interim for impacting at ESD, impacts the response signal of probe unit transmission according to ESD and sends a high voltage signal, opens the transistor of releasing;
The transistor of releasing turn-offs path, is used under ESD impacts, and for the transistor of releasing provides enough opening times, then turn-offs the transistor of releasing; Namely impact temporarily at ESD, after the transistor of releasing is opened, after the delay in the past that the CR time constant of by the time ESD impact probe unit is brought, provide again the regular hour to postpone to guarantee to release transistorized opening time long enough; After the static electricity discharge electric charge is complete, the transistor of releasing is turn-offed;
The transistor of releasing is used for impacting at ESD interim, enters rapidly low resistive state, and the ESD that releases impacts the electrostatic charge that brings.
Wherein, ESD impact probe unit comprises capacitor C 1 and resistance R 1; Capacitor C 1 top crown is connected with circuit power pin VDD, and bottom crown is connected with resistance R 1 one ends, resistance R 1 other end ground connection; Variation is exactly the structure that protective circuit itself has reduced the one-level inverter to use the CR structure to replace RC+ inverter structure of the prior art to bring the most intuitively as ESD impact probe unit, so that more the simplifying in structure shown in Figure 1 of the present invention, to a great extent so that circuit is more succinct; In addition, such improvement also can prolong the transistorized opening time of releasing to a certain extent.
Wherein, the transistor of releasing is nmos pass transistor Mbig, and nmos pass transistor Mbig grid opens path with the transistor of releasing respectively and the transistor of releasing shutoff path is connected, source ground, and drain electrode is connected with circuit power pin VDD.
Wherein, the transistor of releasing is opened path and is comprised PMOS transistor Mp2, Mp3 and nmos pass transistor Mn2; The grid of PMOS transistor Mp2 turn-offs path with the bottom crown of capacitor C 1, the transistor of releasing respectively and nmos pass transistor Mn2 grid is connected, source electrode is connected with circuit power pin VDD, and drain electrode is connected with PMOS transistor Mp3 grid and nmos pass transistor Mn2 drain electrode respectively; PMOS transistor Mp3 source electrode is connected with circuit power pin VDD, and drain electrode is turn-offed path with nmos pass transistor Mbig grid and the transistor of releasing respectively and is connected; Nmos pass transistor Mn2 source ground.
Wherein, the transistor of releasing shutoff path comprises PMOS transistor Mp4, Mp5, Mp6, nmos pass transistor Mn3, Mn4, capacitor C 2, C3, the first current lens unit and the second current lens unit; PMOS transistor Mp4 grid is connected with PMOS transistor Mp5 drain electrode, capacitor C 2 top crowns, nmos pass transistor Mn4 grid and the first current lens unit respectively, source electrode is connected with circuit power pin VDD, and drain electrode is connected with PMOS transistor Mp6 grid and nmos pass transistor Mn4 drain electrode respectively; PMOS transistor Mp5 grid is connected with capacitor C 1 bottom crown, and source electrode is connected with circuit power pin VDD; PMOS transistor Mp6 source electrode is connected with circuit power pin VDD, and drain electrode is connected with nmos pass transistor Mn3 grid, capacitor C 3 top crowns and the second current lens unit respectively; Nmos pass transistor Mn3 source ground, drain electrode is connected with nmos pass transistor Mbig grid; Nmos pass transistor Mn4 source ground; Use current mirror namely to add extra active device by the electric capacity that the transistor of releasing is turn-offed path and come equivalent passive device electric capacity is done greatly, can obtain with less chip area so on the one hand the larger passive device of equivalence, on the other hand, can prolong the transistorized opening time of releasing.
Wherein, the first current lens unit comprises nmos pass transistor Man1, Man2; Nmos pass transistor Man1 grid is connected source ground with capacitor C 2 bottom crowns, nmos pass transistor Man1 drain electrode and nmos pass transistor Man2 grid respectively; Nmos pass transistor Man2 source ground, drain electrode is connected with the top crown of capacitor C 2;
The second current lens unit comprises nmos pass transistor Mbn1, Mbn2; Nmos pass transistor Mbn1 grid is connected source ground with capacitor C 3 bottom crowns, nmos pass transistor Mbn1 drain electrode and nmos pass transistor Mbn2 grid respectively; Nmos pass transistor Mbn2 source ground, drain electrode is connected with the top crown of capacitor C 3.
Can find out from above-described embodiment, a kind of multiple RC of the present invention triggers power supply clamper esd protection circuit and is with respect to one of the main improvement of power supply clamper esd protection circuit in the prior art as shown in Figure 1: replace the RC+ inverter structure to be used as ESD impact probe unit with the CR structure; Such improvement brings the most intuitively that to change be exactly the structure that protective circuit itself has reduced the one-level inverter, so that more the simplifying in protective circuit structure of the prior art of the present invention.
Be CR structure and RC+ inverter structure shown in Fig. 3 under same ESD impacts, output voltage is curve chart over time.Wherein, V shown in the solid line
RCBe the output of RC+ inverter structure under ESD impacts, V shown in the dotted line
CRBe the output of CR structure under ESD impacts.As we can see from the figure: after two curve voltages were all drawn high, the speed that CR structure output voltage is dragged down obviously will be slower than the RC+ inverter structure.In theory, the absolute value of the slope of the direct current transmission characteristic of inverter is infinitely-great, and the rate of change of CR structure output voltage depends on the size of CR self time constant; Although it is slow that the speed ratio RC+ inverter structure that the CR structure voltage is dragged down is wanted, because the too late RC+ inverter structure of maximum of CR structure output voltage under ESD impacts, so two curves have an intersection point among the figure, the coordinate of definition intersection point is (T
c, V
c); Under the ESD impact, when the output voltage values of ESD impact probe unit was reduced to a certain degree, the transistor of releasing turn-offs path to begin to start, and the critical voltage that defines the transistor shutoff path startup of releasing is V
OffV
OffSize turn-off path equivalent delay time constant R with the transistor of releasing
Mp5* C
C2And R
Mp6* C
C3Positive correlation.
If V
Off＜V
cUnder same ESD impacts; CR structure output voltage reaches the critical voltage time of the transistor shutoff path unlatching of releasing just than RC+ inverter structure length, and such first improvement not only makes whole protection structure be simplified, and prolongs but also be beneficial to the transistor open-interval of releasing.If V
OffV
cUnder same ESD impacts; it is just short than RC+ inverter structure that CR structure output voltage reaches the critical voltage required time of the transistor shutoff path unlatching of releasing; so; first improvement can shorten the transistorized opening time of releasing to a certain extent, and this is the requirement that runs counter to protection reliability.
In order to ensure condition V
Off＜V
cSet up, a kind of multiple RC of the present invention triggers power supply clamper esd protection circuit and is with respect to two of the main improvement of power supply clamper esd protection circuit in the prior art as shown in Figure 1: the electric capacity that the transistor of releasing is turn-offed path has used current lens unit; If passive capacitive and current lens unit are regarded as an equivalent capacity structure, the total current size of equivalent capacity structure is exactly that the current lens unit of passive capacitive size of current copies multiple and adds 1 times so, thus, the equivalent capacitance value of equivalent capacity structure will increase several times than passive capacitive.
Introduce current lens unit in the transistor shutoff path of releasing, realized obtaining with less chip area on the one hand the effect of larger equivalent delay, this transistor open-interval under ESD impacts that is conducive to release itself prolongs; On the other hand, the transistor of releasing turn-offs after the equivalent delay increase of path, can guarantee V
Off＜V
c, such first improvement increases the transistor open-interval effect of releasing and also can be guaranteed.
As shown in Figure 4, wherein, V
RefRepresent in the prior art protective circuit under ESD impacts, release the transistor grid voltage over time, V
pRepresent protective circuit of the present invention under ESD impacts, release the transistor grid voltage over time; As can be seen from the figure, by the mutual reinforcement of first improvement and second point improvement effect, V
pThe time that remains high level is compared V
RefTwice more than.
As shown in Figure 5, wherein, V
RefRepresent in the prior art protective circuit and when normally powering on, release the transistor grid voltage over time, V
pRepresent circuit shown in Figure 2 when normally powering on, release the transistor grid voltage over time; As can be seen from the figure, protective circuit of the present invention has not only effectively prolonged under the ESD impact releases the transistorized opening time, and has reduced the transistorized electric leakage of releasing when normally powering on.
In sum; a kind of multiple RC of the present invention triggers power supply clamper esd protection circuit not only can reasonably effectively prolong the opening time of transistor under ESD impacts of releasing under the chip area; and can guarantee protective circuit when normally powering on, leak electricity very little, for the normal operation that guarantees integrated circuit (IC) chip provides strong technical support.
Above execution mode only is used for explanation the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; in the situation that do not break away from the spirit and scope of the present invention; can also make a variety of changes and modification, so all technical schemes that are equal to also belong to protection category of the present invention.
Claims (6)
1. a multiple RC triggers power supply clamper esd protection circuit, it is characterized in that, comprise ESD impact probe unit and respectively the connected transistor of releasing open path and the transistor of releasing turn-offs path, the described transistor of releasing is opened path and the transistor of releasing and is turn-offed path and be connected with the transistor of releasing respectively;
Described ESD impacts probe unit, and whether be used for surveying has electrostatic pulse to access this circuit; If have, then send response signal to the described transistor of releasing and open path;
The described transistor of releasing is opened path, is used for opening the transistor of releasing according to described response signal;
The described transistor of releasing turn-offs path, is used under ESD impacts, and for the transistor of releasing provides enough opening times, then turn-offs the transistor of releasing;
The described transistor of releasing, the electrostatic charge that the described electrostatic pulse that is used for releasing is brought.
2. protective circuit according to claim 1 is characterized in that, described ESD impacts probe unit and comprises capacitor C 1 and resistance R 1; Described capacitor C 1 top crown is connected with circuit power pin VDD, and bottom crown is connected with described resistance R 1 one ends, described resistance R 1 other end ground connection.
3. protective circuit according to claim 2; it is characterized in that; the described transistor of releasing is nmos pass transistor Mbig; described nmos pass transistor Mbig grid opens path with the described transistor of releasing respectively and the transistor of releasing shutoff path is connected; source ground, drain electrode is connected with circuit power pin VDD.
4. protective circuit according to claim 3 is characterized in that, the described transistor of releasing is opened path and comprised PMOS transistor Mp2, Mp3 and nmos pass transistor Mn2; The grid of described PMOS transistor Mp2 turn-offs path with the bottom crown of described capacitor C 1, the transistor of releasing respectively and nmos pass transistor Mn2 grid is connected, source electrode is connected with circuit power pin VDD, and drain electrode is connected with described PMOS transistor Mp3 grid and nmos pass transistor Mn2 drain electrode respectively; Described PMOS transistor Mp3 source electrode is connected with circuit power pin VDD, and drain electrode is turn-offed path with described nmos pass transistor Mbig grid and the transistor of releasing respectively and is connected; Described nmos pass transistor Mn2 source ground.
5. protective circuit according to claim 4 is characterized in that, the described transistor of releasing turn-offs path and comprises PMOS transistor Mp4, Mp5, Mp6, nmos pass transistor Mn3, Mn4, capacitor C 2, C3, the first current lens unit and the second current lens unit; Described PMOS transistor Mp4 grid is connected with described PMOS transistor Mp5 drain electrode, capacitor C 2 top crowns, nmos pass transistor Mn4 grid and the first current lens unit respectively, source electrode is connected with circuit power pin VDD, and drain electrode is connected with described PMOS transistor Mp6 grid and nmos pass transistor Mn4 drain electrode respectively; Described PMOS transistor Mp5 grid is connected with described capacitor C 1 bottom crown, and source electrode is connected with circuit power pin VDD; Described PMOS transistor Mp6 source electrode is connected with circuit power pin VDD, and drain electrode is connected with described nmos pass transistor Mn3 grid, capacitor C 3 top crowns and the second current lens unit respectively; Described nmos pass transistor Mn3 source ground, drain electrode is connected with described nmos pass transistor Mbig grid; Described nmos pass transistor Mn4 source ground.
6. protective circuit according to claim 5 is characterized in that, described the first current lens unit comprises nmos pass transistor Man1, Man2; Described nmos pass transistor Man1 grid is connected source ground with described capacitor C 2 bottom crowns, nmos pass transistor Man1 drain electrode and nmos pass transistor Man2 grid respectively; Described nmos pass transistor Man2 source ground, drain electrode is connected with the top crown of described capacitor C 2;
Described the second current lens unit comprises nmos pass transistor Mbn1, Mbn2; Described nmos pass transistor Mbn1 grid is connected source ground with described capacitor C 3 bottom crowns, nmos pass transistor Mbn1 drain electrode and nmos pass transistor Mbn2 grid respectively; Described nmos pass transistor Mbn2 source ground, drain electrode is connected with the top crown of described capacitor C 3.
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