CN115047930B - A bandgap reference circuit - Google Patents

A bandgap reference circuit Download PDF

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CN115047930B
CN115047930B CN202210580109.1A CN202210580109A CN115047930B CN 115047930 B CN115047930 B CN 115047930B CN 202210580109 A CN202210580109 A CN 202210580109A CN 115047930 B CN115047930 B CN 115047930B
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pmos tube
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pmos
gate
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CN115047930A (en
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孙大鹰
朱凯
王冲
顾文华
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Nanjing University of Science and Technology
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Nanjing University of Science and Technology
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current 
    • G05F1/46—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56—Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

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Abstract

本申请提供了一种带隙基准电路，包括：带隙基准启动电路和基准电压产生电路；带隙基准启动电路包括延时电路、低电流关断电路和ESD保护单元；带隙基准电压产生电路包括运算跨导放大器和基准电压核心电路。本申请启动电路一方面可以使带隙电路脱离非平衡工作点正常工作并可以自动关断启动电路，降低静态功耗；另一方面电路设计ESD静电防护单元，可以有效防止器件的静电损伤，保证电路工作的稳定性和可靠性。

The present application provides a bandgap reference circuit, including: a bandgap reference startup circuit and a reference voltage generation circuit; the bandgap reference startup circuit includes a delay circuit, a low current shutdown circuit and an ESD protection unit; the bandgap reference voltage generation circuit includes an operational transconductance amplifier and a reference voltage core circuit. On the one hand, the startup circuit of the present application can enable the bandgap circuit to work normally away from an unbalanced operating point and can automatically shut down the startup circuit to reduce static power consumption; on the other hand, the circuit is designed with an ESD electrostatic protection unit, which can effectively prevent electrostatic damage to the device and ensure the stability and reliability of the circuit operation.

Description

一种带隙基准电路A bandgap reference circuit

技术领域Technical Field

本申请涉及模拟集成电路技术领域，特别涉及一种带隙基准电路。The present application relates to the technical field of analog integrated circuits, and in particular to a bandgap reference circuit.

背景技术Background technique

随着集成技术的快速发展，带隙基准广泛应用于各种模拟、模数混合、电源管理等集成电路中。带隙基准的设计好坏直接影响芯片的整体性能，高精度比较器、A/D和D/A转换器等都需要带隙基准源提供稳定精确的基准电压。因此，提高带隙基准源的性能对于提高系统工作的可靠性和稳定性有重要意义。With the rapid development of integrated technology, bandgap references are widely used in various integrated circuits such as analog, analog-digital hybrid, and power management. The design of the bandgap reference directly affects the overall performance of the chip. High-precision comparators, A/D and D/A converters all require bandgap reference sources to provide stable and accurate reference voltages. Therefore, improving the performance of the bandgap reference source is of great significance to improving the reliability and stability of the system.

带隙基准电路的启动电路，具有避免带隙基准电路的支路电流处于零状态(简并点)，输出电压恒定为零，无法正常工作的状态。而现有技术中，带隙基准电路的启动电路不管是通过电流镜像启动，还是通过输出电压反馈控制等等，在启动完成后，启动电路仍然存在一部分电流损耗。The startup circuit of the bandgap reference circuit has the function of preventing the branch current of the bandgap reference circuit from being in a zero state (degenerate point), the output voltage being constant at zero, and the state of being unable to work normally. In the prior art, whether the startup circuit of the bandgap reference circuit is started by current mirroring or by output voltage feedback control, etc., after the startup is completed, the startup circuit still has a part of current loss.

同时，带隙基准电路正常工作时，由于外部接口的ESD浪涌而遭受损坏的风险不可忽视。静电释放对器件的损伤是不可估量的，静电放电是电子产品质量最大的潜在杀手，它可以使器件严重损坏、功能丧失，因此，ESD防护是提高电路工作稳定性与可靠性不可忽视的一环。但是，At the same time, when the bandgap reference circuit is working normally, the risk of damage due to ESD surges on the external interface cannot be ignored. The damage to the device caused by electrostatic discharge is immeasurable. Electrostatic discharge is the biggest potential killer of electronic product quality. It can cause serious damage to the device and loss of function. Therefore, ESD protection is an important part of improving the stability and reliability of circuit operation. However,

带隙基准电路中没有设计ESD保护单元。No ESD protection unit is designed in the bandgap reference circuit.

发明内容Summary of the invention

本申请公开了一种带隙基准电路，用于解决带隙基准电路摆脱兼并点并关断启动电路的过程中，存在功耗的问题。The present application discloses a bandgap reference circuit, which is used to solve the problem of power consumption in the process of the bandgap reference circuit getting rid of the merger point and shutting down the startup circuit.

本申请提供了一种带隙基准电路，包括，带隙基准启动电路和带隙基准电压产生电路；The present application provides a bandgap reference circuit, including a bandgap reference startup circuit and a bandgap reference voltage generation circuit;

所述带隙基准启动电路包括延时电路、低电流关断电路和ESD保护单元；The bandgap reference startup circuit includes a delay circuit, a low current shutdown circuit and an ESD protection unit;

所述带隙基准电压产生电路包括运算跨导放大器和基准电压核心电路；The bandgap reference voltage generating circuit comprises an operational transconductance amplifier and a reference voltage core circuit;

所述延时电路通过电流用于产生时间延迟，并启动电路关断信号；The delay circuit passes current to generate a time delay and initiates a circuit shutdown signal;

所述低电流关断电路用于关断关断信号来临的支路；The low current shutdown circuit is used to shut down the branch when the shutdown signal comes;

所述ESD保护单元用于保护电路；The ESD protection unit is used to protect the circuit;

所述运算跨导放大器用于发挥钳位功能；The operational transconductance amplifier is used to perform a clamping function;

所述基准电压核心电路用于产生零温度系数的电压。The reference voltage core circuit is used to generate a voltage with a zero temperature coefficient.

可选的，所述延时电路包括：Optionally, the delay circuit includes:

第一PMOS管、第一NMOS管、第二PMOS管、第二NMOS管、第三PMOS管、第四PMOS管以及第三NMOS管；A first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube, a third PMOS tube, a fourth PMOS tube and a third NMOS tube;

所述第一PMOS管的源极连接电源，所述第一PMOS管的栅极连接基准电压产生电路的第九PMOS管，第十PMOS管，第十五PMOS管和第十六PMOS管的栅极；The source of the first PMOS tube is connected to a power supply, and the gate of the first PMOS tube is connected to the gates of a ninth PMOS tube, a tenth PMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube of a reference voltage generating circuit;

所述第一NMOS管的栅极与第一PMOS管的漏极连接，所述第一NMOS管的源极与地连接，所述第一NMOS管的漏极与地连接；The gate of the first NMOS tube is connected to the drain of the first PMOS tube, the source of the first NMOS tube is connected to the ground, and the drain of the first NMOS tube is connected to the ground;

所述第二PMOS管的源极连接电源，所述第二PMOS管的漏极与第一PMOS管的漏极连接，所述第二PMOS管的栅极与第三PMOS管的漏极连接；The source of the second PMOS tube is connected to a power supply, the drain of the second PMOS tube is connected to the drain of the first PMOS tube, and the gate of the second PMOS tube is connected to the drain of the third PMOS tube;

所述第三PMOS管的栅极连接第一NMOS管的栅极，所述第三PMOS管的源极连接电源，所述第三PMOS管的漏极连接第二NMOS管的漏极；The gate of the third PMOS tube is connected to the gate of the first NMOS tube, the source of the third PMOS tube is connected to the power supply, and the drain of the third PMOS tube is connected to the drain of the second NMOS tube;

所述第二NMOS管的栅极连接第一NMOS管的栅极，所述的第二NMOS管源极连接地，所述第二NMOS管的漏极连接第三PMOS管的漏极；The gate of the second NMOS tube is connected to the gate of the first NMOS tube, the source of the second NMOS tube is connected to the ground, and the drain of the second NMOS tube is connected to the drain of the third PMOS tube;

所述第四PMOS管的栅极连接第三PMOS管的漏极，所述第四PMOS管的源极连接电源，所述第四PMOS管的漏极连接第三NMOS管的漏极；The gate of the fourth PMOS tube is connected to the drain of the third PMOS tube, the source of the fourth PMOS tube is connected to the power supply, and the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube;

所述的第三NMOS管栅极连接第二NMOS的漏极，所述的第三NMOS管源极连接地，所述的第三NMOS管漏极连接第四PMOS的漏极。The gate of the third NMOS tube is connected to the drain of the second NMOS tube, the source of the third NMOS tube is connected to the ground, and the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube.

可选的，所述低电流关断电路包括：Optionally, the low current shutdown circuit includes:

第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第四NMOS管以及第六NMOS管；a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube and a sixth NMOS tube;

所述的第五PMOS管栅极连接第六PMOS管的栅极、第七PMOS管的栅极和漏极，所述的第五PMOS管源极连接电源，所述的第五PMOS管漏极连接第六PMOS管的源极；The gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, the gate and the drain of the seventh PMOS tube, the source of the fifth PMOS tube is connected to the power supply, and the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube;

所述的第六PMOS管栅极连接第七PMOS管的栅极，所述的第六PMOS管源极连接第五PMOS管的漏极，所述的第六PMOS管漏极连接第七PMOS管的源极；The gate of the sixth PMOS tube is connected to the gate of the seventh PMOS tube, the source of the sixth PMOS tube is connected to the drain of the fifth PMOS tube, and the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube;

所述的第七PMOS管栅极连接第七PMOS管的漏极，所述的第七PMOS管源极连接第六PMOS管的漏极，所述第七PMOS管的漏极连接第八PMOS管的源极；The gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube, the source of the seventh PMOS tube is connected to the drain of the sixth PMOS tube, and the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube;

所述第八PMOS管的栅极连接第四PMOS管的漏极，所述第八PMOS管的源极连接第七PMOS管的漏极，所述第八PMOS管的漏极连接第五NMOS管的漏极、第四NMOS管漏极；The gate of the eighth PMOS tube is connected to the drain of the fourth PMOS tube, the source of the eighth PMOS tube is connected to the drain of the seventh PMOS tube, and the drain of the eighth PMOS tube is connected to the drain of the fifth NMOS tube and the drain of the fourth NMOS tube;

所述第四NMOS管的栅极连接第四PMOS管的漏极，所述第四NMOS管的源极连接地，所述第四NMOS管的漏极连接第五NMOS管的漏极；The gate of the fourth NMOS tube is connected to the drain of the fourth PMOS tube, the source of the fourth NMOS tube is connected to the ground, and the drain of the fourth NMOS tube is connected to the drain of the fifth NMOS tube;

所述第六NMOS管的栅极连接第五NMOS管的漏极，所述第六NMOS管的源极连接地，所述第六NMOS管的漏极连接第一PMOS管、第九PMOS管、第十PMOS管、第十五PMOS管和第十六PMOS管的栅极。The gate of the sixth NMOS tube is connected to the drain of the fifth NMOS tube, the source of the sixth NMOS tube is connected to the ground, and the drain of the sixth NMOS tube is connected to the gates of the first PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube.

可选的，所述ESD保护单元包括：Optionally, the ESD protection unit includes:

第五NMOS管，所述第五NMOS管的栅极连接地，所述第五NMOS管的源极连接地，所述第五NMOS管的漏极连接第八PMOS管的漏极。A fifth NMOS tube, wherein a gate of the fifth NMOS tube is connected to the ground, a source of the fifth NMOS tube is connected to the ground, and a drain of the fifth NMOS tube is connected to the drain of the eighth PMOS tube.

可选的，所述运算跨导放大器包括：Optionally, the operational transconductance amplifier includes:

第九PMOS管、第十PMOS管、第十一PMOS管、第十二PMOS管、第七NMOS管、第八NMOS管、第十三PMOS管、第十四PMOS管、第九NMOS管、第十NMOS管、第十一NMOS管以及第十二NMOS管；a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, and a twelfth NMOS tube;

所述第九PMOS管的栅极连接第十PMOS管的栅极，所述第九PMOS管的源极连接电源，所述第九PMOS管的漏极连接第七NMOS管的漏极；The gate of the ninth PMOS tube is connected to the gate of the tenth PMOS tube, the source of the ninth PMOS tube is connected to the power supply, and the drain of the ninth PMOS tube is connected to the drain of the seventh NMOS tube;

所述第十PMOS管的栅极连接第九PMOS管的栅极，所述第十PMOS管的源极连接电源，所述第十PMOS管的漏极连接第十一PMOS管和第十二PMOS管的源极；The gate of the tenth PMOS tube is connected to the gate of the ninth PMOS tube, the source of the tenth PMOS tube is connected to a power supply, and the drain of the tenth PMOS tube is connected to the sources of the eleventh PMOS tube and the twelfth PMOS tube;

所述第十一PMOS管的栅极连接第三电阻R3的正端，所述第十一PMOS管的源极连接第十PMOS管的漏极，所述第十一PMOS管的漏极连接第十一NMOS管的漏极；The gate of the eleventh PMOS tube is connected to the positive end of the third resistor R3 , the source of the eleventh PMOS tube is connected to the drain of the tenth PMOS tube, and the drain of the eleventh PMOS tube is connected to the drain of the eleventh NMOS tube;

所述第十二PMOS管的栅极连接第一电阻R1的负端，所述第十二PMOS管的源极连接第十PMOS管的漏极，所述第十二PMOS管的漏极连接第十二NMOS的漏极；The gate of the twelfth PMOS tube is connected to the negative end of the first resistor R1 , the source of the twelfth PMOS tube is connected to the drain of the tenth PMOS tube, and the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS;

所述第七NMOS管的栅极连接第七NMOS管的漏极，所述第七NMOS管的源极连接第八NMOS管的漏极，所述第七NMOS管的漏极连接第九PMOS管的漏极；The gate of the seventh NMOS tube is connected to the drain of the seventh NMOS tube, the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube, and the drain of the seventh NMOS tube is connected to the drain of the ninth PMOS tube;

所述第八NMOS管的栅极连接第八NMOS管的漏极，所述第八NMOS管的源极连接地，所述第八NMOS管的漏极连接第七NMOS管的源极；The gate of the eighth NMOS tube is connected to the drain of the eighth NMOS tube, the source of the eighth NMOS tube is connected to the ground, and the drain of the eighth NMOS tube is connected to the source of the seventh NMOS tube;

所述第十三PMOS管的栅极连接第十四PMOS管的栅极和第十三PMOS管的漏极，所述第十三PMOS管的源极连接电源，所述第十三PMOS管的漏极连接第九NMOS管的漏极；The gate of the thirteenth PMOS tube is connected to the gate of the fourteenth PMOS tube and the drain of the thirteenth PMOS tube, the source of the thirteenth PMOS tube is connected to the power supply, and the drain of the thirteenth PMOS tube is connected to the drain of the ninth NMOS tube;

所述第十四PMOS管的栅极连接第十三PMOS管的栅极，所述第十四PMOS管的源极连接电源，所述第十四PMOS管的漏极连接第十NMOS管的漏极；The gate of the fourteenth PMOS tube is connected to the gate of the thirteenth PMOS tube, the source of the fourteenth PMOS tube is connected to the power supply, and the drain of the fourteenth PMOS tube is connected to the drain of the tenth NMOS tube;

所述第九NMOS管的栅极连接第七NMOS管和第十NMOS管的栅极，所述第九NMOS管的源极连接第十一NMOS管的漏极，所述第九NMOS管的漏极连接第十三PMOS的漏极；The gate of the ninth NMOS tube is connected to the gates of the seventh NMOS tube and the tenth NMOS tube, the source of the ninth NMOS tube is connected to the drain of the eleventh NMOS tube, and the drain of the ninth NMOS tube is connected to the drain of the thirteenth PMOS;

所述第十NMOS管的栅极连接第九NMOS管栅极，所述第十NMOS管的源极连接第十二NMOS管漏极，所述第十NMOS管的漏极连接第十四PMOS管的漏极；The gate of the tenth NMOS tube is connected to the gate of the ninth NMOS tube, the source of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, and the drain of the tenth NMOS tube is connected to the drain of the fourteenth PMOS tube;

所述第十一NMOS管的栅极连接第十二NMOS管栅极，所述第十一NMOS管的源极连接地，所述第十一NMOS管的漏极连接第九NMOS的源极；The gate of the eleventh NMOS tube is connected to the gate of the twelfth NMOS tube, the source of the eleventh NMOS tube is connected to the ground, and the drain of the eleventh NMOS tube is connected to the source of the ninth NMOS;

所述第十二NMOS管的栅极连接第十一NMOS管栅极，所述第十二NMOS管的源极连接地，所述第十二NMOS管的漏极连接第十NMOS管源极。The gate of the twelfth NMOS tube is connected to the gate of the eleventh NMOS tube, the source of the twelfth NMOS tube is connected to the ground, and the drain of the twelfth NMOS tube is connected to the source of the tenth NMOS tube.

可选的，所述基准电压核心电路包括：Optionally, the reference voltage core circuit includes:

第十五PMOS管、第十六PMOS管、第一电阻R1、第二电阻R2、第三电阻R3、第一三极管以及第二三极管；A fifteenth PMOS transistor, a sixteenth PMOS transistor, a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a first triode and a second triode;

所述第十五PMOS管的栅极连接第十六PMOS管栅极，所述第十五PMOS管的源极连接电源，所述第十五PMOS管的漏极连接第一电阻R1的正端；The gate of the fifteenth PMOS tube is connected to the gate of the sixteenth PMOS tube, the source of the fifteenth PMOS tube is connected to the power supply, and the drain of the fifteenth PMOS tube is connected to the positive end of the first resistor R1 ;

所述第十六PMOS管的栅极连接第十五PMOS管栅极，所述第十六PMOS管的源极连接电源，所述第十六PMOS管的漏极连接第二电阻R2正端；The gate of the sixteenth PMOS tube is connected to the gate of the fifteenth PMOS tube, the source of the sixteenth PMOS tube is connected to the power supply, and the drain of the sixteenth PMOS tube is connected to the positive end of the second resistor R2 ;

所述第一电阻R1正端连接第十五PMOS管漏极，所述第一电阻R1的负端连接第一三极管的集电极；The positive end of the first resistor R1 is connected to the drain of the fifteenth PMOS tube, and the negative end of the first resistor R1 is connected to the collector of the first transistor;

所述第二电阻R2正端连接第十六PMOS管漏极，所述第二电阻R2的负端连接第三电阻R3正端；The positive end of the second resistor R 2 is connected to the drain of the sixteenth PMOS tube, and the negative end of the second resistor R 2 is connected to the positive end of the third resistor R 3 ;

所述第三电阻R3正端连接第二电阻R2负端，所述第三电阻R3的负端连接第二三极管的集电极；The positive end of the third resistor R 3 is connected to the negative end of the second resistor R 2 , and the negative end of the third resistor R 3 is connected to the collector of the second transistor;

所述第一三极管的基极与第二三极管的基极连接，所述第一三极管发射极接地，所述第一三极管集电极连接第一电阻R1负端；The base of the first transistor is connected to the base of the second transistor, the emitter of the first transistor is grounded, and the collector of the first transistor is connected to the negative end of the first resistor R1 ;

所述第二三极管的基极与第一三极管的基极连接，所述第二三极管的发射极接地，所述第二三极管的集电极与第三电阻R3的负端连接。The base of the second transistor is connected to the base of the first transistor, the emitter of the second transistor is grounded, and the collector of the second transistor is connected to the negative end of the third resistor R3 .

本申请中提出的一种带隙基准电路，包括带隙基准启动电路和带隙基准电压产生电路，所述带隙基准启动电路中，若第一PMOS管的栅极为高电平，带隙基准电路则处于兼并点，电路无法正常工作输出电压，第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管均关断，第五PMOS管、第六PMOS管、第七PMOS管呈现电阻特性，第六NMOS管的栅极为高电平，第六NMOS管的漏极为低电平，此时第九PMOS管、第十PMOS管、第十五PMOS管、第十六PMOS管、第一PMOS管栅极为低电平，VB为高电平，启动电路被关断，带隙基准电路摆脱兼并点正常工作，启动电路关断，降低带隙基准电路的功耗。A bandgap reference circuit proposed in the present application includes a bandgap reference startup circuit and a bandgap reference voltage generating circuit. In the bandgap reference startup circuit, if the gate of the first PMOS tube is at a high level, the bandgap reference circuit is at a merge point, the circuit cannot normally operate and output voltage, the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube are all turned off, the fifth PMOS tube, the sixth PMOS tube, and the seventh PMOS tube present resistance characteristics, the gate of the sixth NMOS tube is at a high level, and the drain of the sixth NMOS tube is at a low level. At this time, the gates of the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube, the sixteenth PMOS tube, and the first PMOS tube are at a low level, VB is at a high level, the startup circuit is turned off, the bandgap reference circuit is freed from the merge point and operates normally, the startup circuit is turned off, and the power consumption of the bandgap reference circuit is reduced.

当输入电源电压突然产生一个较大的静电过冲时，通过第五、第六、第七PMOS管和第五NMOS管，构成ESD保护电路，通过第五NMOS管反向二极管泄放电流，保护电路。When the input power supply voltage suddenly generates a large electrostatic overshoot, the fifth, sixth, seventh PMOS tubes and the fifth NMOS tube form an ESD protection circuit, and the reverse diode of the fifth NMOS tube discharges current to protect the circuit.

附图说明BRIEF DESCRIPTION OF THE DRAWINGS

图1为本申请实施例提供的带隙基准电路结构示意图；FIG1 is a schematic diagram of a bandgap reference circuit structure provided in an embodiment of the present application;

图2为本申请实施例提供的带隙基准源的输出波形图；FIG2 is an output waveform diagram of a bandgap reference source provided in an embodiment of the present application;

图3为本申请实施例提供的带隙基准源的启动电路电流波形图。FIG3 is a current waveform diagram of a startup circuit of a bandgap reference source provided in an embodiment of the present application.

具体实施方式Detailed ways

下面结合附图和实施例对本申请进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对申请的限定。The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the application.

图1所示为本申请提供的一种带隙基准结构示意图，本实施例可以使电路摆脱简并态并关断启动电路，降低功耗。FIG1 is a schematic diagram of a bandgap reference structure provided by the present application. This embodiment can enable the circuit to escape from a degenerate state and shut down the startup circuit, thereby reducing power consumption.

附图标记说明如下：The following are the descriptions of the reference numerals:

1、启动电路，2、运算跨导放大器，3、基准电压核心电路；1. Start-up circuit, 2. Operational transconductance amplifier, 3. Reference voltage core circuit;

带隙基准启动电路中，P1、第一PMOS管，P2、第二PMOS管，P3、第三PMOS管，P4、第四PMOS管，P5、第五PMOS管，P6、第六PMOS管，P7、第七PMOS管，P8、第八PMOS管，N1、第一NMOS管，N2、第二NMOS管，N3、第三NMOS管，N4、第四NMOS管，N5、第五NMOS管，N6、第六NMOS管；In the bandgap reference startup circuit, P 1 is a first PMOS tube, P 2 is a second PMOS tube, P 3 is a third PMOS tube, P 4 is a fourth PMOS tube, P 5 is a fifth PMOS tube, P 6 is a sixth PMOS tube, P 7 is a seventh PMOS tube, P 8 is an eighth PMOS tube, N 1 is a first NMOS tube, N 2 is a second NMOS tube, N 3 is a third NMOS tube, N 4 is a fourth NMOS tube, N 5 is a fifth NMOS tube, and N 6 is a sixth NMOS tube;

跨导运算放大器中：P9、第九PMOS管，P10、第十PMOS管，P11、第十一PMOS管，P12、第十二PMOS管，P13、第十三PMOS管，P14、第十四PMOS管，N7、第七NMOS管，N8、第八NMOS管，N9、第九NMOS管，N10、第十NMOS管，N11、第十一NMOS管，N12、第十二NMOS管；In the transconductance operational amplifier: P9 , the ninth PMOS tube, P10 , the tenth PMOS tube, P11 , the eleventh PMOS tube, P12 , the twelfth PMOS tube, P13 , the thirteenth PMOS tube, P14 , the fourteenth PMOS tube, N7 , the seventh NMOS tube, N8 , the eighth NMOS tube, N9 , the ninth NMOS tube, N10 , the tenth NMOS tube, N11 , the eleventh NMOS tube, N12 , the twelfth NMOS tube;

基准电压核心电路中：P15、第十五PMOS管，P16、第十六PMOS管，R1、第一电阻，R2、第二电阻，R3、第三电阻，Q1、第一三极管，Q2、第二三极管。In the reference voltage core circuit: P 15 , the fifteenth PMOS tube, P 16 , the sixteenth PMOS tube, R 1 , the first resistor, R 2 , the second resistor, R 3 , the third resistor, Q 1 , the first triode, Q 2 , the second triode.

具体参考如图1所示，本实施例提供的一种带隙基准电路具体包括：带隙基准启动电路和带隙基准电压产生电路；Specific reference is made to FIG. 1 , a bandgap reference circuit provided in this embodiment specifically includes: a bandgap reference startup circuit and a bandgap reference voltage generation circuit;

带隙基准启动电路包括延时电路、低电流关断电路和ESD保护单元。The bandgap reference startup circuit includes a delay circuit, a low current shutdown circuit and an ESD protection unit.

带隙基准电压产生电路包括运算跨导放大器和基准电压核心电路。The bandgap reference voltage generating circuit comprises an operational transconductance amplifier and a reference voltage core circuit.

延时电路通过电流对MOSCAP进行充电，产生时间延迟，并经过反相器组产生启动电路关断信号。The delay circuit charges the MOSCAP through current to generate a time delay, and generates a startup circuit shutdown signal through an inverter group.

低电流关断电路通过两个MOS开关管在关断信号来临时，关断关断信号来临的支路。The low current shutdown circuit uses two MOS switch tubes to shut down the branch where the shutdown signal comes when the shutdown signal comes.

ESD保护单元用于保护电路。具体的，通过GGNMOS避免在基准突然上电或者静电释放时出现电流过大，损坏器件的情况。The ESD protection unit is used to protect the circuit. Specifically, the GGNMOS is used to prevent excessive current from damaging the device when the reference is suddenly powered on or when static electricity is released.

运算跨导放大器用于发挥钳位功能，具体的，采用折叠共源共栅结构实现电路的良好钳位功能，保证带隙基准电路工作的稳定性。The operational transconductance amplifier is used to play a clamping function. Specifically, a folded common source and common gate structure is used to achieve a good clamping function of the circuit to ensure the stability of the bandgap reference circuit.

基准电压核心电路，用于产生零温度系数的电压。具体的，通过支路电流相同，二极管比例不同的结构以及一定比例的电阻产生零温度系数的电压。The reference voltage core circuit is used to generate a voltage with a zero temperature coefficient. Specifically, the voltage with a zero temperature coefficient is generated through a structure with the same branch current, different diode ratios, and a certain ratio of resistors.

延时电路包括：The delay circuit includes:

第一PMOS管、第一NMOS管、第二PMOS管、第二NMOS管、第三PMOS管、第四PMOS管以及第三NMOS管。a first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube, a third PMOS tube, a fourth PMOS tube and a third NMOS tube.

第一PMOS管的源极连接电源，第一PMOS管的栅极连接基准电压产生电路的第九PMOS管，第十PMOS管，第十五PMOS管和第十六PMOS管的栅极。The source of the first PMOS tube is connected to the power supply, and the gate of the first PMOS tube is connected to the gates of the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube of the reference voltage generating circuit.

第一NMOS管的栅极与第一PMOS管的漏极连接，第一NMOS管的源极与地连接，第一NMOS管的漏极与地连接。The gate of the first NMOS tube is connected to the drain of the first PMOS tube, the source of the first NMOS tube is connected to the ground, and the drain of the first NMOS tube is connected to the ground.

第二PMOS管的源极连接电源，第二PMOS管的漏极与第一PMOS管的漏极连接，第二PMOS管的栅极与第三PMOS管的漏极连接。The source of the second PMOS tube is connected to the power supply, the drain of the second PMOS tube is connected to the drain of the first PMOS tube, and the gate of the second PMOS tube is connected to the drain of the third PMOS tube.

第三PMOS管的栅极连接第一NMOS管的栅极，第三PMOS管的源极连接电源，第三PMOS管的漏极连接第二NMOS管的漏极。The gate of the third PMOS tube is connected to the gate of the first NMOS tube, the source of the third PMOS tube is connected to the power supply, and the drain of the third PMOS tube is connected to the drain of the second NMOS tube.

第二NMOS管的栅极连接第一NMOS管的栅极，的第二NMOS管源极连接地，第二NMOS管的漏极连接第三PMOS管的漏极。The gate of the second NMOS tube is connected to the gate of the first NMOS tube, the source of the second NMOS tube is connected to the ground, and the drain of the second NMOS tube is connected to the drain of the third PMOS tube.

第四PMOS管的栅极连接第三PMOS管的漏极，第四PMOS管的源极连接电源，第四PMOS管的漏极连接第三NMOS管的漏极。The gate of the fourth PMOS tube is connected to the drain of the third PMOS tube, the source of the fourth PMOS tube is connected to the power supply, and the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube.

第三NMOS管栅极连接第二NMOS的漏极，的第三NMOS管源极连接地，的第三NMOS管漏极连接第四PMOS的漏极。The gate of the third NMOS tube is connected to the drain of the second NMOS tube, the source of the third NMOS tube is connected to the ground, and the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube.

低电流关断电路包括：The low current shutdown circuit includes:

第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第四NMOS管以及第六NMOS管。a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube and a sixth NMOS tube.

第五PMOS管栅极连接第六PMOS管的栅极、第七PMOS管的栅极和漏极，的第五PMOS管源极连接电源，的第五PMOS管漏极连接第六PMOS管的源极。The gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, the gate and the drain of the seventh PMOS tube, the source of the fifth PMOS tube is connected to the power supply, and the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube.

第六PMOS管栅极连接第七PMOS管的栅极，的第六PMOS管源极连接第五PMOS管的漏极，的第六PMOS管漏极连接第七PMOS管的源极。The gate of the sixth PMOS tube is connected to the gate of the seventh PMOS tube, the source of the sixth PMOS tube is connected to the drain of the fifth PMOS tube, and the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube.

第七PMOS管栅极连接第七PMOS管的漏极，的第七PMOS管源极连接第六PMOS管的漏极，第七PMOS管的漏极连接第八PMOS管的源极。The gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube, the source of the seventh PMOS tube is connected to the drain of the sixth PMOS tube, and the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube.

第八PMOS管的栅极连接第四PMOS管的漏极，第八PMOS管的源极连接第七PMOS管的漏极，第八PMOS管的漏极连接第五NMOS管的漏极、第四NMOS管漏极。The gate of the eighth PMOS tube is connected to the drain of the fourth PMOS tube, the source of the eighth PMOS tube is connected to the drain of the seventh PMOS tube, and the drain of the eighth PMOS tube is connected to the drain of the fifth NMOS tube and the drain of the fourth NMOS tube.

第四NMOS管的栅极连接第四PMOS管的漏极，第四NMOS管的源极连接地，第四NMOS管的漏极连接第五NMOS管的漏极。The gate of the fourth NMOS tube is connected to the drain of the fourth PMOS tube, the source of the fourth NMOS tube is connected to the ground, and the drain of the fourth NMOS tube is connected to the drain of the fifth NMOS tube.

第六NMOS管的栅极连接第五NMOS管的漏极，第六NMOS管的源极连接地，第六NMOS管的漏极连接第一PMOS管、第九PMOS管、第十PMOS管、第十五PMOS管和第十六PMOS管的栅极。The gate of the sixth NMOS tube is connected to the drain of the fifth NMOS tube, the source of the sixth NMOS tube is connected to the ground, and the drain of the sixth NMOS tube is connected to the gates of the first PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube.

ESD保护单元包括：The ESD protection unit includes:

第五NMOS管，第五NMOS管的栅极连接地，第五NMOS管的源极连接地，第五NMOS管的漏极连接第八PMOS管的漏极。A fifth NMOS tube, a gate of the fifth NMOS tube is connected to the ground, a source of the fifth NMOS tube is connected to the ground, and a drain of the fifth NMOS tube is connected to the drain of the eighth PMOS tube.

运算跨导放大器包括：Operational transconductance amplifiers include:

第九PMOS管、第十PMOS管、第十一PMOS管、第十二PMOS管、第七NMOS管、第八NMOS管、第十三PMOS管、第十四PMOS管、第九NMOS管、第十NMOS管、第十一NMOS管以及第十二NMOS管。a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube.

第九PMOS管的栅极连接第十PMOS管的栅极，第九PMOS管的源极连接电源，第九PMOS管的漏极连接第七NMOS管的漏极。The gate of the ninth PMOS tube is connected to the gate of the tenth PMOS tube, the source of the ninth PMOS tube is connected to the power supply, and the drain of the ninth PMOS tube is connected to the drain of the seventh NMOS tube.

第十PMOS管的栅极连接第九PMOS管的栅极，第十PMOS管的源极连接电源，第十PMOS管的漏极连接第十一PMOS管和第十二PMOS管的源极。The gate of the tenth PMOS tube is connected to the gate of the ninth PMOS tube, the source of the tenth PMOS tube is connected to the power supply, and the drain of the tenth PMOS tube is connected to the sources of the eleventh PMOS tube and the twelfth PMOS tube.

第十一PMOS管的栅极连接第三电阻R3的正端，第十一PMOS管的源极连接第十PMOS管的漏极，第十一PMOS管的漏极连接第十一NMOS管的漏极。The gate of the eleventh PMOS tube is connected to the positive end of the third resistor R3 , the source of the eleventh PMOS tube is connected to the drain of the tenth PMOS tube, and the drain of the eleventh PMOS tube is connected to the drain of the eleventh NMOS tube.

第十二PMOS管的栅极连接第一电阻R1的负端，第十二PMOS管的源极连接第十PMOS管的漏极，第十二PMOS管的漏极连接第十二NMOS的漏极。The gate of the twelfth PMOS tube is connected to the negative end of the first resistor R1 , the source of the twelfth PMOS tube is connected to the drain of the tenth PMOS tube, and the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS.

第七NMOS管的栅极连接第七NMOS管的漏极，第七NMOS管的源极连接第八NMOS管的漏极，第七NMOS管的漏极连接第九PMOS管的漏极。The gate of the seventh NMOS tube is connected to the drain of the seventh NMOS tube, the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube, and the drain of the seventh NMOS tube is connected to the drain of the ninth PMOS tube.

第八NMOS管的栅极连接第八NMOS管的漏极，第八NMOS管的源极连接地，第八NMOS管的漏极连接第七NMOS管的源极。The gate of the eighth NMOS tube is connected to the drain of the eighth NMOS tube, the source of the eighth NMOS tube is connected to the ground, and the drain of the eighth NMOS tube is connected to the source of the seventh NMOS tube.

第十三PMOS管的栅极连接第十四PMOS管的栅极和第十三PMOS管的漏极，第十三PMOS管的源极连接电源，第十三PMOS管的漏极连接第九NMOS管的漏极。The gate of the thirteenth PMOS tube is connected to the gate of the fourteenth PMOS tube and the drain of the thirteenth PMOS tube, the source of the thirteenth PMOS tube is connected to the power supply, and the drain of the thirteenth PMOS tube is connected to the drain of the ninth NMOS tube.

第十四PMOS管的栅极连接第十三PMOS管的栅极，第十四PMOS管的源极连接电源，第十四PMOS管的漏极连接第十NMOS管的漏极。The gate of the fourteenth PMOS tube is connected to the gate of the thirteenth PMOS tube, the source of the fourteenth PMOS tube is connected to the power supply, and the drain of the fourteenth PMOS tube is connected to the drain of the tenth NMOS tube.

第九NMOS管的栅极连接第七NMOS管和第十NMOS管的栅极，第九NMOS管的源极连接第十一NMOS管的漏极，第九NMOS管的漏极连接第十三PMOS的漏极。The gate of the ninth NMOS tube is connected to the gates of the seventh NMOS tube and the tenth NMOS tube, the source of the ninth NMOS tube is connected to the drain of the eleventh NMOS tube, and the drain of the ninth NMOS tube is connected to the drain of the thirteenth PMOS tube.

第十NMOS管的栅极连接第九NMOS管栅极，第十NMOS管的源极连接第十二NMOS管漏极，第十NMOS管的漏极连接第十四PMOS管的漏极。The gate of the tenth NMOS tube is connected to the gate of the ninth NMOS tube, the source of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, and the drain of the tenth NMOS tube is connected to the drain of the fourteenth PMOS tube.

第十一NMOS管的栅极连接第十二NMOS管栅极，第十一NMOS管的源极连接地，第十一NMOS管的漏极连接第九NMOS的源极。The gate of the eleventh NMOS tube is connected to the gate of the twelfth NMOS tube, the source of the eleventh NMOS tube is connected to the ground, and the drain of the eleventh NMOS tube is connected to the source of the ninth NMOS tube.

第十二NMOS管的栅极连接第十一NMOS管栅极，第十二NMOS管的源极连接地，第十二NMOS管的漏极连接第十NMOS管源极。The gate of the twelfth NMOS tube is connected to the gate of the eleventh NMOS tube, the source of the twelfth NMOS tube is connected to the ground, and the drain of the twelfth NMOS tube is connected to the source of the tenth NMOS tube.

基准电压核心电路包括：The reference voltage core circuit includes:

第十五PMOS管、第十六PMOS管、第一电阻R1、第二电阻R2、第三电阻R3、第一三极管以及第二三极管。A fifteenth PMOS transistor, a sixteenth PMOS transistor, a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a first transistor and a second transistor.

第十五PMOS管的栅极连接第十六PMOS管栅极，第十五PMOS管的源极连接电源，第十五PMOS管的漏极连接第一电阻R1的正端。The gate of the fifteenth PMOS tube is connected to the gate of the sixteenth PMOS tube, the source of the fifteenth PMOS tube is connected to the power supply, and the drain of the fifteenth PMOS tube is connected to the positive end of the first resistor R1 .

第十六PMOS管的栅极连接第十五PMOS管栅极，第十六PMOS管的源极连接电源，第十六PMOS管的漏极连接第二电阻R2正端。The gate of the sixteenth PMOS tube is connected to the gate of the fifteenth PMOS tube, the source of the sixteenth PMOS tube is connected to the power supply, and the drain of the sixteenth PMOS tube is connected to the positive end of the second resistor R2 .

第一电阻R1正端连接第十五PMOS管漏极，第一电阻R1的负端连接第一三极管的集电极。The positive end of the first resistor R1 is connected to the drain of the fifteenth PMOS tube, and the negative end of the first resistor R1 is connected to the collector of the first transistor.

第二电阻R2正端连接第十六PMOS管漏极，第二电阻R2的负端连接第三电阻R3正端。The positive end of the second resistor R 2 is connected to the drain of the sixteenth PMOS tube, and the negative end of the second resistor R 2 is connected to the positive end of the third resistor R 3 .

第三电阻R3正端连接第二电阻R2负端，第三电阻R3的负端连接第二三极管的集电极。The positive end of the third resistor R 3 is connected to the negative end of the second resistor R 2 , and the negative end of the third resistor R 3 is connected to the collector of the second transistor.

第一三极管的基极与第二三极管的基极连接，第一三极管发射极接地，第一三极管集电极连接第一电阻R1负端。The base of the first transistor is connected to the base of the second transistor, the emitter of the first transistor is grounded, and the collector of the first transistor is connected to the negative end of the first resistor R1 .

第二三极管的基极与第一三极管的基极连接，第二三极管的发射极接地，第二三极管的集电极与第三电阻R3的负端连接。The base of the second triode is connected to the base of the first triode, the emitter of the second triode is grounded, and the collector of the second triode is connected to the negative end of the third resistor R3 .

如图2所示，输出基准电压约为1.22V。As shown in Figure 2, the output reference voltage is approximately 1.22V.

如图3所示，启动电路损耗的电流近乎为零，实现启动电路的真关断，节省功耗。As shown in FIG3 , the current loss of the startup circuit is almost zero, thereby achieving true shutdown of the startup circuit and saving power consumption.

进一步地，第一电阻R1与第二电阻R2阻值相同，第三电阻R3阻值与第一电阻R1、第二电阻R2可调，以便能够调整输出电压VBG的范围。Furthermore, the first resistor R 1 and the second resistor R 2 have the same resistance value, and the third resistor R 3 has an adjustable resistance value as the first resistor R 1 and the second resistor R 2 , so as to adjust the range of the output voltage V BG .

上述带隙基准电路的输出电压VBG为：The output voltage V BG of the above bandgap reference circuit is:

其中，ΔVBE为三极管基极-发射极电压，n为第一三极管与第二三极管的个数比例系数，VT＝26mV(300K)，R1为第一电阻的阻值，R2为第二电阻的阻值。Wherein, ΔV BE is the base-emitter voltage of the transistor, n is the ratio coefficient of the number of the first transistor and the second transistor, VT=26mV (300K), R 1 is the resistance value of the first resistor, and R 2 is the resistance value of the second resistor.

根据输出电压VBG的表达式可以看出，输出电压是通过调整R1、R2的大小来改变，或者调整三极管的个数，实现输出电压可调的情况下保持温度系数不变。According to the expression of output voltage V BG, it can be seen that the output voltage is changed by adjusting the size of R 1 and R 2 , or adjusting the number of transistors, so as to keep the temperature coefficient unchanged while the output voltage is adjustable.

上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

由上述技术方案可知，本申请的有益效果为：It can be seen from the above technical solution that the beneficial effects of this application are:

本申请中提出的一种带隙基准电路，包括带隙基准启动电路和带隙基准电压产生电路，所述带隙基准启动电路中，若第一PMOS管的栅极为高电平，带隙基准电路则处于兼并点，电路无法正常工作输出电压，第一PMOS管、第二PMOS管、第三PMOS管、第四PMOS管均关断，第五PMOS管、第六PMOS管、第七PMOS管呈现电阻特性，第六NMOS管的栅极为高电平，第六NMOS管的漏极为低电平，此时第九PMOS管、第十PMOS管、第十五PMOS管、第十六PMOS管、第一PMOS管栅极为低电平，VB为高电平，启动电路被关断，带隙基准电路摆脱兼并点正常工作，启动电路关断，降低带隙基准电路的功耗。A bandgap reference circuit proposed in the present application includes a bandgap reference startup circuit and a bandgap reference voltage generating circuit. In the bandgap reference startup circuit, if the gate of the first PMOS tube is at a high level, the bandgap reference circuit is at a merge point, the circuit cannot normally operate and output voltage, the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube are all turned off, the fifth PMOS tube, the sixth PMOS tube, and the seventh PMOS tube present resistance characteristics, the gate of the sixth NMOS tube is at a high level, and the drain of the sixth NMOS tube is at a low level. At this time, the gates of the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube, the sixteenth PMOS tube, and the first PMOS tube are at a low level, VB is at a high level, the startup circuit is turned off, the bandgap reference circuit is freed from the merge point and operates normally, the startup circuit is turned off, and the power consumption of the bandgap reference circuit is reduced.

当输入电源电压突然产生一个较大的静电过冲时，通过第五、第六、第七PMOS管和第五NMOS管，构成ESD保护电路，通过第五NMOS管反向二极管泄放电流，保护电路。When the input power supply voltage suddenly generates a large electrostatic overshoot, the fifth, sixth, seventh PMOS tubes and the fifth NMOS tube form an ESD protection circuit, and the reverse diode of the fifth NMOS tube discharges current to protect the circuit.

Claims (3)

1.一种带隙基准电路，其特征在于，所述带隙基准电路包括，带隙基准启动电路和带隙基准电压产生电路；1. A bandgap reference circuit, characterized in that the bandgap reference circuit comprises a bandgap reference startup circuit and a bandgap reference voltage generating circuit; 所述带隙基准启动电路包括延时电路、低电流关断电路和ESD保护单元；The bandgap reference startup circuit includes a delay circuit, a low current shutdown circuit and an ESD protection unit; 所述带隙基准电压产生电路包括运算跨导放大器和基准电压核心电路；The bandgap reference voltage generating circuit comprises an operational transconductance amplifier and a reference voltage core circuit; 所述延时电路通过电流用于产生时间延迟，并启动电路关断信号；The delay circuit passes current to generate a time delay and initiates a circuit shutdown signal; 所述低电流关断电路用于关断关断信号来临的支路；The low current shutdown circuit is used to shut down the branch when the shutdown signal comes; 所述ESD保护单元用于保护电路；The ESD protection unit is used to protect the circuit; 所述运算跨导放大器用于发挥钳位功能；The operational transconductance amplifier is used to perform a clamping function; 所述基准电压核心电路用于产生零温度系数的电压；The reference voltage core circuit is used to generate a voltage with a zero temperature coefficient; 所述延时电路包括：The delay circuit comprises: 第一PMOS管、第一NMOS管、第二PMOS管、第二NMOS管、第三PMOS管、第四PMOS管以及第三NMOS管；A first PMOS tube, a first NMOS tube, a second PMOS tube, a second NMOS tube, a third PMOS tube, a fourth PMOS tube and a third NMOS tube; 所述第一PMOS管的源极连接电源，所述第一PMOS管的栅极连接基准电压产生电路的第九PMOS管，第十PMOS管，第十五PMOS管和第十六PMOS管的栅极；The source of the first PMOS tube is connected to a power supply, and the gate of the first PMOS tube is connected to the gates of a ninth PMOS tube, a tenth PMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube of a reference voltage generating circuit; 所述第一NMOS管的栅极与第一PMOS管的漏极连接，所述第一NMOS管的源极与地连接，所述第一NMOS管的漏极与地连接；The gate of the first NMOS tube is connected to the drain of the first PMOS tube, the source of the first NMOS tube is connected to the ground, and the drain of the first NMOS tube is connected to the ground; 所述第二PMOS管的源极连接电源，所述第二PMOS管的漏极与第一PMOS管的漏极连接，所述第二PMOS管的栅极与第三PMOS管的漏极连接；The source of the second PMOS tube is connected to a power supply, the drain of the second PMOS tube is connected to the drain of the first PMOS tube, and the gate of the second PMOS tube is connected to the drain of the third PMOS tube; 所述第三PMOS管的栅极连接第一NMOS管的栅极，所述第三PMOS管的源极连接电源，所述第三PMOS管的漏极连接第二NMOS管的漏极；The gate of the third PMOS tube is connected to the gate of the first NMOS tube, the source of the third PMOS tube is connected to the power supply, and the drain of the third PMOS tube is connected to the drain of the second NMOS tube; 所述第二NMOS管的栅极连接第一NMOS管的栅极，所述的第二NMOS管源极连接地，所述第二NMOS管的漏极连接第三PMOS管的漏极；The gate of the second NMOS tube is connected to the gate of the first NMOS tube, the source of the second NMOS tube is connected to the ground, and the drain of the second NMOS tube is connected to the drain of the third PMOS tube; 所述第四PMOS管的栅极连接第三PMOS管的漏极，所述第四PMOS管的源极连接电源，所述第四PMOS管的漏极连接第三NMOS管的漏极；The gate of the fourth PMOS tube is connected to the drain of the third PMOS tube, the source of the fourth PMOS tube is connected to the power supply, and the drain of the fourth PMOS tube is connected to the drain of the third NMOS tube; 所述的第三NMOS管栅极连接第二NMOS的漏极，所述的第三NMOS管源极连接地，所述的第三NMOS管漏极连接第四PMOS的漏极；The gate of the third NMOS tube is connected to the drain of the second NMOS tube, the source of the third NMOS tube is connected to the ground, and the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube; 所述低电流关断电路包括：The low current shutdown circuit comprises: 第五PMOS管、第六PMOS管、第七PMOS管、第八PMOS管、第四NMOS管以及第六NMOS管；a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube and a sixth NMOS tube; 所述的第五PMOS管栅极连接第六PMOS管的栅极、第七PMOS管的栅极和漏极，所述的第五PMOS管源极连接电源，所述的第五PMOS管漏极连接第六PMOS管的源极；The gate of the fifth PMOS tube is connected to the gate of the sixth PMOS tube, the gate and the drain of the seventh PMOS tube, the source of the fifth PMOS tube is connected to the power supply, and the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube; 所述的第六PMOS管栅极连接第七PMOS管的栅极，所述的第六PMOS管源极连接第五PMOS管的漏极，所述的第六PMOS管漏极连接第七PMOS管的源极；The gate of the sixth PMOS tube is connected to the gate of the seventh PMOS tube, the source of the sixth PMOS tube is connected to the drain of the fifth PMOS tube, and the drain of the sixth PMOS tube is connected to the source of the seventh PMOS tube; 所述的第七PMOS管栅极连接第七PMOS管的漏极，所述的第七PMOS管源极连接第六PMOS管的漏极，所述第七PMOS管的漏极连接第八PMOS管的源极；The gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube, the source of the seventh PMOS tube is connected to the drain of the sixth PMOS tube, and the drain of the seventh PMOS tube is connected to the source of the eighth PMOS tube; 所述第八PMOS管的栅极连接第四PMOS管的漏极，所述第八PMOS管的源极连接第七PMOS管的漏极，所述第八PMOS管的漏极连接第五NMOS管的漏极、第四NMOS管漏极；The gate of the eighth PMOS tube is connected to the drain of the fourth PMOS tube, the source of the eighth PMOS tube is connected to the drain of the seventh PMOS tube, and the drain of the eighth PMOS tube is connected to the drain of the fifth NMOS tube and the drain of the fourth NMOS tube; 所述第四NMOS管的栅极连接第四PMOS管的漏极，所述第四NMOS管的源极连接地，所述第四NMOS管的漏极连接第五NMOS管的漏极；The gate of the fourth NMOS tube is connected to the drain of the fourth PMOS tube, the source of the fourth NMOS tube is connected to the ground, and the drain of the fourth NMOS tube is connected to the drain of the fifth NMOS tube; 所述第六NMOS管的栅极连接第五NMOS管的漏极，所述第六NMOS管的源极连接地，所述第六NMOS管的漏极连接第一PMOS管、第九PMOS管、第十PMOS管、第十五PMOS管和第十六PMOS管的栅极；The gate of the sixth NMOS tube is connected to the drain of the fifth NMOS tube, the source of the sixth NMOS tube is connected to the ground, and the drain of the sixth NMOS tube is connected to the gates of the first PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube, and the sixteenth PMOS tube; 所述ESD保护单元包括：The ESD protection unit comprises: 第五NMOS管，所述第五NMOS管的栅极连接地，所述第五NMOS管的源极连接地，所述第五NMOS管的漏极连接第八PMOS管的漏极。A fifth NMOS tube, wherein a gate of the fifth NMOS tube is connected to the ground, a source of the fifth NMOS tube is connected to the ground, and a drain of the fifth NMOS tube is connected to the drain of the eighth PMOS tube. 2.根据权利要求1所述的带隙基准电路，其特征在于，所述运算跨导放大器包括：2. The bandgap reference circuit according to claim 1, wherein the operational transconductance amplifier comprises: 第九PMOS管、第十PMOS管、第十一PMOS管、第十二PMOS管、第七NMOS管、第八NMOS管、第十三PMOS管、第十四PMOS管、第九NMOS管、第十NMOS管、第十一NMOS管以及第十二NMOS管；a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, and a twelfth NMOS tube; 所述第九PMOS管的栅极连接第十PMOS管的栅极，所述第九PMOS管的源极连接电源，所述第九PMOS管的漏极连接第七NMOS管的漏极；The gate of the ninth PMOS tube is connected to the gate of the tenth PMOS tube, the source of the ninth PMOS tube is connected to the power supply, and the drain of the ninth PMOS tube is connected to the drain of the seventh NMOS tube; 所述第十PMOS管的栅极连接第九PMOS管的栅极，所述第十PMOS管的源极连接电源，所述第十PMOS管的漏极连接第十一PMOS管和第十二PMOS管的源极；The gate of the tenth PMOS tube is connected to the gate of the ninth PMOS tube, the source of the tenth PMOS tube is connected to a power supply, and the drain of the tenth PMOS tube is connected to the sources of the eleventh PMOS tube and the twelfth PMOS tube; 所述第十一PMOS管的栅极连接第三电阻R3的正端，所述第十一PMOS管的源极连接第十PMOS管的漏极，所述第十一PMOS管的漏极连接第十一NMOS管的漏极；The gate of the eleventh PMOS tube is connected to the positive end of the third resistor R3 , the source of the eleventh PMOS tube is connected to the drain of the tenth PMOS tube, and the drain of the eleventh PMOS tube is connected to the drain of the eleventh NMOS tube; 所述第十二PMOS管的栅极连接第一电阻R1的负端，所述第十二PMOS管的源极连接第十PMOS管的漏极，所述第十二PMOS管的漏极连接第十二NMOS的漏极；The gate of the twelfth PMOS tube is connected to the negative end of the first resistor R1 , the source of the twelfth PMOS tube is connected to the drain of the tenth PMOS tube, and the drain of the twelfth PMOS tube is connected to the drain of the twelfth NMOS; 所述第七NMOS管的栅极连接第七NMOS管的漏极，所述第七NMOS管的源极连接第八NMOS管的漏极，所述第七NMOS管的漏极连接第九PMOS管的漏极；The gate of the seventh NMOS tube is connected to the drain of the seventh NMOS tube, the source of the seventh NMOS tube is connected to the drain of the eighth NMOS tube, and the drain of the seventh NMOS tube is connected to the drain of the ninth PMOS tube; 所述第八NMOS管的栅极连接第八NMOS管的漏极，所述第八NMOS管的源极连接地，所述第八NMOS管的漏极连接第七NMOS管的源极；The gate of the eighth NMOS tube is connected to the drain of the eighth NMOS tube, the source of the eighth NMOS tube is connected to the ground, and the drain of the eighth NMOS tube is connected to the source of the seventh NMOS tube; 所述第十三PMOS管的栅极连接第十四PMOS管的栅极和第十三PMOS管的漏极，所述第十三PMOS管的源极连接电源，所述第十三PMOS管的漏极连接第九NMOS管的漏极；The gate of the thirteenth PMOS tube is connected to the gate of the fourteenth PMOS tube and the drain of the thirteenth PMOS tube, the source of the thirteenth PMOS tube is connected to the power supply, and the drain of the thirteenth PMOS tube is connected to the drain of the ninth NMOS tube; 所述第十四PMOS管的栅极连接第十三PMOS管的栅极，所述第十四PMOS管的源极连接电源，所述第十四PMOS管的漏极连接第十NMOS管的漏极；The gate of the fourteenth PMOS tube is connected to the gate of the thirteenth PMOS tube, the source of the fourteenth PMOS tube is connected to the power supply, and the drain of the fourteenth PMOS tube is connected to the drain of the tenth NMOS tube; 所述第九NMOS管的栅极连接第七NMOS管和第十NMOS管的栅极，所述第九NMOS管的源极连接第十一NMOS管的漏极，所述第九NMOS管的漏极连接第十三PMOS的漏极；The gate of the ninth NMOS tube is connected to the gates of the seventh NMOS tube and the tenth NMOS tube, the source of the ninth NMOS tube is connected to the drain of the eleventh NMOS tube, and the drain of the ninth NMOS tube is connected to the drain of the thirteenth PMOS; 所述第十NMOS管的栅极连接第九NMOS管栅极，所述第十NMOS管的源极连接第十二NMOS管漏极，所述第十NMOS管的漏极连接第十四PMOS管的漏极；The gate of the tenth NMOS tube is connected to the gate of the ninth NMOS tube, the source of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, and the drain of the tenth NMOS tube is connected to the drain of the fourteenth PMOS tube; 所述第十一NMOS管的栅极连接第十二NMOS管栅极，所述第十一NMOS管的源极连接地，所述第十一NMOS管的漏极连接第九NMOS的源极；The gate of the eleventh NMOS tube is connected to the gate of the twelfth NMOS tube, the source of the eleventh NMOS tube is connected to the ground, and the drain of the eleventh NMOS tube is connected to the source of the ninth NMOS; 所述第十二NMOS管的栅极连接第十一NMOS管栅极，所述第十二NMOS管的源极连接地，所述第十二NMOS管的漏极连接第十NMOS管源极。The gate of the twelfth NMOS tube is connected to the gate of the eleventh NMOS tube, the source of the twelfth NMOS tube is connected to the ground, and the drain of the twelfth NMOS tube is connected to the source of the tenth NMOS tube. 3.根据权利要求1所述的带隙基准电路，其特征在于，所述基准电压核心电路包括：3. The bandgap reference circuit according to claim 1, wherein the reference voltage core circuit comprises: 第十五PMOS管、第十六PMOS管、第一电阻R1、第二电阻R2、第三电阻R3、第一三极管以及第二三极管；A fifteenth PMOS transistor, a sixteenth PMOS transistor, a first resistor R 1 , a second resistor R 2 , a third resistor R 3 , a first triode and a second triode; 所述第十五PMOS管的栅极连接第十六PMOS管栅极，所述第十五PMOS管的源极连接电源，所述第十五PMOS管的漏极连接第一电阻R1的正端；The gate of the fifteenth PMOS tube is connected to the gate of the sixteenth PMOS tube, the source of the fifteenth PMOS tube is connected to the power supply, and the drain of the fifteenth PMOS tube is connected to the positive end of the first resistor R1 ; 所述第十六PMOS管的栅极连接第十五PMOS管栅极，所述第十六PMOS管的源极连接电源，所述第十六PMOS管的漏极连接第二电阻R2正端；The gate of the sixteenth PMOS tube is connected to the gate of the fifteenth PMOS tube, the source of the sixteenth PMOS tube is connected to the power supply, and the drain of the sixteenth PMOS tube is connected to the positive end of the second resistor R2 ; 所述第一电阻R1正端连接第十五PMOS管漏极，所述第一电阻R1的负端连接第一三极管的集电极；The positive end of the first resistor R1 is connected to the drain of the fifteenth PMOS tube, and the negative end of the first resistor R1 is connected to the collector of the first transistor; 所述第二电阻R2正端连接第十六PMOS管漏极，所述第二电阻R2的负端连接第三电阻R3正端；The positive end of the second resistor R 2 is connected to the drain of the sixteenth PMOS tube, and the negative end of the second resistor R 2 is connected to the positive end of the third resistor R 3 ; 所述第三电阻R3正端连接第二电阻R2负端，所述第三电阻R3的负端连接第二三极管的集电极；The positive end of the third resistor R 3 is connected to the negative end of the second resistor R 2 , and the negative end of the third resistor R 3 is connected to the collector of the second transistor; 所述第一三极管的基极与第二三极管的基极连接，所述第一三极管发射极接地，所述第一三极管集电极连接第一电阻R1负端；The base of the first transistor is connected to the base of the second transistor, the emitter of the first transistor is grounded, and the collector of the first transistor is connected to the negative end of the first resistor R1 ; 所述第二三极管的基极与第一三极管的基极连接，所述第二三极管的发射极接地，所述第二三极管的集电极与第三电阻R3的负端连接。The base of the second transistor is connected to the base of the first transistor, the emitter of the second transistor is grounded, and the collector of the second transistor is connected to the negative end of the third resistor R3 .
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