CN115047930B - Band gap reference circuit - Google Patents

Band gap reference circuit Download PDF

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Publication number
CN115047930B
CN115047930B CN202210580109.1A CN202210580109A CN115047930B CN 115047930 B CN115047930 B CN 115047930B CN 202210580109 A CN202210580109 A CN 202210580109A CN 115047930 B CN115047930 B CN 115047930B
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tube
pmos tube
electrode
drain electrode
pmos
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CN115047930A (en
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孙大鹰
朱凯
王冲
顾文华
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Nanjing University of Science and Technology
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Nanjing University of Science and Technology
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
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  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The application provides a band gap reference circuit, comprising: a bandgap reference start circuit and a reference voltage generation circuit; the band gap reference starting circuit comprises a delay circuit, a low current turn-off circuit and an ESD protection unit; the bandgap reference voltage generating circuit comprises an operational transconductance amplifier and a reference voltage core circuit. The starting circuit can enable the band gap circuit to work normally apart from an unbalanced working point and automatically turn off the starting circuit, so that the static power consumption is reduced; on the other hand, the ESD electrostatic protection unit is designed by the circuit, so that electrostatic damage of the device can be effectively prevented, and the stability and reliability of the circuit operation are ensured.

Description

Band gap reference circuit
Technical Field
The application relates to the technical field of analog integrated circuits, in particular to a band gap reference circuit.
Background
With the rapid development of integration technology, bandgap references are widely used in various integrated circuits such as analog, analog-to-digital hybrid, and power management. The design quality of the band gap reference directly influences the overall performance of the chip, and a band gap reference source is required to provide stable and accurate reference voltage for high-precision comparators, A/D and D/A converters and the like. Therefore, improving the performance of the bandgap reference source is of great importance to improve the reliability and stability of the system operation.
The starting circuit of the band gap reference circuit has the state of avoiding the branch current of the band gap reference circuit from being in a zero state (degenerated point), keeping the output voltage constant to be zero and not working normally. In the prior art, the starting circuit of the bandgap reference circuit is started by current mirror image or output voltage feedback control, and a part of current loss still exists in the starting circuit after the starting is completed.
Meanwhile, when the band gap reference circuit works normally, the risk of damage caused by ESD surge of an external interface cannot be ignored. The damage of the electrostatic discharge to the device is not measurable, the electrostatic discharge is the potential killer with the largest quality of the electronic product, and the device can be seriously damaged and the function is lost, so the ESD protection is a non-negligible loop for improving the working stability and the reliability of the circuit. But however
The bandgap reference circuit is not designed with ESD protection cells.
Disclosure of Invention
The application discloses a band-gap reference circuit which is used for solving the problem of power consumption in the process that the band-gap reference circuit gets rid of a merging point and turns off a starting circuit.
The application provides a band gap reference circuit, which comprises a band gap reference starting circuit and a band gap reference voltage generating circuit;
The band gap reference starting circuit comprises a delay circuit, a low current turn-off circuit and an ESD protection unit;
the band gap reference voltage generation circuit comprises an operational transconductance amplifier and a reference voltage core circuit;
The delay circuit is used for generating time delay through current and starting a circuit turn-off signal;
The low-current turn-off circuit is used for turning off a branch circuit to which a turn-off signal comes;
The ESD protection unit is used for protecting a circuit;
the operational transconductance amplifier is used for playing a clamping function;
the reference voltage core circuit is used for generating a voltage with zero temperature coefficient.
Optionally, the delay circuit includes:
the first PMOS tube, the first NMOS tube, the second PMOS tube, the second NMOS tube, the third PMOS tube, the fourth PMOS tube and the third NMOS tube;
The source electrode of the first PMOS tube is connected with a power supply, and the grid electrode of the first PMOS tube is connected with the grid electrodes of a ninth PMOS tube, a tenth PMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube of the reference voltage generating circuit;
The grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the first NMOS tube is connected with the ground, and the drain electrode of the first NMOS tube is connected with the ground;
the source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrode of the third PMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the third PMOS tube is connected with a power supply, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube;
the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected with the ground, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with a power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube;
The grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS, the source electrode of the third NMOS tube is connected with the ground, and the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS.
Optionally, the low current shutdown circuit includes:
A fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube and a sixth NMOS tube;
The grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the grid electrode of the seventh PMOS tube and the drain electrode of the seventh PMOS tube, the source electrode of the fifth PMOS tube is connected with a power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube;
The grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube;
the grid electrode of the seventh PMOS tube is connected with the drain electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube;
The grid electrode of the eighth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the eighth PMOS tube is connected with the drain electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the drain electrode of the fourth NMOS tube;
The grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the fourth NMOS tube is connected with the ground, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube;
The grid electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is connected with the ground, and the drain electrode of the sixth NMOS tube is connected with the grid electrodes of the first PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube.
Optionally, the ESD protection unit includes:
And the grid electrode of the fifth NMOS tube is connected with the ground, the source electrode of the fifth NMOS tube is connected with the ground, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the eighth PMOS tube.
Optionally, the operational transconductance amplifier includes:
A ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube;
The grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with a power supply, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the seventh NMOS tube;
the grid electrode of the tenth PMOS tube is connected with the grid electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube is connected with a power supply, and the drain electrode of the tenth PMOS tube is connected with the source electrodes of the eleventh PMOS tube and the twelfth PMOS tube;
The grid electrode of the eleventh PMOS tube is connected with the positive end of the third resistor R 3, the source electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube;
The grid electrode of the twelfth PMOS tube is connected with the negative end of the first resistor R 1, the source electrode of the twelfth PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the twelfth NMOS;
The grid electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the ninth PMOS tube;
The grid electrode of the eighth NMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is connected with the ground, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the seventh NMOS tube;
The grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the fourteenth PMOS tube and the drain electrode of the thirteenth PMOS tube, the source electrode of the thirteenth PMOS tube is connected with a power supply, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the ninth NMOS tube;
The grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the thirteenth PMOS tube, the source electrode of the fourteenth PMOS tube is connected with a power supply, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the tenth NMOS tube;
The grid electrode of the ninth NMOS tube is connected with the grid electrodes of the seventh NMOS tube and the tenth NMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the thirteenth PMOS;
the grid electrode of the tenth NMOS tube is connected with the grid electrode of the ninth NMOS tube, the source electrode of the tenth NMOS tube is connected with the drain electrode of the twelfth NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube;
The grid electrode of the eleventh NMOS tube is connected with the grid electrode of the twelfth NMOS tube, the source electrode of the eleventh NMOS tube is connected with the ground, and the drain electrode of the eleventh NMOS tube is connected with the source electrode of the ninth NMOS;
the grid electrode of the twelfth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, the source electrode of the twelfth NMOS tube is connected with the ground, and the drain electrode of the twelfth NMOS tube is connected with the source electrode of the tenth NMOS tube.
Optionally, the reference voltage core circuit includes:
A fifteenth PMOS transistor, a sixteenth PMOS transistor, a first resistor R 1, a second resistor R 2, a third resistor R 3, a first transistor, and a second transistor;
The grid electrode of the fifteenth PMOS tube is connected with the grid electrode of the sixteenth PMOS tube, the source electrode of the fifteenth PMOS tube is connected with a power supply, and the drain electrode of the fifteenth PMOS tube is connected with the positive end of the first resistor R 1;
The grid electrode of the sixteenth PMOS tube is connected with the grid electrode of the fifteenth PMOS tube, the source electrode of the sixteenth PMOS tube is connected with a power supply, and the drain electrode of the sixteenth PMOS tube is connected with the positive end of the second resistor R 2;
The positive end of the first resistor R 1 is connected with the drain electrode of the fifteenth PMOS tube, and the negative end of the first resistor R 1 is connected with the collector electrode of the first triode;
The positive end of the second resistor R 2 is connected with the drain electrode of the sixteenth PMOS tube, and the negative end of the second resistor R 2 is connected with the positive end of the third resistor R 3;
the positive end of the third resistor R 3 is connected with the negative end of the second resistor R 2, and the negative end of the third resistor R 3 is connected with the collector electrode of the second triode;
The base electrode of the first triode is connected with the base electrode of the second triode, the emitting electrode of the first triode is grounded, and the collecting electrode of the first triode is connected with the negative end of the first resistor R 1;
the base of the second triode is connected with the base of the first triode, the emitter of the second triode is grounded, and the collector of the second triode is connected with the negative end of the third resistor R 3.
The band gap reference circuit comprises a band gap reference starting circuit and a band gap reference voltage generating circuit, wherein in the band gap reference starting circuit, if the grid electrode of a first PMOS tube is high level, the band gap reference circuit is at a merging point, the circuit cannot normally work to output voltage, the first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube are all turned off, the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube present resistance characteristics, the grid electrode of the sixth NMOS tube is high level, the drain electrode of the sixth NMOS tube is low level, at the moment, the grid electrode of a ninth PMOS tube, a tenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube and the first PMOS tube is low level, VB is high level, the starting circuit is turned off, the band gap reference circuit breaks away from the normal work of the merging point, the starting circuit is turned off, and the power consumption of the band gap reference circuit is reduced.
When the input power supply voltage suddenly generates a larger electrostatic overshoot, an ESD protection circuit is formed through the fifth, sixth, seventh PMOS tubes and the fifth NMOS tube, and the current is discharged through the reverse diode of the fifth NMOS tube, so that the protection circuit is protected.
Drawings
FIG. 1 is a schematic diagram of a bandgap reference circuit according to an embodiment of the present application;
FIG. 2 is a waveform diagram of an output of a bandgap reference source according to an embodiment of the present application;
Fig. 3 is a current waveform diagram of a start-up circuit of a bandgap reference source according to an embodiment of the present application.
Detailed Description
The application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application.
Fig. 1 is a schematic diagram of a bandgap reference structure provided by the present application, where the present embodiment can enable a circuit to get rid of degeneracy and turn off a start-up circuit, thereby reducing power consumption.
The reference numerals are explained as follows:
1. A starting circuit, 2, an operational transconductance amplifier, 3 and a reference voltage core circuit;
In the band gap reference starting circuit, P 1, a first PMOS tube, P 2, a second PMOS tube, P 3, a third PMOS tube, P 4, a fourth PMOS tube, P 5, a fifth PMOS tube, P 6, a sixth PMOS tube, P 7, a seventh PMOS tube, P 8, an eighth PMOS tube, N 1, a first NMOS tube, N 2, a second NMOS tube, N 3, a third NMOS tube, N 4, a fourth NMOS tube, N 5, a fifth NMOS tube, N 6 and a sixth NMOS tube;
In a transconductance operational amplifier: p 9, a ninth PMOS tube, P 10, a tenth PMOS tube, P 11, an eleventh PMOS tube, P 12, a twelfth PMOS tube, P 13, a thirteenth PMOS tube, P 14, a fourteenth PMOS tube, N 7, a seventh NMOS tube, N 8, an eighth NMOS tube, N 9, a ninth NMOS tube, N 10, a tenth NMOS tube, N 11, an eleventh NMOS tube, N 12, a twelfth NMOS tube;
In the reference voltage core circuit: p 15, fifteenth PMOS tube, P 16, sixteenth PMOS tube, R 1, first resistor, R 2, second resistor, R 3, third resistor, Q 1, first triode, Q 2, second triode.
Referring specifically to fig. 1, the bandgap reference circuit provided in this embodiment specifically includes: a bandgap reference start-up circuit and a bandgap reference voltage generation circuit;
the bandgap reference start-up circuit comprises a delay circuit, a low current turn-off circuit and an ESD protection unit.
The bandgap reference voltage generating circuit comprises an operational transconductance amplifier and a reference voltage core circuit.
The delay circuit charges the MOSCAP by current, generates a time delay, and generates a start circuit off signal through the inverter group.
The low-current turn-off circuit temporarily turns off signals through two MOS switching tubes to turn off branches to which the turn-off signals come.
The ESD protection unit is used for protecting the circuit. Specifically, the GGNMOS can avoid the situation that the device is damaged due to overlarge current when the reference is suddenly electrified or static electricity is released.
The operational transconductance amplifier is used for playing a clamping function, and particularly, a folding cascode structure is adopted to achieve a good clamping function of the circuit, so that the working stability of the band gap reference circuit is ensured.
And the reference voltage core circuit is used for generating a voltage with zero temperature coefficient. Specifically, the zero temperature coefficient voltage is generated by the structure with the same branch current and different diode proportions and a certain proportion of resistors.
The delay circuit includes:
The first PMOS tube, the first NMOS tube, the second PMOS tube, the second NMOS tube, the third PMOS tube, the fourth PMOS tube and the third NMOS tube.
The source electrode of the first PMOS tube is connected with a power supply, and the grid electrode of the first PMOS tube is connected with the grid electrodes of a ninth PMOS tube, a tenth PMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube of the reference voltage generating circuit.
The grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the first NMOS tube is connected with the ground, and the drain electrode of the first NMOS tube is connected with the ground.
The source electrode of the second PMOS tube is connected with the power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube.
The grid electrode of the third PMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the third PMOS tube is connected with a power supply, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube.
The grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected with the ground, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube.
The grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with a power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube.
The grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS, the source electrode of the third NMOS tube is connected with the ground, and the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS.
The low current turn-off circuit includes:
Fifth PMOS pipe, sixth PMOS pipe, seventh PMOS pipe, eighth PMOS pipe, fourth NMOS pipe and sixth NMOS pipe.
The grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the grid electrode and the drain electrode of the seventh PMOS tube, the source electrode of the fifth PMOS tube is connected with a power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube.
The grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube.
The grid electrode of the seventh PMOS tube is connected with the drain electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube.
The grid electrode of the eighth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the eighth PMOS tube is connected with the drain electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the drain electrode of the fourth NMOS tube.
The grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the fourth NMOS tube is connected with the ground, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube.
The grid electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is connected with the ground, and the drain electrode of the sixth NMOS tube is connected with the grid electrodes of the first PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube.
The ESD protection unit includes:
and the grid electrode of the fifth NMOS tube is connected with the ground, the source electrode of the fifth NMOS tube is connected with the ground, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the eighth PMOS tube.
The operational transconductance amplifier includes:
Ninth PMOS pipe, tenth PMOS pipe, eleventh PMOS pipe, twelfth PMOS pipe, seventh NMOS pipe, eighth NMOS pipe, thirteenth PMOS pipe, fourteenth PMOS pipe, ninth NMOS pipe, tenth NMOS pipe, eleventh NMOS pipe and twelfth NMOS pipe.
The grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with a power supply, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the seventh NMOS tube.
The grid electrode of the tenth PMOS tube is connected with the grid electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube is connected with a power supply, and the drain electrode of the tenth PMOS tube is connected with the source electrodes of the eleventh PMOS tube and the twelfth PMOS tube.
The grid electrode of the eleventh PMOS tube is connected with the positive end of the third resistor R 3, the source electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube.
The grid electrode of the twelfth PMOS tube is connected with the negative end of the first resistor R 1, the source electrode of the twelfth PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the twelfth NMOS.
The grid electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the ninth PMOS tube.
The grid electrode of the eighth NMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is connected with the ground, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the seventh NMOS tube.
The grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the fourteenth PMOS tube and the drain electrode of the thirteenth PMOS tube, the source electrode of the thirteenth PMOS tube is connected with a power supply, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the ninth NMOS tube.
The grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the thirteenth PMOS tube, the source electrode of the fourteenth PMOS tube is connected with a power supply, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the tenth NMOS tube.
The grid electrode of the ninth NMOS tube is connected with the grid electrodes of the seventh NMOS tube and the tenth NMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the thirteenth PMOS.
The grid electrode of the tenth NMOS tube is connected with the grid electrode of the ninth NMOS tube, the source electrode of the tenth NMOS tube is connected with the drain electrode of the twelfth NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube.
The grid electrode of the eleventh NMOS tube is connected with the grid electrode of the twelfth NMOS tube, the source electrode of the eleventh NMOS tube is connected with the ground, and the drain electrode of the eleventh NMOS tube is connected with the source electrode of the ninth NMOS.
The grid electrode of the twelfth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, the source electrode of the twelfth NMOS tube is connected with the ground, and the drain electrode of the twelfth NMOS tube is connected with the source electrode of the tenth NMOS tube.
The reference voltage core circuit includes:
The circuit comprises a fifteenth PMOS tube, a sixteenth PMOS tube, a first resistor R 1, a second resistor R 2, a third resistor R 3, a first triode and a second triode.
The grid electrode of the fifteenth PMOS tube is connected with the grid electrode of the sixteenth PMOS tube, the source electrode of the fifteenth PMOS tube is connected with a power supply, and the drain electrode of the fifteenth PMOS tube is connected with the positive end of the first resistor R 1.
The grid electrode of the sixteenth PMOS tube is connected with the grid electrode of the fifteenth PMOS tube, the source electrode of the sixteenth PMOS tube is connected with the power supply, and the drain electrode of the sixteenth PMOS tube is connected with the positive end of the second resistor R 2.
The positive end of the first resistor R 1 is connected with the drain electrode of the fifteenth PMOS tube, and the negative end of the first resistor R 1 is connected with the collector electrode of the first triode.
The positive end of the second resistor R 2 is connected with the drain electrode of the sixteenth PMOS tube, and the negative end of the second resistor R 2 is connected with the positive end of the third resistor R 3.
The positive end of the third resistor R 3 is connected with the negative end of the second resistor R 2, and the negative end of the third resistor R 3 is connected with the collector electrode of the second triode.
The base of the first triode is connected with the base of the second triode, the emitter of the first triode is grounded, and the collector of the first triode is connected with the negative end of the first resistor R 1.
The base of the second triode is connected with the base of the first triode, the emitter of the second triode is grounded, and the collector of the second triode is connected with the negative end of the third resistor R 3.
As shown in fig. 2, the output reference voltage is about 1.22V.
As shown in fig. 3, the current loss of the starting circuit is almost zero, so that the starting circuit is turned off truly, and the power consumption is saved.
Further, the first resistor R 1 has the same resistance as the second resistor R 2, and the third resistor R 3 has a resistance adjustable with the first resistor R 1 and the second resistor R 2, so that the range of the output voltage V BG can be adjusted.
The output voltage V BG of the bandgap reference circuit is:
Wherein Δv BE is the base-emitter voltage of the triode, n is the number proportionality coefficient of the first triode and the second triode, vt=26 mV (300K), R 1 is the resistance value of the first resistor, and R 2 is the resistance value of the second resistor.
As can be seen from the expression of the output voltage V BG, the output voltage is changed by adjusting the size of R 1、R2, or the number of the triodes is adjusted, so that the temperature coefficient is kept unchanged under the condition that the output voltage is adjustable.
The above embodiments are provided to illustrate the technical concept and features of the present invention and are intended to enable those skilled in the art to understand the content of the present invention and implement the same, and are not intended to limit the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
According to the technical scheme, the beneficial effects of the application are as follows:
the band gap reference circuit comprises a band gap reference starting circuit and a band gap reference voltage generating circuit, wherein in the band gap reference starting circuit, if the grid electrode of a first PMOS tube is high level, the band gap reference circuit is at a merging point, the circuit cannot normally work to output voltage, the first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube are all turned off, the fifth PMOS tube, the sixth PMOS tube and the seventh PMOS tube present resistance characteristics, the grid electrode of the sixth NMOS tube is high level, the drain electrode of the sixth NMOS tube is low level, at the moment, the grid electrode of a ninth PMOS tube, a tenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube and the first PMOS tube is low level, VB is high level, the starting circuit is turned off, the band gap reference circuit breaks away from the normal work of the merging point, the starting circuit is turned off, and the power consumption of the band gap reference circuit is reduced.
When the input power supply voltage suddenly generates a larger electrostatic overshoot, an ESD protection circuit is formed through the fifth, sixth, seventh PMOS tubes and the fifth NMOS tube, and the current is discharged through the reverse diode of the fifth NMOS tube, so that the protection circuit is protected.

Claims (3)

1. A bandgap reference circuit, characterized in that the bandgap reference circuit comprises a bandgap reference start-up circuit and a bandgap reference voltage generation circuit;
The band gap reference starting circuit comprises a delay circuit, a low current turn-off circuit and an ESD protection unit;
the band gap reference voltage generation circuit comprises an operational transconductance amplifier and a reference voltage core circuit;
The delay circuit is used for generating time delay through current and starting a circuit turn-off signal;
The low-current turn-off circuit is used for turning off a branch circuit to which a turn-off signal comes;
The ESD protection unit is used for protecting a circuit;
the operational transconductance amplifier is used for playing a clamping function;
The reference voltage core circuit is used for generating voltage with zero temperature coefficient;
The delay circuit includes:
the first PMOS tube, the first NMOS tube, the second PMOS tube, the second NMOS tube, the third PMOS tube, the fourth PMOS tube and the third NMOS tube;
The source electrode of the first PMOS tube is connected with a power supply, and the grid electrode of the first PMOS tube is connected with the grid electrodes of a ninth PMOS tube, a tenth PMOS tube, a fifteenth PMOS tube and a sixteenth PMOS tube of the reference voltage generating circuit;
The grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the first NMOS tube is connected with the ground, and the drain electrode of the first NMOS tube is connected with the ground;
the source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrode of the third PMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the third PMOS tube is connected with a power supply, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube;
the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected with the ground, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with a power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube;
The grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS, the source electrode of the third NMOS tube is connected with the ground, and the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS;
The low current turn-off circuit includes:
A fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube and a sixth NMOS tube;
The grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the grid electrode of the seventh PMOS tube and the drain electrode of the seventh PMOS tube, the source electrode of the fifth PMOS tube is connected with a power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube;
The grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube;
the grid electrode of the seventh PMOS tube is connected with the drain electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube;
The grid electrode of the eighth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the eighth PMOS tube is connected with the drain electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the drain electrode of the fourth NMOS tube;
The grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the fourth NMOS tube is connected with the ground, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube;
The grid electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is connected with the ground, and the drain electrode of the sixth NMOS tube is connected with the grid electrodes of the first PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube;
The ESD protection unit includes:
And the grid electrode of the fifth NMOS tube is connected with the ground, the source electrode of the fifth NMOS tube is connected with the ground, and the drain electrode of the fifth NMOS tube is connected with the drain electrode of the eighth PMOS tube.
2. The bandgap reference circuit according to claim 1, wherein said operational transconductance amplifier comprises:
A ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube;
The grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with a power supply, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the seventh NMOS tube;
the grid electrode of the tenth PMOS tube is connected with the grid electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube is connected with a power supply, and the drain electrode of the tenth PMOS tube is connected with the source electrodes of the eleventh PMOS tube and the twelfth PMOS tube;
The grid electrode of the eleventh PMOS tube is connected with the positive end of the third resistor R 3, the source electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube;
The grid electrode of the twelfth PMOS tube is connected with the negative end of the first resistor R 1, the source electrode of the twelfth PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the twelfth NMOS;
The grid electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the ninth PMOS tube;
The grid electrode of the eighth NMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is connected with the ground, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the seventh NMOS tube;
The grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the fourteenth PMOS tube and the drain electrode of the thirteenth PMOS tube, the source electrode of the thirteenth PMOS tube is connected with a power supply, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the ninth NMOS tube;
The grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the thirteenth PMOS tube, the source electrode of the fourteenth PMOS tube is connected with a power supply, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the tenth NMOS tube;
The grid electrode of the ninth NMOS tube is connected with the grid electrodes of the seventh NMOS tube and the tenth NMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the thirteenth PMOS;
the grid electrode of the tenth NMOS tube is connected with the grid electrode of the ninth NMOS tube, the source electrode of the tenth NMOS tube is connected with the drain electrode of the twelfth NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube;
The grid electrode of the eleventh NMOS tube is connected with the grid electrode of the twelfth NMOS tube, the source electrode of the eleventh NMOS tube is connected with the ground, and the drain electrode of the eleventh NMOS tube is connected with the source electrode of the ninth NMOS;
the grid electrode of the twelfth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, the source electrode of the twelfth NMOS tube is connected with the ground, and the drain electrode of the twelfth NMOS tube is connected with the source electrode of the tenth NMOS tube.
3. The bandgap reference circuit of claim 1, wherein said reference voltage core circuit comprises:
A fifteenth PMOS transistor, a sixteenth PMOS transistor, a first resistor R 1, a second resistor R 2, a third resistor R 3, a first transistor, and a second transistor;
The grid electrode of the fifteenth PMOS tube is connected with the grid electrode of the sixteenth PMOS tube, the source electrode of the fifteenth PMOS tube is connected with a power supply, and the drain electrode of the fifteenth PMOS tube is connected with the positive end of the first resistor R 1;
The grid electrode of the sixteenth PMOS tube is connected with the grid electrode of the fifteenth PMOS tube, the source electrode of the sixteenth PMOS tube is connected with a power supply, and the drain electrode of the sixteenth PMOS tube is connected with the positive end of the second resistor R 2;
The positive end of the first resistor R 1 is connected with the drain electrode of the fifteenth PMOS tube, and the negative end of the first resistor R 1 is connected with the collector electrode of the first triode;
The positive end of the second resistor R 2 is connected with the drain electrode of the sixteenth PMOS tube, and the negative end of the second resistor R 2 is connected with the positive end of the third resistor R 3;
the positive end of the third resistor R 3 is connected with the negative end of the second resistor R 2, and the negative end of the third resistor R 3 is connected with the collector electrode of the second triode;
The base electrode of the first triode is connected with the base electrode of the second triode, the emitting electrode of the first triode is grounded, and the collecting electrode of the first triode is connected with the negative end of the first resistor R 1;
the base of the second triode is connected with the base of the first triode, the emitter of the second triode is grounded, and the collector of the second triode is connected with the negative end of the third resistor R 3.
CN202210580109.1A 2022-05-26 2022-05-26 Band gap reference circuit Active CN115047930B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180640A (en) * 2005-12-27 2007-07-12 Seiko Epson Corp Voltage generation circuit, regulator circuit, and integrated circuit device
CN103001200A (en) * 2012-12-14 2013-03-27 北京大学 Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit
KR20190068952A (en) * 2017-12-11 2019-06-19 단국대학교 산학협력단 Band-Gap Reference Circuit
CN110703841A (en) * 2019-10-29 2020-01-17 湖南国科微电子股份有限公司 Starting circuit of band-gap reference source, band-gap reference source and starting method
CN113985957A (en) * 2021-12-27 2022-01-28 唯捷创芯(天津)电子技术股份有限公司 Overshoot-free quick-start band gap reference circuit, chip and electronic equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180640A (en) * 2005-12-27 2007-07-12 Seiko Epson Corp Voltage generation circuit, regulator circuit, and integrated circuit device
CN103001200A (en) * 2012-12-14 2013-03-27 北京大学 Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit
KR20190068952A (en) * 2017-12-11 2019-06-19 단국대학교 산학협력단 Band-Gap Reference Circuit
CN110703841A (en) * 2019-10-29 2020-01-17 湖南国科微电子股份有限公司 Starting circuit of band-gap reference source, band-gap reference source and starting method
CN113985957A (en) * 2021-12-27 2022-01-28 唯捷创芯(天津)电子技术股份有限公司 Overshoot-free quick-start band gap reference circuit, chip and electronic equipment

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