CN114879798B - Band-gap reference voltage source with offset elimination and nonlinear compensation - Google Patents
Band-gap reference voltage source with offset elimination and nonlinear compensation Download PDFInfo
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- CN114879798B CN114879798B CN202210322209.4A CN202210322209A CN114879798B CN 114879798 B CN114879798 B CN 114879798B CN 202210322209 A CN202210322209 A CN 202210322209A CN 114879798 B CN114879798 B CN 114879798B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
- G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
Abstract
The invention provides a band-gap reference voltage source with offset elimination and nonlinear compensation, which comprises a band-gap reference voltage source, wherein a band-gap reference voltage source circuit is arranged in the band-gap reference voltage source, and comprises a traditional band-gap circuit and an operational amplifier coreThe traditional band gap circuit structure comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, an MN22MOS (metal oxide semiconductor) transistor, a Q1 transistor, a Q2 transistor and a band gap reference voltage source output port V ref The band-gap reference voltage source adopts the traditional band-gap circuit structure to carry out first-order linear compensation on output voltage, utilizes negative temperature coefficient current and a triode to generate a nonlinear compensation item, carries out nonlinear compensation through a four-input operational amplifier with mismatch elimination, realizes high precision and low temperature coefficient, and ensures high power supply rejection ratio of the band-gap reference voltage source in a steady state.
Description
Technical Field
The invention relates to the field of band-gap reference sources, in particular to a band-gap reference voltage source with offset elimination and nonlinear compensation.
Background
The most classical bandgap reference is a voltage reference which is independent of temperature and is about 1.25V, because the difference between the reference voltage and the bandgap voltage of silicon is not much, it is called as bandgap reference, and the bandgap reference voltage source is a very important voltage source in integrated circuits, and is widely used in analog circuits, digital-analog hybrid circuits, a/D converters, etc. Because the precision and the temperature characteristic of the band-gap reference voltage source greatly determine the stability of an integrated circuit system chip, the band-gap reference voltage source is required to have high precision and good temperature characteristic at the same time so as to solve the problem that the first-order temperature compensation temperature coefficient of the traditional band-gap reference voltage source is higher, and therefore the invention provides the band-gap reference voltage source with offset cancellation and nonlinear compensation to solve the problems in the prior art.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a bandgap reference voltage source with offset cancellation and nonlinear compensation, which has the advantages of offset cancellation and nonlinear compensation, and effectively solves the problem of a bandgap reference voltage source with a high first-order temperature compensation temperature coefficient in the prior art.
In order to realize the purpose of the invention, the invention is realized by the following technical scheme: a band-gap reference voltage source with offset elimination and nonlinear compensation comprises a band-gap reference voltage source, wherein a band-gap reference voltage source circuit is arranged in the band-gap reference voltage source and comprises a traditional band-gap circuit, an operational amplifier core circuit, a negative temperature coefficient current generating circuit, a nonlinear compensation generating circuit, a starting circuit and a biasing circuit, and the traditional band-gap circuit structure comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, an MN22MOS (metal oxide semiconductor) transistor, a Q1 transistor, a Q2 transistor and a band-gap reference voltage source output port V ref The negative temperature coefficient current generating circuit comprises an MP19MOS tube, an MN20MOS tube, a folding operational amplifier A3 and a resistor R5, the nonlinear compensation generating circuit comprises an MP21MOS tube and a Q3 transistor, and the operational amplifier core circuit comprises a four-input operational amplifier A1 with offset cancellation and a four-input operational amplifier A2 with error storage.
The further improvement lies in that: the upper end of the resistor R1 is connected with VDD, the lower end of the resistor R1 is connected with the drain electrode of the MN22MOS tube, and the source electrode of the MN22MOS tube is connected with the output port V of the band-gap reference voltage source ref The upper ends of the resistor R2 and the resistor R3 are connected, the lower end of the resistor R2 is connected with the emitting and folding operational amplifier A3 of the transistor Q1, the lower end of the resistor R3 is connected with the upper end of the resistor R4, and the lower end of the resistor R4 is connected with the emitting electrode of the transistor Q2.
The further improvement lies in that: the source electrode of the MP19MOS tube is connected with VDD, the drain electrode of the MP19MOS tube is connected with the drain electrode of the MN20MOS tube, the grid electrode of the MN20MOS tube is connected with the drain electrode of the MP19MOS tube, the source electrode of the MN20MOS tube is connected with the upper end of a resistor R5, the grid electrode of the MN20MOS tube is connected with the output of a folding operational amplifier A3, the lower end of the resistor R5 is connected with GND, and the inverting input end of the folding operational amplifier A3 is connected with the source electrode of the MN20MOS tube.
The further improvement lies in that: the source electrode of the MP21MOS tube is connected with VDD, the drain electrode of the MP21MOS tube is connected with the emitter electrode of the Q3 transistor, the grid electrode of the Q3 transistor is connected with the grid electrode of the MP19MOS tube, and the base electrode and the collector electrode of the Q3 transistor are connected with GND.
The further improvement lies in that: the operational amplifier A1 is provided with two sets of in-phase input ends and two sets of reverse phase input ends, wherein the two sets of in-phase input ends and the two sets of reverse phase input ends are respectively P1, P2, N1 and N2, the in-phase input end P1 and the in-phase input end P2 are both connected with the lower end of a resistor R2, the reverse phase input end N1 is connected with the lower end of a resistor R3, and the reverse phase input end N2 of the operational amplifier A1 is connected with an emitting electrode of a Q3PNP type bipolar transistor.
The further improvement lies in that: the bias circuit comprises an MP1MOS tube, an MP2MOS tube, an MP6MOS tube, an MP8MOS tube, an MP11MOS tube, an MP12MOS tube, an MP15MOS tube, an MP16MOS tube, an MN3MOS tube, an MN4MOS tube, an MN5MOS tube, an MN7MOS tube, an MN9MOS tube, an MN10MOS tube, an MN13MOS tube, an MN14MOS tube, an MN17MOS tube, an MN18MOS tube and a clock control switch S1.
The further improvement lies in that: the starting circuit comprises an MP23MOS tube, an MP24MOS tube, an MP25MOS tube, an MP27MOS tube, an MP28MOS tube, an MP29MOS tube, an MN26MOS tube, an MN30MOS tube, an S2 clock control switch, an S3 clock control switch and an S4 clock control switch.
The further improvement lies in that: the number ratio of the Q1 transistor to the Q2 transistor is 1.
The further improvement lies in that: the gate electrodes of the MN9MOS tube, the MP1MOS tube, the MP6MOS tube, the MN14MOS tube and the MP15MOS tube respectively generate a bias voltage V0, a bias voltage V1, a bias voltage V2, a bias voltage V3 and a bias voltage V4.
The invention has the beneficial effects that: the band-gap reference voltage source with offset elimination and nonlinear compensation performs high-order nonlinear compensation on the basis of first-order compensation of a traditional band-gap circuit, and simultaneously utilizes negative temperature coefficient current and a triode V BE The characteristic generates a nonlinear compensation term, anThe operational amplifier with offset elimination carries out offset elimination of an operational amplifier input tube by controlling the short circuit of an input end, and the band-gap reference voltage source with offset elimination and nonlinear compensation can achieve an ideal effect under the traditional CMOS process without adopting a special process, thereby realizing high precision and low temperature coefficient and ensuring high power supply rejection ratio of the band-gap reference voltage source in a steady state.
Drawings
Fig. 1 is a schematic diagram of the circuit structure of the present invention.
Fig. 2 is a schematic circuit diagram of a four-input operational amplifier A1 with offset cancellation according to the present invention.
Fig. 3 is a schematic circuit diagram of a four-input operational amplifier A2 with error storage according to the present invention.
Fig. 4 is a schematic circuit diagram of a folded operational amplifier A3 according to the present invention.
FIG. 5 is a comparison diagram of the output temperature characteristics of bandgap reference voltage sources before and after detuning elimination according to the present invention.
Detailed Description
In order to further understand the present invention, the following detailed description will be made with reference to the following examples, which are only used for explaining the present invention and are not to be construed as limiting the scope of the present invention.
According to fig. 1 to 5, the present embodiment provides a bandgap reference voltage source with offset cancellation and nonlinear compensation, including a bandgap reference voltage source, a bandgap reference voltage source circuit is disposed in the bandgap reference voltage source, the bandgap reference voltage source circuit includes a conventional bandgap circuit, an operational amplifier core circuit, a negative temperature coefficient current generating circuit, a nonlinear compensation generating circuit, a start circuit, and a bias circuit, the conventional bandgap circuit structure includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, an MN22MOS transistor, a Q1 transistor, a Q2 transistor, and a bandgap reference voltage source output port V ref The negative temperature coefficient current generating circuit comprises an MP19MOS tube, an MN20MOS tube, a folding operational amplifier A3 and a resistor R5, the nonlinear compensation generating circuit comprises an MP21MOS tube and a Q3 transistor, and the operational amplifier core circuit comprises a four-input operational amplifier with offset eliminationA device A1 and a four input operational amplifier A2 with error storage.
In this embodiment, the transistor is a PNP bipolar transistor, and the MOS transistors are divided into a P-type MOS transistor and an N-type MOS transistor.
In the traditional band gap circuit structure, the upper end of a resistor R1 is connected with VDD, the lower end of the resistor R1 is connected with the drain electrode of an MN22MOS tube, and the source electrode of the MN22MOS tube is connected with a band gap reference voltage source output port V ref The upper ends of the resistor R2 and the resistor R3 are connected, the lower end of the resistor R2 is connected with the emitting and folding operational amplifier A3 of the transistor Q1, the lower end of the resistor R3 is connected with the upper end of the resistor R4, and the lower end of the resistor R4 is connected with the emitting electrode of the transistor Q2.
In the negative temperature coefficient current generating circuit structure, the source electrode of an MP19MOS tube is connected with VDD, the drain electrode of the MP19MOS tube is connected with the drain electrode of an MN20MOS tube, the grid electrode of the MN20MOS tube is connected with the drain electrode of the MP19MOS tube, the source electrode of the MN20MOS tube is connected with the upper end of a resistor R5, the grid electrode of the MN20MOS tube is connected with the output of a folding operational amplifier A3, the lower end of the resistor R5 is connected with GND, the inverting input end of the folding operational amplifier A3 is connected with the source electrode of the MN20MOS tube, and negative temperature coefficient current is generated between the source electrode and the drain electrode of the MP19MOS tube.
In the nonlinear compensation generating circuit, the source electrode of an MP21MOS tube is connected with VDD, the drain electrode of the MP21MOS tube is connected with the emitter electrode of a Q3 transistor, the grid electrode of the Q3 transistor is connected with the grid electrode of an MP19MOS tube, the base electrode and the collector electrode of the Q3 transistor are both connected with GND, and a nonlinear compensation term is generated between the emitter electrodes of the Q1 transistor and the Q3 transistor.
The operational amplifier A1 is provided with two groups of in-phase input ends and two groups of reverse-phase input ends, wherein the two groups of in-phase input ends and the two groups of reverse-phase input ends are respectively P1, P2, N1 and N2, the in-phase input end P1 and the in-phase input end P2 are both connected with the lower end of the resistor R2, the reverse-phase input end N1 is connected with the lower end of the resistor R3, and the reverse-phase input end N2 of the operational amplifier A1 is connected with an emitting electrode of the Q3PNP type bipolar transistor.
The bias circuit comprises an MP1MOS tube, an MP2MOS tube, an MP6MOS tube, an MP8MOS tube, an MP11MOS tube, an MP12MOS tube, an MP15MOS tube, an MP16MOS tube, an MN3MOS tube, an MN4MOS tube, an MN5MOS tube, an MN7MOS tube, an MN9MOS tube, an MN10MOS tube, an MN13MOS tube, an MN14MOS tube, an MN17MOS tube, an MN18MOS tube and a clock control switch S1, wherein the MP1MOS tube, the MP2MOS tube, the MP6MOS tube, the MP8MOS tube, the MP11MOS tube, the MP12MOS tube, the MP15MOS tube and the MP16MOS tube are P-type MOS tubes, the MN3MOS tube, the MN4MOS tube, the MN5MOS tube, the MN7MOS tube, the MN9MOS tube, the MN10MOS tube, the MN13MOS tube, the MN14MOS tube, the MN17MOS tube and the MN18MOS tube are N-type MOS tubes, the source electrode of the MP1MOS tube is connected with VDD, the drain electrode of the MP1MOS tube is connected with the source electrode of the MP2MOS tube, the grid electrode of the MP1MOS tube is connected with the drain electrode of the MP2MOS tube, the drain electrode of the MP2MOS tube is connected with the drain electrode of the MN3MOS tube, the source electrode of the MN3MOS tube is connected with the drain electrode of the MN4MOS tube, the source electrode of the MN4MOS tube is connected with GND, the grid electrode of the MN4MOS tube is connected with the grid electrodes of the MN5MOS tube and the MN7MOS tube, the drain electrode of the MN5MOS tube is connected with the lower end of the clock control switch S1 and the grid electrode of the MN5MOS tube, the source electrode of the MP6MOS tube is connected with VDD, the grid electrode of the MP6MOS tube is connected with the drain electrode of the MP6MOS tube, the drain electrode of the MN7MOS tube and the grid electrode of the MP8MOS tube, the source electrode of the MN7MOS tube is connected with GND, the source electrode of the MP8MOS tube is connected with VDD, the drain electrode of the MP8MOS tube is connected with the drain electrode of the MN9MOS tube, the drain electrode of the MN9MOS tube and the grid electrode of the MN9MOS tube, the source electrode of the MN9MOS tube is connected with the drain electrode of the MN10MOS tube, the source electrode of the MN10MOS tube is connected with GND, the source electrode of the MP11MOS tube is connected with VDD, the drain electrode of the MP11MOS tube is connected with the source electrode of the MP12MOS tube, the drain electrode of the MP12MOS tube is connected with the grid electrodes of the MN13MOS tube and the MN14MOS tube and the drain electrode of the MN13MOS tube, the source electrode of the MN13MOS tube is connected with the drain electrode of the MN12MOS tube, the source electrode of the MN14MOS tube is connected with GND, the source electrode of the MP15MOS tube is connected with VDD, the drain electrode of the MP15MOS tube is connected with the source electrode of the MP16MOS tube, the grid electrode of the MP15MOS tube is connected with the drain electrode of the MP16MOS tube, the drain electrode of the MP16MOS tube is connected with the drain electrode of the MN17MOS tube, the source electrode of the MN17MOS tube is connected with the drain electrode of the MN18MOS tube, and the source electrode of the MN18MOS tube is connected with GND.
The starting circuit comprises an MP23MOS tube, an MP24MOS tube, an MP25MOS tube, an MP27MOS tube, an MP28MOS tube, an MP29MOS tube, an MN26MOS tube, an MN30MOS tube, an S2 clock control switch, an S3 clock control switch and an S4 clock control switch, wherein the source electrode of the MP23MOS tube is connected with VDD, the drain electrode of the MP23MOS tube is connected with the source electrode of the MP24MOS tube, the grid electrode of the MP23MOS tube is connected with the grid electrode of the MP27MOS tube, the source electrode of the MP27MOS tube is connected with VDD, the drain electrode of the MP27MOS tube is connected with the source electrode of the MP28MOS tube, the drain electrode of the MP24MOS tube is connected with the drain electrode of the MN26MOS tube, and the grid electrode of the MP24MOS tube is connected with the grid electrode of the MP28MOS tube, the drain electrode of the MP28MOS tube is connected with the source electrode of the MP29MOS tube, the source electrode of the MP25MOS tube is connected with VDD, the drain electrode of the MP25MOS tube is connected with the output end of an operational amplifier A2 and the upper end of an S2 clock control switch, the grid electrode of the MP25MOS tube is connected with the drain electrode of the MP24MOS tube, the lower end of the S2 clock control switch is connected with GND, the upper end of the S3 clock control switch is connected with VDD, the lower end of the S3 clock control switch is connected with the drain electrode of an MOS tube MN26, the source electrode of the MN2MOS tube is connected with GND, the grid electrode of the MN2MOS tube is connected with the drain electrode of an MN26MOS tube and the grid electrode of an MN30MOS tube, the drain electrode of the MP29MOS tube is connected with the drain electrode of an MN30MOS tube, and the grid electrode of the MP29MOS tube is connected with the lower end of a resistor R3; the source of the MN30MOS tube is connected with GND.
The ratio of the number of Q1 transistors to the number of Q2 transistors is 1.
The gate electrodes of the MN9MOS tube, the MP1MOS tube, the MP6MOS tube, the MN14MOS tube and the MP15MOS tube respectively generate a bias voltage V0, a bias voltage V1, a bias voltage V2, a bias voltage V3 and a bias voltage V4.
In this embodiment, the operational amplifier A1 circuit includes a P-type MP31MOS transistor, an MP32MOS transistor, an MP33MOS transistor, an MP34MOS transistor, an MP35MOS transistor, an MP36MOS transistor, an MP37MOS transistor, an MP38MOS transistor, an MP39MOS transistor, an MP40MOS transistor, an MP41MOS transistor, an MP42MOS transistor, an MP43MOS transistor, an MP44MOS transistor, an MP45MOS transistor, an MP46MOS transistor, an MP51MOS transistor, an MP52MOS transistor, an N-type MN47MOS transistor, an MN48MOS transistor, an MN49MOS transistor, an MN50MOS transistor, an MN53MOS transistor, an MN54MOS transistor, an MN55MOS transistor, an MN56MOS transistor, an MN57MOS transistor, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4, a source of the MP31MOS transistor is connected to VDD, a drain of the MP31MOS transistor is connected to a source of the MP32MOS transistor, and a drain of the MP32MOS transistor is connected to sources of the MP33MOS transistor and the MP34MOS transistor; the drain electrode of the MP33MOS tube is connected with the source electrode of the MN47MOS tube; the drain electrode of the MP34MOS tube is connected with the source electrode of the MN48MOS tube, the source electrode of the MP35MOS tube is connected with VDD, the drain electrode of the MP35MOS tube is connected with the source electrode of the MP36MOS tube, the drain electrode of the MP36MOS tube is connected with the source electrodes of the MP37MOS tube and the MP38MOS tube, the drain electrode of the MP37MOS tube is connected with the source electrode of the MN47MOS tube, the drain electrode of the MP38MOS tube is connected with the source electrode of the MN48MOS tube, the source electrode of the MP39MOS tube is connected with VDD, the drain electrode of the MP39MOS tube is connected with the source electrode of the MP40MOS tube, the drain electrode of the MP40MOS tube is connected with the source electrodes of the MP41MOS tube and the MP42MOS tube, the drain electrode of the MP41MOS tube is connected with the left ends of the capacitor C1 and the capacitor C2 and the upper end of the capacitor C3, the drain electrode of the MP42MOS tube is connected with the right ends of the capacitor C1 and the capacitor C2 and the upper end of the capacitor C4, the source electrode of the MP43MOS tube is connected with VDD, the drain electrode of the MP43MOS tube is connected with the source electrode of the MP45MOS tube, the grid electrode of the MP43MOS tube is connected with the grid electrode of the MP44MOS tube, the source electrode of the MP44MOS tube is connected with VDD, the drain electrode of the MP44MOS tube is connected with the source electrode of the MP46MOS tube, the drain electrode of the MP45MOS tube is connected with the drain electrode of the MN47MOS tube, the grid electrode of the MP45MOS tube is connected with the grid electrode of the MP46MIS tube, the drain electrode of the MP46MOS tube is connected with the drain electrode of the MN48MOS tube, the grid electrode of the MN47MOS tube is connected with the grid electrode of the MN48MOS tube, the source electrode of the MN47MOS tube is connected with the drain electrode of the MN49MOS tube, the source electrode of the MN48MOS tube is connected with the drain electrode of the MN50MOS tube, the grid electrode of the MN49MOS tube is connected with the grid electrodes of the MN50MOS tube and the MN53MOS tube, and the source electrode of the MN49MOS tube is connected with GND; the source electrode of the MN50MOS tube is connected with GND, the source electrode of the MP51MOS tube is connected with VDD, the drain electrode of the MP51MOS tube is connected with the source electrode of the MP52MOS tube, the drain electrode of the MP52MOS tube is connected with the drain electrode of the MN53MOS tube, the grid electrode of the MN53MOS tube and the drain electrode of the MN54MOS tube, the source electrode of the MN53MOS tube is connected with GND, the source electrode of the MN54MOS tube is connected with the drain electrode of the MN55MOS tube 5, and the source electrode of the MN55MOS tube is connected with GND; the drain electrodes of the MN56MOS tube and the MN57MOS tube are connected with VDD, and the source electrodes of the MN56MOS tube and the MN57MOS tube are connected with the source electrode of the MN54MOS tube.
In this embodiment, the operational amplifier A2 includes a P-type MP58MOS transistor, an MP59MOS transistor, an MP60MOS transistor, an MP61MOS transistor, an MP62MOS transistor, an MP63MOS transistor, an MP64MOS transistor, an MP65MOS transistor, an MP66MOS transistor, an MP67MOS transistor, an MP68MOS transistor, an MP69MOS transistor, an N-type MN70MOS transistor, an MN71MOS transistor, an MN72MOS transistor, an MN73MOS transistor, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, a source of the MP58MOS transistor is connected to VDD, a drain of the MP58MOS transistor is connected to a source of the MP59MOS transistor, a drain of the MP59MOS transistor is connected to sources of the MP60MOS transistor and the MP61MOS transistor, a drain of the MP60MOS transistor is connected to a source of the MN70MOS transistor, a drain of the MP61MOS transistor is connected to a source of the MN71MOS transistor, a source of the MP62MOS transistor is connected to a drain of the MP62MOS transistor to a source of the MP63MOS transistor, a drain of the MP63MOS transistor is connected to a drain of the MP65, a drain of the MP61MOS transistor is connected to a drain of the MP64, a drain of the MP6MOS transistor, a capacitor C64 of the MP6 is connected to a capacitor C6, and a drain of the capacitor C64 are connected to a left end of the capacitor C5, the gate of the MP65MOS transistor is connected to the capacitor C5, the right end of the capacitor C6 and the upper end of the capacitor C8, the drain of the MP65MOS transistor is connected to the source of the MN71MOS transistor, the lower ends of the capacitor C7 and the capacitor C8 are both connected to GND, the source of the MP66MOS transistor is connected to VDD, the gate of the MP66MOS transistor is connected to the gate of the MP68MOS transistor, the drain of the MP66MOS transistor is connected to the source of the MP67MOS transistor, the gate of the MP67MOS transistor is connected to the gate of the MP69MOS transistor, the drain of the MP67MOS transistor is connected to the drain of the MN70MOS transistor, the source of the MP68MOS transistor is connected to VDD, the drain of the MP68MOS transistor is connected to the source of the MP69MOS transistor, the drain of the MP69MOS transistor is connected to the drain of the MN71MOS transistor, the upper end of the capacitor C9 is connected to the drain of the MP69MOS transistor, the lower end of the capacitor C9 is connected to the gate of the MN70MOS transistor is connected to the gate of the MN71MOS transistor and the drain of the MN72, the drain of the MN72 is connected to the source of the MN72, and the drain of the MN73 is connected to the drain of the MN71MOS transistor, the MN transistor is connected to the drain of the MN 72.
In this embodiment, the folding operational amplifier A3 includes P-type MP74MOS transistors, MP75, MP76, MP77, MP78, MP79, MP80, MP81, N-type MN82MOS transistors, MN83, MN84, MN85 and a capacitor C10, the source of the MP74MOS transistor is connected to VDD, the drain of the MP74MOS transistor is connected to the source of the MP75MOS transistor, the drain of the MP75MOS transistor is connected to the sources of the MP76MOS transistor and the MP77MOS transistor, the drain of the MP76MOS transistor is connected to the source of the MN82MOS transistor, the drain of the MP77MOS transistor is connected to the source of the MN83MOS transistor, the source of the MP78MOS transistor is connected to VDD, the gate of the 78MOS transistor is connected to the gate of the MP80MOS transistor, the drain of the MP78MOS transistor is connected to the source of the MP79MOS transistor, the gate of the MP79MOS tube is connected with the gate of the MP81MOS tube, the drain of the MP79MOS tube is connected with the left end of the capacitor C10 and the drain of the MN82MOS tube, the source of the MP80MOS tube is connected with VDD, the drain of the MP80MOS tube is connected with the source of the MP81MOS tube, the drain of the MP81MOS tube is connected with the right end of the capacitor C10 and the drain of the MN83MOS tube, the gate of the MN82MOS tube is connected with the gate of the MN83MOS tube, the source of the MN82MOS tube is connected with the drain of the MN84MOS tube, the source of the MN83MOS tube is connected with the drain of the MN85MOS tube, the gate of the MN84MOS tube is connected with the drain of the MN82MOS tube and the gate of the MN85MOS tube, the source of the MN84MOS tube is connected with GND, and the source of the MN85MOS tube is connected with GND.
As shown in FIG. 1, a negative temperature coefficient current generation circuit and a nonlinear compensation generation circuit are added to perform high-order nonlinear compensation, and a folded operational amplifier A3 locks the voltage at the upper end of a resistor R5 to be V BE1 The current flowing through the resistor R5 is:
the current flowing through the resistor R5 is a negative temperature coefficient current, and the negative temperature coefficient current of the resistor R5 is copied to the Q3 bipolar transistor branch through a current mirror consisting of MP19 and MP21, and at the moment:
v flowing through Q1 and Q3 BE The difference between the voltages is expressed as:
and the nonlinear compensation term is introduced into the traditional band gap circuit to compensate the high-order nonlinear term, and the high-order nonlinear term is as follows:
in the subsequent layout and tape-out process, inevitable process errors exist, so that the input end of the operational amplifier may generate certain mismatch and offset voltage exists, and the bandgap reference output is affected, and therefore, it is necessary to add an operational amplifier offset cancellation technique, as shown in fig. 2 and 3, the four-input operational amplifier A1 adds an offset cancellation technique, and the four-input operational amplifier A2 adds an error storage technique.
Wherein, the first stage of the circuit start-up: the clock control switch S1 is closed, S2, S3 and S4 are opened, proper bias voltage is built in a bias circuit, the operational amplifier starts to work, and the circuit is started in a second stage: the gates of the MP41 and MP42 are shorted, so that the mismatch errors of the MP41 and MP42 are stored in C5, C6, C7, and C8 of the four-input operational amplifier A2, and the third stage of the circuit start-up: the gates of MP33 and MP34 are shorted, the gates of MP37 and MP38 are shorted, the mismatch errors of the two input ports MP33, MP34, MP37, MP38 of the four-input operational amplifier A1 are stored in C1, C2, C3, C4, the fourth stage of the circuit start-up: and the input end of the operational amplifier A1 is short-circuited and disconnected, the operational amplifier A is connected into a normal circuit, the error voltage stored in the C1-C8 is added into a feedback loop, and the band-gap reference voltage source starts to work normally.
As shown in FIG. 5, the input offset voltage of the operational amplifier is set to 6mV, and the simulation result shows that when the operational amplifier is not offset-eliminated, the bandgap output voltage is shown as ". Smallcircle" in the figure, the output reference voltage is 1.231V, and the temperature coefficient is 3.18 × 10 within the range of-40 deg.C to 80 deg.C -6 /° c; when the offset of the operational amplifier is eliminated, the band gap output voltage is shown as a tangle-solidup in the figure, the output reference voltage is 1.219V, and the temperature coefficient is 1.50 multiplied by 10 < -6 >/DEG C within the range of minus 40 ℃ to 80 ℃, so that the offset elimination of the operational amplifier with mismatching input ends can well improve the temperature characteristic of the band gap reference voltage source.
The foregoing illustrates and describes the principles, general features, and advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (2)
1. A bandgap reference voltage source with offset cancellation and non-linear compensation, comprising: the band-gap reference circuit comprises a band-gap reference voltage source, wherein a band-gap reference voltage source circuit is arranged in the band-gap reference voltage source, the band-gap reference voltage source circuit comprises a traditional band-gap circuit, an operational amplifier core circuit, a negative temperature coefficient current generating circuit, a nonlinear compensation generating circuit, a starting circuit and a biasing circuit, the traditional band-gap circuit structure comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, an MN22MOS (metal oxide semiconductor) transistor, a Q1 transistor, a Q2 transistor and a band-gap reference voltage source output port Vref, the negative temperature coefficient current generating circuit comprises an MP19MOS transistor, an MN20MOS transistor, a folding operational amplifier A3 and a resistor R5, the nonlinear compensation generating circuit comprises an MP21MOS transistor and a Q3 transistor, and the operational amplifier core circuit comprises a four-input operational amplifier A1 with offset elimination and a four-input operational amplifier A2 with error storage;
first phase of circuit start-up: the clock control switch S1 is closed, S2, S3 and S4 are opened, proper bias voltage is established in a bias circuit, the four-input operational amplifier A1, the four-input operational amplifier A2 and the folding operational amplifier A3 start to work, and the second stage of circuit starting is as follows: the gates of the MP41 and MP42 are shorted, so that the mismatch errors of the MP41 and MP42 are stored in C5, C6, C7, and C8 of the four-input operational amplifier A2, and the third stage of the circuit start-up is as follows: the gates of MP33 and MP34 are shorted, the gates of MP37 and MP38 are shorted, the mismatch errors of the two input ports MP33, MP34, MP37, MP38 of the four-input operational amplifier A1 are stored in C1, C2, C3, C4, the fourth stage of circuit start-up: the input end of the four-input operational amplifier A1 is in short circuit disconnection and is connected to a normal circuit, the error voltages stored in C1-C8 are added to a feedback loop, and a band-gap reference voltage source starts to work normally;
the source electrode of the MP19MOS tube is connected with VDD, the drain electrode of the MP19MOS tube is connected with the drain electrode of the MN20MOS tube, the source electrode of the MN20MOS tube is connected with the upper end of a resistor R5, the grid electrode of the MN20MOS tube is connected with the output of a folding operational amplifier A3, the lower end of the resistor R5 is connected with GND, and the inverting input end of the folding operational amplifier A3 is connected with the source electrode of the MN20MOS tube;
the source electrode of the MP21MOS tube is connected with VDD, the drain electrode of the MP21MOS tube is connected with the emitter electrode of the Q3 transistor, the base electrode and the collector electrode of the Q3 transistor are both connected with GND, and the grid electrode of the MP19MOS tube is connected with the drain electrode and the grid electrode of the MP21MOS tube;
the four-input operational amplifier A1 is provided with two groups of in-phase input ends and two groups of reverse-phase input ends, wherein the two groups of in-phase input ends are P1, P2, N1 and N2 respectively, the in-phase input end P1 and the in-phase input end P2 are both connected with the lower end of a resistor R2, the reverse-phase input end N1 is connected with the lower end of a resistor R3, and the reverse-phase input end N2 of the four-input operational amplifier A1 is connected with an emitting electrode of a Q3 transistor;
the upper end of the resistor R1 is connected with VDD, the lower end of the resistor R1 is connected with the drain electrode of an MN22MOS tube, the source electrode of the MN22MOS tube is connected with the output port Vref of a band-gap reference voltage source, the upper ends of the resistor R2 and the resistor R3, the lower end of the resistor R2 is connected with the emitter electrode of the Q1 transistor and the folding operational amplifier A3, the lower end of the resistor R3 is connected with the upper end of the resistor R4, and the lower end of the resistor R4 is connected with the emitter electrode of the Q2 transistor; the grid electrode of the MN22MOS tube is connected with the output end of the four-input operational amplifier A2, the emitter electrode of the Q1 transistor is connected with the non-inverting input end of the folding operational amplifier A3, the base electrode and the collector electrode of the Q1 transistor are connected with GND, and the base electrode and the collector electrode of the Q2 transistor are connected with GND;
the bias circuit comprises an MP1MOS tube, an MP2MOS tube, an MP6MOS tube, an MP8MOS tube, an MP11MOS tube, an MP12MOS tube, an MP15MOS tube, an MP16MOS tube, an MN3MOS tube, an MN4MOS tube, an MN5MOS tube, an MN7MOS tube, an MN9MOS tube, an MN10MOS tube, an MN13MOS tube, an MN14MOS tube, an MN17MOS tube, an MN18MOS tube and a clock control switch S1;
wherein, the MP1MOS tube, the MP2MOS tube, the MP6MOS tube, the MP8MOS tube, the MP11MOS tube, the MP12MOS tube, the MP15MOS tube, the MP16MOS tube are P-type MOS tubes, the MN3MOS tube, the MN4MOS tube, the MN5MOS tube, the MN7MOS tube, the MN9MOS tube, the MN10MOS tube, the MN13MOS tube, the MN14MOS tube, the MN17MOS tube, the MN18MOS tube are N-type MOS tubes, the source of the MP1MOS tube is connected with VDD, the drain of the MP1MOS tube is connected with the source of the MP2MOS tube, the gate of the MP1MOS tube is connected with the drain of the MP2MOS tube, the drain of the MP2MOS tube is connected with the drain of the MN3MOS tube, the gate of the MP2MOS tube is connected with a bias voltage V2, the gate of the MN4MOS tube is connected with the source of the MN5MOS tube, the drain of the MN3MOS tube is connected with the drain of the MN4MOS tube, the drain of the MP 4MOS tube is connected with the drain of the MN5MOS tube, the drain of the MP6MOS tube is connected with the drain of the MN 6MOS tube, the drain of the MP6MOS tube is connected with the drain of the MN 6MOS tube, the drain of the MP6MOS tube and the drain of the MP6MOS tube, the source electrode of the MP8MOS tube is connected with VDD, the drain electrode of the MP8MOS tube is connected with the drain electrode of the MN9MOS tube, the drain electrode of the MN9MOS tube and the gate electrode of the MN10MOS tube, the source electrode of the MN10MOS tube is connected with GND, the source electrode of the MP11MOS tube is connected with VDD, the drain electrode of the MP11MOS tube is connected with the source electrode of the MP12MOS tube, the gate electrode of the MP11MOS tube is connected with a bias voltage V1, the drain electrode of the MP12MOS tube is connected with the gate electrode of the MN14MOS tube and the drain electrode of the MN13MOS tube, the gate electrode of the MP12MOS tube is connected with a bias voltage V2, the source electrode of the MN13MOS tube is connected with the drain electrode of the MN14MOS tube, the source electrode of the MP15MOS tube is connected with VDD, the drain electrode of the MP15MOS tube is connected with the source electrode of the MP16MOS tube, the gate electrode of the MP15MOS tube is connected with the drain electrode of the MP16MOS tube, the drain electrode of the MP16MOS tube is connected with the drain electrode of the MN17, the drain electrode of the MN17MOS tube is connected with the bias voltage V17, and the drain electrode of the MN17 is connected with the bias voltage V2, the bias voltage V17, the drain electrode of the MOS tube is connected with the drain electrode of the MN14MOS tube, the drain electrode of the MOS tube is connected with the drain electrode of the MOS tube, the drain electrode of the MN14MOS tube is connected with the MN14MOS tube, the source electrode of the MN18MOS tube is connected with GND, and the grid electrode of the MN18MOS tube is connected with a bias voltage V3;
the starting circuit comprises an MP23MOS tube, an MP24MOS tube, an MP25MOS tube, an MP27MOS tube, an MP28MOS tube, an MP29MOS tube, an MN26MOS tube, an MN30MOS tube, an S2 clock control switch, an S3 clock control switch and an S4 clock control switch;
wherein, the source electrode of the MP23MOS tube is connected with VDD, the drain electrode of the MP23MOS tube is connected with the source electrode of the MP24MOS tube, the grid electrode of the MP23MOS tube is connected with the grid electrode of the MP27MOS tube, the source electrode of the MP27MOS tube is connected with VDD, the drain electrode of the MP27MOS tube is connected with the source electrode of the MP28MOS tube, the drain electrode of the MP24MOS tube is connected with the drain electrode of the MN26MOS tube, the grid electrode of the MP24MOS tube is connected with the grid electrode of the MOS tube MP28, the drain electrode of the MP28MOS tube is connected with the source electrode of the MP29MOS tube, the source electrode of the MP25MOS tube is connected with VDD, the drain electrode of the MP25MOS tube is connected with the output end of the four-input operational amplifier A2 and the upper end of the S2 clock control switch, the grid electrode of the MP25MOS tube is connected with the drain electrode of the MP24MOS tube, the lower end of the S2 clock control switch is connected with GND, the upper end of the S3 clock control switch is connected with VDD, the lower end of the S3 clock control switch is connected with the drain electrode of the MOS tube MN26MOS tube, the source electrode of the MN26MOS tube is connected with GND, the grid electrode of the MN26MOS tube is connected with the drain electrode of the MN26MOS tube and the grid electrode of the MN30MOS tube, the drain electrode of the MP29MOS tube is connected with the drain electrode of the MN30MOS tube, and the grid electrode of the MP29MOS tube is connected with the lower end of the resistor R3; the source electrode of MN30MOS pipe is connected with GND, clock control switch S4 is connected with bias voltage V2, the upper end of clock control switch S4 links to each other with VDD, the lower extreme of clock control switch S4 is connected with the grid of MP24MOS pipe and the grid of MP28MOS pipe respectively, the grid of MP23MOS pipe, the grid of MP27MOS pipe are connected with bias voltage V1, the grid of MN9MOS pipe, MP1MOS pipe, MP6MOS pipe, MN14MOS pipe and MP15MOS pipe produces bias voltage V0, bias voltage V1, bias voltage V2, bias voltage V3 and bias voltage V4 respectively.
2. A bandgap reference voltage source with offset cancellation and non-linearity compensation according to claim 1, wherein: the number ratio of the Q1 transistor to the Q2 transistor is 1.
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| CN104111683B (en) * | 2014-06-27 | 2016-04-20 | 成都嘉纳海威科技有限责任公司 | A kind of reference source with automatically eliminating amplifier imbalance function |
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