CN111026226B

CN111026226B - Voltage regulator

Info

Publication number: CN111026226B
Application number: CN201911263814.3A
Authority: CN
Inventors: 赵冬; 王钊
Original assignee: Nanjing ZGmicro Co Ltd
Current assignee: Nanjing ZGmicro Co Ltd
Priority date: 2019-12-11
Filing date: 2019-12-11
Publication date: 2021-06-11
Anticipated expiration: 2039-12-11
Also published as: CN111026226A

Abstract

The invention provides a voltage regulator, which adopts a reference voltage source for automatically eliminating input offset voltage. The reference voltage source includes: inputting an offset voltage elimination circuit, a band-gap reference source sub-circuit and a switch clock circuit; the input offset voltage elimination circuit is used for eliminating input offset voltage existing between the homodromous input end and the reverse input end of the operational amplifier and controlling the output end VBG voltage of the band-gap reference source sub-circuit; the switch clock circuit is used for providing a clock signal for the input offset voltage elimination circuit, so that the input offset voltage elimination circuit alternately operates in a first working mode and a second working mode. So that the input offset voltage elimination circuit eliminates the input offset voltage and keeps the VBG voltage at the output end of the band-gap reference source sub-circuit in a normal working state. And further the accuracy of the output voltage of the voltage regulator is improved.

Description

Voltage regulator

Technical Field

The invention relates to the technical field of electronic circuits, in particular to an improved voltage regulator.

Background

The reference voltage source is an important component of analog and mixed signal integrated circuits, and is widely applied to the design of circuits such as a power management chip, a voltage stabilizer and the like. The reference voltage source is used for providing a reference voltage or a reference current for the whole circuit, and the performance of the reference voltage source directly influences the performance of the whole circuit. With the development of integrated circuits, the complexity of design becomes higher and higher, and higher requirements are put forward on the anti-interference capability of a reference voltage source.

For example, fig. 1 shows a schematic circuit diagram of a conventional Complementary Metal Oxide Semiconductor (cmos) bandgap reference voltage source. As seen in fig. 1, the circuit includes two bipolar transistors Q1 and Q2, a resistor R1, a resistor R2, a resistor R3, and an Operational Amplifier (OP). Wherein, R1 and R2 have the same resistance, and the emitter area of the bipolar transistor Q1 is N times of the emitter area of the bipolar transistor Q2. It can be seen that there are mismatch effects, such as threshold mismatch, aspect mismatch, etc. of the input tube, due to the input of the operational amplifier op. Will have a relatively large influence on the dc characteristics of the operational amplifier op. It is mainly shown that there is an input offset voltage across the input of the operational amplifier op. As in fig. 1, an input offset voltage V is present across the input of the operational amplifier op_OS. It can also be seen from fig. 1 that the inverting input of the operational amplifier op is coupled to the point a between R1 and R3, and the inverting input of the operational amplifier op is coupled to R2 and to a bipolar transistor Q2At point B, the output of the operational amplifier op is coupled to the output port V_OUT。

The voltages at the two inputs of the operational amplifier op are the same, i.e. V, due to the clamping effect of the operational amplifier op_B＝V_A-V_OS. From the Hall-based voltage law, it can be known that the voltage drop at R3 is V_R3＝V_BE2-V_BE1+V_OS＝ΔV_BE+V_OS. Wherein, V_BE1And V_BE2The base-emitter voltages of bipolar transistors Q1 and Q2, respectively. The voltage drop across R1 is also known,

namely, it is

;

And an output port voltage drop of

. Obviously when assuming the input offset voltage V_OSAt zero time, the output voltage

. It can be seen that when the offset voltage V is input_OSWhen it is not zero, the output voltage will be increased

The excessive part is the output offset voltage V_OS(OUT)。

Due to V_OSBecause of the temperature characteristic, the output offset voltage has a large influence on not only the output voltage of the CMOS bandgap reference voltage source circuit, but also the temperature coefficient of the CMOS bandgap reference voltage source circuit. Therefore, the voltage regulator using the bandgap reference voltage source may not accurately form the voltage value due to the deviation of the generated bandgap reference voltage VGB.

Disclosure of Invention

The invention aims to provide a voltage regulator, which adopts an improved band-gap reference voltage source voltage, and the band-gap reference voltage source voltage can further improve the precision of the output reference voltage, thereby improving the precision of the output voltage of the voltage regulator.

In order to solve the above problems, the present invention provides a voltage regulator including: a reference voltage source providing a bandgap reference voltage; the first connection end of the power transistor is coupled with a power supply end, and the second connection end of the power transistor is used as the output end of the voltage regulator; the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series between the output end of the voltage regulator and the ground end; and an error amplifier having a first input terminal receiving the bandgap reference voltage, a second input terminal connected to an intermediate node of the first and second voltage dividing resistors, and an output terminal coupled to a gate of the power transistor, wherein the reference voltage source comprises: inputting an offset voltage elimination circuit, a band-gap reference source sub-circuit and a switch clock circuit; the input offset voltage cancellation circuit includes: the circuit comprises an operational amplifier, a first switch group, a second switch group, a first capacitor C1 and a second capacitor C2; wherein, operational amplifier includes: a main operational amplifier and an auxiliary operational amplifier, wherein the output of the main operational amplifier and the output of the auxiliary operational amplifier are superposed to be used as the output of the operational amplifier; the first input terminal of the main operational amplifier is coupled to the first terminal of the second switch set, the second input terminal of the main operational amplifier is coupled to the third terminal of the second switch set, the second terminal of the second switch set is coupled to the first clamp point of the bandgap reference source sub-circuit, the second input terminal of the main operational amplifier is further coupled to the second clamp point of the bandgap reference source sub-circuit, the first input terminal of the auxiliary operational amplifier is coupled to one terminal of the second capacitor C2, the other terminal of the second capacitor C2 is grounded, the first input terminal of the auxiliary operational amplifier is further coupled to the control terminal of the driving transistor in the bandgap reference source sub-circuit, the first input terminal of the auxiliary operational amplifier is further coupled to the second terminal of the first switch set, the second input terminal of the auxiliary operational amplifier is coupled to one terminal of the first capacitor C1, the other end of the first capacitor C1 is grounded, the second input end of the auxiliary operational amplifier is further coupled to the third end of the first switch set, and the output end of the operational amplifier is coupled to the first end of the first switch set; the switch clock circuit is used for providing a clock signal for the input offset voltage elimination circuit so as to control the coupling mode of the first switch group and the second switch group, so that the input offset voltage elimination circuit alternately operates in a first working mode and a second working mode; when the input offset voltage cancellation circuit operates in the first working mode, a first end of the first switch set is coupled to a second end of the first switch set, and a first end of the second switch set is coupled to a second end of the second switch set; when the input offset voltage cancellation circuit operates in the second working mode, the first terminal of the first switch set is coupled to the third terminal of the first switch set, and the first terminal of the second switch set is coupled to the third terminal of the second switch set.

Compared with the prior art, the reference voltage source eliminates the voltage difference between the two input ends of the main operational amplifier through the feedback regulation of the operational amplifier, so that the voltage between the two input ends of the main operational amplifier is not influenced by the input offset voltage Vos to change. Meanwhile, the accuracy of the output of the whole CMOS band-gap reference voltage source is improved, and the output reference voltage is not influenced by the input offset voltage. Because the accuracy of the output of the CMOS band-gap reference voltage source is improved, the trimming circuits (trimming pads) of the chip can be effectively reduced, and the die size (die size) of the whole chip is reduced, thereby finally reducing the production cost. Meanwhile, the temperature drift coefficient of the CMOS band-gap reference voltage source can be reduced, and the performance and the anti-interference capability of the CMOS band-gap reference voltage source are improved.

Drawings

FIG. 1 is a schematic circuit diagram of a conventional COMS bandgap reference voltage source;

fig. 2 is a schematic diagram of a reference voltage source circuit for eliminating an input offset voltage according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an operational amplifier according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another reference voltage source circuit for eliminating input offset voltage according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a reference voltage source circuit for eliminating an input offset voltage according to another embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating a variation of a VBG voltage at an output terminal according to an embodiment of the present invention;

fig. 7 is a flowchart of a method for eliminating an input offset voltage according to an embodiment of the present invention;

fig. 8 is a circuit diagram of a voltage regulator according to an embodiment of the present invention.

Detailed Description

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Fig. 2 is a schematic diagram of a reference voltage source circuit for eliminating an input offset voltage according to an embodiment of the present invention.

In one embodiment, as shown in fig. 2, the present invention provides a reference voltage source for eliminating the input offset voltage. The circuit schematic diagram of which is shown in fig. 2, the reference voltage source may include: the input offset voltage elimination circuit, the band gap reference source sub-circuit and the switch clock circuit. Although in some instances a start-up circuit may also be included.

In one example, an input offset voltage cancellation circuit includes: the circuit comprises an operational amplifier, a first switch group, a second switch group, a first capacitor C1 and a second capacitor C2. In another example, the operational amplifier may be as shown in fig. 3, and fig. 3 is a schematic diagram of an operational amplifier according to an embodiment of the present invention. The operational amplifier includes a Main operational amplifier Main OP and an auxiliary operational amplifier Aux OP. The output of the main operational amplifier and the output of the auxiliary operational amplifier are superposed to be used as the output VOUT _ OP of the operational amplifier. In one example, the superimposing may be a vector superimposing.

It should be noted by those skilled in the art that in the embodiment shown in fig. 2, the first switch group and the second switch group may be single-pole double-throw switches, or may be a switch group composed of two or more switches. For example, a first switch group including a first switch and a second switch, and a second switch group including a third switch and a fourth switch may be used. In yet another example, the first switch, the second switch, the third switch and the fourth switch may also be NMOS transistors or PMOS transistors. For example, as shown in fig. 4, all of the transistors may be NMOS transistors, or as shown in fig. 5, all of the transistors may be PMOS transistors. Of course, it is obvious to those skilled in the art that the first switch, the second switch, the third switch and the fourth switch may be different MOS transistors. It will be obvious that any equivalent electronic components may be substituted, and the invention is not limited thereto.

As shown in fig. 2, the first input terminal of the main operational amplifier is coupled to the first terminal of the second switch set, the second input terminal of the main operational amplifier is coupled to the third terminal of the second switch set, the second terminal of the second switch set is coupled to the first clamp point C of the bandgap reference source sub-circuit, the second input terminal of the main operational amplifier is further coupled to the second clamp point a of the bandgap reference source sub-circuit, the first input terminal of the auxiliary operational amplifier is coupled to one terminal of a second capacitor C2, the other terminal of the second capacitor C2 is grounded, the first input terminal of the auxiliary operational amplifier is further coupled to the control terminal of the driving transistor in the bandgap reference source sub-circuit, the first input terminal of the auxiliary operational amplifier is further coupled to the second terminal of the first switch set, the second input terminal of the auxiliary operational amplifier is coupled to one terminal of a first capacitor C1, the other terminal of the first capacitor C1 is grounded, the second input terminal of the auxiliary operational amplifier is further coupled to the third terminal of the first switch, the output end of the operational amplifier is coupled to the first end of the first switch set.

The first switch set and the second switch set shown in fig. 2 can select the operation mode of the input offset voltage cancellation circuit according to the clock signal sent by the switch clock circuit. It can be understood that the corresponding relationship between the clock signal and the operation mode can be specifically set according to actual situations. In one example, the input offset voltage cancellation circuit may be alternately operated in the first operation mode and the second operation mode according to a clock signal provided by the input offset voltage cancellation circuit.

For example, when the input offset voltage cancellation circuit operates in the first operation mode, the first terminal of the first switch set is coupled to the second terminal of the first switch set, and the first terminal of the second switch set is coupled to the second terminal of the second switch set. The voltage of the first clamping point and the voltage of the second clamping point are increased until the voltage of the first clamping point is equal to the voltage of the second clamping point.

For another example, when the input offset voltage cancellation circuit operates in the second operation mode, the first terminal of the first switch set is coupled to the third terminal of the first switch set, and the first terminal of the second switch set is coupled to the third terminal of the second switch set. And performing feedback adjustment through the operational amplifier until the difference between the first input end and the second input end of the auxiliary operational amplifier is the same as the difference between the first input end and the second input end of the main operational amplifier.

In one example, if the first switch group is composed of a first switch and a second switch, and the second switch group is composed of a third switch and a fourth switch. When the first signal S1 is at the first level and the second signal S2 is at the second level, the first switch is turned off, the second switch is turned on, the third switch is turned off, and the fourth switch is turned on; and when the first signal S1 is at the second level and the second signal S2 is at the first level, the first switch is turned on, the second switch is turned off, the third switch is turned on, and the fourth switch is turned off.

As shown in fig. 2, the bandgap reference source sub-circuit includes: the driving transistor, a first resistor R1, a second resistor R2, a third resistor R3, a first bipolar transistor Q1, a second bipolar transistor Q2 and an output port VBG. The control end of the driving tube is coupled to the second end of the first switch group in the input offset voltage elimination circuit, the first end of the driving tube is coupled to a power supply VDD, and the second end of the driving tube is coupled to an output port VBG.

Of course, in some embodiments, the driving transistor may also be an NMOS transistor or a PMOS transistor. It can be understood that the driving terminals are gates regardless of whether the driving transistors are NMOS transistors or PMOS transistors. When the driving tube is an NMOS tube, the first end of the driving tube is a drain electrode, and the second end of the driving tube is a source electrode; when the driving transistor is a PMOS transistor, the first end is a source electrode and the second end is a drain electrode.

It should be noted by those skilled in the art that an input offset voltage V is present at the non-inverting input VINP of the main operational amplifier of fig. 2_OSHowever, it is understood that an input offset voltage is not really added here, but is schematically shown in the figure to represent the input offset voltage actually existing in the operational amplifier due to the manufacturing process of the hardware circuit and the like.

In one example, the first input terminals of the main and auxiliary operational amplifiers may be non-inverting input terminals and the second input terminals may be inverting input terminals. In other examples, the first input terminals of the main operational amplifier and the auxiliary operational amplifier may be inverting input terminals, and the second input terminals may be non-inverting input terminals.

The present solution can be described with reference to a more detailed example, such as that shown in fig. 4, which selects two NMOS transistors as the first switch group, i.e., the switch transistor MN1 and the switch transistor MN2, and selects two NMOS transistors as the second switch group, i.e., the switch transistor MN3 and the switch transistor MN 4. Meanwhile, the bandgap reference source sub-circuit driving transistor MN5 is an NMOS transistor, and the first bipolar transistor Q1 and the second bipolar transistor Q2 are PNP bipolar transistors. And the first input terminals of the main operational amplifier and the auxiliary operational amplifier may be non-inverting input terminals, and the second input terminals may be inverting input terminals.

This will be described in more detail below in connection with the circuit diagram shown in fig. 4.

In one example, a bandgap reference source sub-circuit may include: the driving transistor MN5, the first resistor R1, the second resistor R2, the third resistor R3, the first bipolar transistor Q1, the second bipolar transistor Q2 and the output port VBG.

The output end of the operational amplifier is coupled to the drain of the first switch tube MN1 and the source of the second switch tube MN 2. The gate of the first switch MN1 receives the second signal S2 of the switch clock circuit, and the source of the first switch MN1 is coupled to the inverting input terminal AUX _ N of the auxiliary operational amplifier. The inverting input terminal AUX _ N of the auxiliary operational amplifier is further coupled to one terminal of the first capacitor C1, and the other terminal of the first capacitor C1 is grounded. The gate of the second switch MN2 receives the first signal S1 of the switching clock circuit, and the drain of the second switch MN2 is coupled to the non-inverting input AUX _ P of the auxiliary operational amplifier. The non-inverting input terminal AUX _ P of the auxiliary operational amplifier is further coupled to one terminal of a second capacitor C2, and the other terminal of the second capacitor C2 is grounded. The non-inverting input terminal VINP of the main operational amplifier is coupled to the source of the third switch tube MN3 and the drain of the fourth switch tube MN 4. The gate of the third switch MN3 receives the second signal S2 of the switching clock circuit, the drain of the third switch MN3 is coupled to the inverting input VINN of the main operational amplifier, and the inverting input VINN of the main operational amplifier is further coupled to the second clamping point D between the first resistor R1 and the third resistor R3. The gate of the fourth switch MN4 receives the first signal S1 of the switching clock circuit, and the source of the fourth switch MN4 is coupled to the first clamp point C between the emitter of the second bipolar transistor Q2 and the second resistor R2.

The gate of the driving transistor MN5 is coupled to the output terminal VOUT _ OP of the operational amplifier, the drain of the driving transistor MN5 is coupled to the power supply VDD, and the source of the driving transistor MN5 is coupled to the output port VBG. The output port VBG is further coupled to one end of a first resistor R1, and the other end of the first resistor R1 is coupled to one end of a third resistor R3, wherein the second clamp point D is located between the first resistor R1 and the third resistor R3. The other end of the third resistor R3 is coupled to the emitter of the first bipolar transistor Q1, and the base of the first bipolar transistor Q1 and the collector of the first bipolar transistor Q1 are both grounded. The output port VBG is further coupled to one end of a second resistor R2, and the other end of the second resistor R2 is coupled to the emitter of the second bipolar transistor Q2, wherein the first clamp point C is located between the second resistor R2 and the emitter of the second bipolar transistor Q2, and the base of the second bipolar transistor Q2 and the collector of the first bipolar transistor Q1 are both grounded.

In one example, the detection port of the start-up circuit is coupled to the output port VBG, and the output port of the start-up circuit is coupled to the second resistor R2 and the second bipolar transistor Q2E point between the emitters. It is understood that points E and C are understood to be the same point, and the voltages at the two points are also identical, i.e., V_E＝V_C。

In one example, the switching clock circuit generates two disjoint clock signals, namely a first signal S1 and a second signal S2. In another example, the clock signal generated by the switching clock circuit may cause the input offset voltage cancellation circuit to operate in a first operation mode or a second operation mode, and the first operation mode and the second operation mode alternate. The first operation mode is a first level of the first signal S1 and a second level of the second signal S2, and the second operation mode is a second level of the first signal S1 and a first level of the second signal S2. In another example, the first level may be a high level and the second level may be a low level. Of course, it should be noted by those skilled in the art that if the corresponding first switch, second switch, third switch and fourth switch are replaced by other equivalent electronic elements, the corresponding first level may also be replaced by a low level, and the second level may also be replaced by a high level, and the application is not limited herein.

In another example, if different types of MOS transistors are used for the first switch, the second switch, the third switch, and the fourth switch, respectively, a clock signal may be provided for each switch of the switch clock circuit, so as to implement the same function as that in fig. 4.

In one embodiment, the start-up circuit is used to detect the voltage of the output port VBG. When the operating voltage of the VBG after the steady state is zero or cannot enter a normal operating state, the start circuit provides a start signal. As can be seen from fig. 4, the start signal is transmitted as an output of the start circuit to the point E between the resistor R2 and the emitter of the second bipolar transistor Q2. For example, when the start-up circuit detects that the voltage at the output port VBG is zero, which means that the voltage at the input terminals of the main operational amplifier is also zero, in order to make the operational amplifier operate normally, a start-up signal is output to point E to activate the operational amplifier and make it operate normally. The starting signal provided by the starting circuit can make the band-gap reference sub-circuit work in a normal working state.

In one embodiment, when the first signal S1 is at a high level and the second signal S2 is at a low level, the first switch tube MN1 is turned off, the second switch tube MN2 is turned on, the third switch tube MN3 is turned off, and the second switch tube MN4 is turned on. At this time, the output VOUT _ OP of the operational amplifier is transmitted to the non-inverting input AUX _ P of the auxiliary operational amplifier through the second switch MN 2. The inverting input VINP of the main operational amplifier is coupled to the point C, and the inverting input VINN of the main operational amplifier is coupled to the point D. Since the driving tube MN5 is not conducting at this time, there is no voltage at point D and point C. Due to the characteristics of the operational amplifier, the voltage at the non-inverting input VINP of the main operational amplifier is equal to the voltage at the inverting input VINN of the main operational amplifier, i.e., VINP equals VINN. Because the input offset voltage exists at the two input ends of the operational amplifier, the output VOUT _ OP still exists in the operational amplifier and is transmitted to the non-inverting input end AUX _ P of the auxiliary operational amplifier through the second switch tube MN 2. The voltage at the noninverting input terminal AUX _ P of the auxiliary operational amplifier will be greater than the voltage at the inverting input terminal AUX _ N of the auxiliary operational amplifier. Therefore, the output VOUT _ OP of the operational amplifier will be amplified continuously within the clock signal. In other words, when there is no voltage at point D and point C, the voltage at the non-inverting input VINP of the main operational amplifier and the voltage at the inverting input VINN of the main operational amplifier are not equal to each other due to the presence of the start-up circuit and the input of a start-up signal at point C (point E). Therefore, the output VOUT _ OP of the operational amplifier is further amplified within the clock signal. When the VOUT _ OP voltage reaches the threshold voltage of the driving transistor MN5, the driving transistor MN5 will be turned on. Then VBG will also have a voltage present at D, C, and this will result in the voltage at the non-inverting input VINP of the main op-amp no longer being equal to the voltage at the inverting input VINN of the main op-amp. At this time, the operational amplifier still continuously amplifies, i.e. VOUT _ OP continuously increases, and therefore VBG continuously increases, and at this time, the voltages at the D point and the C point also continuously increase. However, due to the principle of series-parallel negative feedback, the voltage at point D increases more rapidly than the voltage at point C. That is, VINN increases voltage more rapidly than VINPThe speed of voltage increase. It should be noted, however, that at this time VINN<VINP+V_OS。

In one embodiment, when the first signal S1 is at a low level and the second signal S2 is at a high level, the first switch tube MN1 is turned on, the second switch tube MN2 is turned off, the third switch tube MN3 is turned on, and the second switch tube MN4 is turned off. At this time, the output of the operational amplifier is transmitted to the inverting input terminal AUX _ N of the auxiliary operational amplifier through the first switch MN 1. The non-inverting input VINP of the main operational amplifier is coupled to the inverting input VINN of the main operational amplifier. At the instant when the first switch MN1 is turned on, since AUX _ N is much smaller than AUX _ P, the output VOUT _ OP will transmit the output to the inverting input AUX _ N of the auxiliary operational amplifier, which causes the voltage of AUX _ N to increase to the voltage value of VOUT _ OP instantaneously. At this time, the voltage difference between the two input terminals of the auxiliary operational amplifier will be significantly reduced, and the output VOUT _ OP will be reduced accordingly. Through multiple feedback regulation of operational amplifier, V is obtained_{AUX_N}<V_{AUX_P}And the voltage difference between the two input ends of the auxiliary operational amplifier also differs by the voltage value of the input offset voltage, i.e. V_OS. When the sum of the inputs of the two non-inverting inputs of the operational amplifier is equal to the sum of the inputs of the two inverting inputs of the operational amplifier, i.e. VINN + V_{AUX_N}＝VINP+V_{AUX_P}. At this time, the output VOUT _ OP of the operational amplifier will remain unchanged.

After the clock period of the multi-time switching clock circuit, when the first signal S1 is at high level and the second signal S2 is at low level, the voltage at the point D is adjusted to be different from the voltage at the point C by an input offset voltage V_OSI.e. V_D＝V_C+V_OS. Then, when the first signal S1 is at low level and the second signal S2 is at high level, the voltage difference between the two input ends of the auxiliary operational amplifier is adjusted to eliminate the input offset voltage V existing at the input end of the main operational amplifier_OS. The output VOUT _ OP of the operational amplifier is made to remain stable so that VBG also remains stable. In one example, the regulated voltage of VBG may be 1.2V.

The invention eliminates the input two-end circuit of the main operational amplifier through the feedback regulation of the operational amplifierDifferential voltage is generated so that the voltage across the input terminals of the main operational amplifier is no longer subject to the input offset voltage V_OSI.e. the input offset voltage is eliminated.

Fig. 5 is a schematic diagram of a reference voltage source circuit for eliminating an input offset voltage according to another embodiment of the present invention.

It is understood that in the circuit diagram shown in fig. 5, the first switch, the second switch, the third switch and the fourth switch of the input offset voltage cancellation circuit may be PMOS transistors. And the band-gap reference source sub-circuit driving tube is a PMOS tube, and the first bipolar transistor Q1 and the second bipolar transistor Q2 are NPN bipolar transistors. And the first input terminals of the main operational amplifier and the auxiliary operational amplifier may be non-inverting input terminals, and the second input terminals may be inverting input terminals.

It should be noted by those skilled in the art that when the first switch, the second switch, the third switch and the fourth switch are PMOS transistors, the coupling method is similar to that of fig. 4, in which the port coupled to the source of the NMOS transistor is coupled to the drain of the PMOS transistor instead, and the port coupled to the drain of the NMOS transistor is coupled to the source of the PMOS transistor instead in fig. 4. The corresponding grid is kept unchanged in coupling relation, and the clock signal of the switch clock circuit is also unchanged. Meanwhile, the driving transistor in the bandgap reference source sub-circuit may also be replaced by a PMOS transistor, obviously, compared with fig. 4, in fig. 4, the port coupled to the source of the NMOS transistor is coupled to the drain of the PMOS transistor, the port coupled to the drain of the NMOS transistor is coupled to the source of the PMOS transistor, and the coupling relationship between the corresponding gates remains unchanged. The first bipolar transistor Q1 and the second bipolar transistor Q2 in the bandgap reference source sub-circuit can be replaced by NPN bipolar transistors. It will be appreciated that in contrast to fig. 4, in fig. 4 the ports coupled to the emitter of the PNP bipolar transistor are instead coupled to the base and collector of the NPN bipolar transistor, and the ports coupled to the collector and base of the PNP bipolar transistor are instead coupled to the emitter of the NPN bipolar transistor.

Those skilled in the art will understand that, for the circuit shown in fig. 5, compared with fig. 4, only the type of MOS transistor and the type of bipolar transistor are replaced correspondingly, and the coupling relationship is also replaced adaptively, but the principle of the circuit is the same as that of the circuit shown in fig. 4, and is not repeated here for convenience of description.

It should be noted by those skilled in the art that the present application only shows two different types of combinations of the first switch, the second switch, the third switch, the fourth switch, the driving transistor, the first bipolar transistor and the second bipolar transistor through fig. 4 and fig. 5, and those skilled in the art can also select any other types of combinations, and the present application is not limited herein.

Fig. 6 is a schematic diagram illustrating a variation of the VBG voltage at the output terminal according to an embodiment of the present invention.

Fig. 6 shows a voltage variation diagram of the output terminal VBG of the circuit shown in fig. 5 according to the present invention. As can be seen, the ordinate indicates the value of the output voltage of the output terminal VBG, and the abscissa indicates the clock period. It can be seen that the output voltage of the output terminal VBG becomes gradually larger with time when the first signal S1 is at a high level and the second signal S2 is at a low level. When the switching clock circuit switches the clock signal to the first signal S1 being at low level and the second signal S2 being at high level, the auxiliary operational amplifier stabilizes the output voltage of the output VBG approximately constant over time, i.e., the VBG voltage remains stable when S1 is at low level and S2 is at high level. After a plurality of clock cycles, the output voltage of the output terminal VBG is finally increased to a voltage value of a stable operation state at the high level of S1 and the low level of S2. Then the output voltage of the output terminal VBG is kept stable by the low level of S1 and the high level of S2.

Fig. 7 is a flowchart of a method for eliminating an input offset voltage according to an embodiment of the present invention.

As shown in fig. 7, there is provided a method of eliminating an input offset voltage, which is applied to the circuits shown in fig. 2 to 6, the method including the steps of:

s701, the input offset voltage elimination circuit receives a first signal S1 and a second signal S2 sent by the switch clock circuit.

And S702, when the first signal S1 is at a first level and the second signal S2 is at a second level, the input offset voltage cancellation circuit outputs an amplified output voltage according to the voltage difference of the input ends, feeds the amplified output voltage back to the first input end of the auxiliary operational amplifier in the input offset voltage cancellation circuit for continuous amplification, and feeds back and reduces the voltage difference of the two input ends of the main operational amplifier in the input offset voltage cancellation circuit through the driving tube of the band-gap reference source sub-circuit so as to cancel the input offset voltage existing between the two input ends of the main operational amplifier. That is, according to the negative feedback principle of the operational amplifier, the effect of increasing the output voltage of the operational amplifier is fed back to the input terminal, thereby reducing VINN and VINP + V_OSThe difference between them.

S703, when the first signal S1 is at the second level and the second signal S2 is at the first level, the output voltage is fed back to the second input terminal of the auxiliary operational amplifier in the input offset voltage cancellation circuit, and the voltage difference between the two input terminals of the auxiliary operational amplifier is reduced until the voltage difference between the two input terminals of the auxiliary operational amplifier is equal to the voltage difference between the two input terminals of the main operational amplifier, so as to cancel the input offset voltage existing between the two input terminals of the main operational amplifier and stabilize the output voltage.

In one embodiment, the first signal S1 and the second signal S2 sent by the switching clock circuit alternate in first level with the first signal S1 and the second signal S2.

The invention eliminates the voltage difference between the two input ends of the main operational amplifier through the feedback regulation of the operational amplifier, thereby realizing that the voltage between the two input ends of the main operational amplifier is not influenced by the input offset voltage V any more_OSI.e. the input offset voltage is eliminated. Meanwhile, on one hand, the accuracy of the output of the whole CMOS band-gap reference voltage source is improved, and the output reference voltage is not influenced by the input offset voltage. In addition, because the accuracy of the output of the CMOS band-gap reference voltage source is improved, trimming pad of the chip can be effectively reduced, and d of the whole chip is reducedie size, thereby ultimately reducing production costs. On the other hand, the temperature drift coefficient of the CMOS band-gap reference voltage source can be reduced, and the performance and the anti-interference capability of the CMOS band-gap reference voltage source are improved.

Fig. 8 is a circuit diagram of a voltage regulator in accordance with an embodiment of the present invention. As shown in fig. 8, the voltage regulator 800 includes: a reference voltage source 810, a first dividing resistor R11, a second dividing voltage R12, a power transistor MPA, and an error amplifier EA. The reference voltage source 810 provides a bandgap reference voltage, which may be the improved reference voltage source described above. The first connection terminal of the power transistor MPA is coupled to a power supply terminal VDD, and the second connection terminal thereof is used as an output terminal VO of the voltage regulator. The first voltage dividing resistor R11 and the second voltage dividing resistor R12 are connected in series between the output terminal of the voltage regulator and the ground terminal. The error amplifier EA has a first input terminal receiving the bandgap reference voltage, a second input terminal connected to an intermediate node of the first and second voltage dividing resistors, and an output terminal coupled to a gate of the power transistor. The power transistor is a PMOS transistor, and the first connecting end and the second connecting end of the power transistor are respectively a source electrode and a drain electrode of the PMOS transistor. In this way, the voltage regulator can provide a more accurate output voltage.

In the present invention, the terms "connect", "couple", "connection", "connecting", and the like mean electrically coupling, and mean directly or indirectly electrically connecting unless otherwise specified.

It should be noted that those skilled in the art can make modifications to the embodiments of the present invention without departing from the scope of the appended claims. Accordingly, the scope of the appended claims is not to be limited to the specific embodiments described above.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A voltage regulator, comprising:

a reference voltage source providing a bandgap reference voltage;

the first connection end of the power transistor is coupled with a power supply end, and the second connection end of the power transistor is used as the output end of the voltage regulator;

the first voltage-dividing resistor and the second voltage-dividing resistor are connected in series between the output end of the voltage regulator and the ground end; and

an error amplifier having a first input terminal receiving the bandgap reference voltage, a second input terminal connected to an intermediate node of the first and second voltage dividing resistors, and an output terminal coupled to a gate of the power transistor,

wherein the reference voltage source comprises: inputting an offset voltage elimination circuit, a band-gap reference source sub-circuit and a switch clock circuit;

the input offset voltage cancellation circuit includes: the circuit comprises an operational amplifier, a first switch group, a second switch group, a first capacitor C1 and a second capacitor C2; wherein, operational amplifier includes: a main operational amplifier and an auxiliary operational amplifier, wherein the output of the main operational amplifier and the output of the auxiliary operational amplifier are superposed to be used as the output of the operational amplifier;

the first input terminal of the main operational amplifier is coupled to the first terminal of the second switch set, the second input terminal of the main operational amplifier is coupled to the third terminal of the second switch set, the second terminal of the second switch set is coupled to the first clamp point of the bandgap reference source sub-circuit, the second input terminal of the main operational amplifier is further coupled to the second clamp point of the bandgap reference source sub-circuit, the first input terminal of the auxiliary operational amplifier is coupled to one terminal of the second capacitor C2, the other terminal of the second capacitor C2 is grounded, the first input terminal of the auxiliary operational amplifier is further coupled to the control terminal of the driving transistor in the bandgap reference source sub-circuit, the first input terminal of the auxiliary operational amplifier is further coupled to the second terminal of the first switch set, the second input terminal of the auxiliary operational amplifier is coupled to one terminal of the first capacitor C1, the other end of the first capacitor C1 is grounded, the second input end of the auxiliary operational amplifier is further coupled to the third end of the first switch set, and the output end of the operational amplifier is coupled to the first end of the first switch set;

the switch clock circuit is used for providing a clock signal for the input offset voltage elimination circuit so as to control the coupling mode of the first switch group and the second switch group, so that the input offset voltage elimination circuit alternately operates in a first working mode and a second working mode;

when the input offset voltage cancellation circuit operates in the first working mode, a first end of the first switch set is coupled to a second end of the first switch set, and a first end of the second switch set is coupled to a second end of the second switch set;

when the input offset voltage cancellation circuit operates in the second working mode, the first terminal of the first switch set is coupled to the third terminal of the first switch set, and the first terminal of the second switch set is coupled to the third terminal of the second switch set.

2. The voltage regulator of claim 1, wherein the bandgap reference source subcircuit comprises: the driving transistor, the first resistor R1, the second resistor R2, the third resistor R3, the first bipolar transistor Q1, the second bipolar transistor Q2 and the output port VBG;

when the first bipolar transistor Q1 and the second bipolar transistor Q2 are PNP bipolar transistors, the control terminal of the driving transistor is coupled to the second terminal of the first switch group in the input offset voltage cancellation circuit, the first terminal of the driving transistor is coupled to the power source VDD, the second terminal of the driving transistor is coupled to the output port VBG, the output port VBG is further coupled to one terminal of the first resistor R1, and the other terminal of the first resistor R1 is coupled to one terminal of the third resistor R3, wherein the second clamping point is located between the first resistor R1 and the third resistor R3, the other terminal of the third resistor R3 is coupled to the emitter of the first bipolar transistor Q1, the base of the first bipolar transistor Q1 and the collector of the first bipolar transistor Q1 are both grounded, and the output port VBG is further coupled to one terminal of the second resistor R2, the other end of the second resistor R2 is coupled to the emitter of the second bipolar transistor Q2, wherein the first clamping point is located between the second resistor R2 and the emitter of the second bipolar transistor Q2, and the base of the second bipolar transistor Q2 and the collector of the first bipolar transistor Q1 are both grounded; or

When the first bipolar transistor Q1 and the second bipolar transistor Q2 are NPN bipolar transistors, the control terminal of the driving transistor is coupled to the second terminal of the first switch group in the input offset voltage cancellation circuit, the first terminal of the driving transistor is coupled to the power source VDD, the second terminal of the driving transistor is coupled to the output port VBG, the output port VBG is further coupled to one terminal of the first resistor R1, the other terminal of the first resistor R1 is coupled to one terminal of the third resistor R3, wherein the second clamping point is located between the first resistor R1 and the third resistor R3, the other terminal of the third resistor R3 is coupled to the base and collector of the first bipolar transistor Q1, the emitter of the first bipolar transistor Q1 is grounded, the VBG is further coupled to one terminal of the second output port resistor R2, and the other terminal of the second resistor R2 is coupled to the base and collector of the second bipolar transistor Q2, wherein the first clamping point is located between the second resistor R2 and the base and collector of the second bipolar transistor Q2, and the emitter of the second bipolar transistor Q2 is grounded.

3. The voltage regulator of claim 2, wherein the driving transistor is an NMOS transistor or a PMOS transistor.

4. The voltage regulator of claim 1, wherein the reference voltage source further comprises a startup circuit;

the starting circuit is used for providing a starting signal for a first clamping point of the band-gap reference source sub-circuit when the voltage of a VBG (voltage source) at the output end of the band-gap reference source sub-circuit is zero or in an abnormal working state.

5. The voltage regulator of claim 1, wherein the clock signal comprises a first signal S1 and a second signal S2;

when the first signal S1 is at a first level and the second signal S2 is at a second level, the input offset voltage cancellation circuit operates in the first operating mode, an output of the operational amplifier is transmitted to the first input terminal of the auxiliary operational amplifier and the control terminal of the driving transistor through the first switch set, and the first input terminal of the main operational amplifier is coupled to the first clamping point through the second switch set;

when the first signal S1 is at the second level and the second signal S2 is at the first level, the input offset voltage cancellation circuit operates in the second operation mode, the output of the operational amplifier is transmitted to the second input terminal of the auxiliary operational amplifier through the first switch set, and the first input terminal of the main operational amplifier is coupled to the second input terminal through the second switch set.

6. The voltage regulator of claim 5, wherein when the first signal S1 is at a first level and the second signal S2 is at a second level, the operational amplifier amplifies the first signal until the output of the operational amplifier reaches a threshold voltage of the control terminal of the driving transistor, the driving transistor is turned on, and the output of the operational amplifier continues to be amplified by the operational amplifier, such that the first clamping point voltage and the second clamping point voltage also increase until the first clamping point voltage is equal to the second clamping point voltage;

when the first signal S1 is at the second level and the second signal S2 is at the first level, the signals are fed back and adjusted by the operational amplifier until the difference between the first input end and the second input end of the auxiliary operational amplifier is the same as the difference between the first input end and the second input end of the main operational amplifier.

7. The voltage regulator of any of claims 5-6, wherein the first switch set comprises a first switch and a second switch; the second switch group comprises a third switch and a fourth switch;

when the first signal S1 is at a first level and the second signal S2 is at a second level, the first switch is turned off, the second switch is turned on, the third switch is turned off, and the fourth switch is turned on;

when the first signal S1 is at the second level and the second signal S2 is at the first level, the first switch is turned on, the second switch is turned off, the third switch is turned on, and the fourth switch is turned off.

8. The voltage regulator of claim 7, wherein the first switch, the second switch, the third switch, and the fourth switch are NMOS transistors or PMOS transistors.