CN116931637B - Current source degenerate point transition control circuit, chip, current source and electronic equipment - Google Patents
Current source degenerate point transition control circuit, chip, current source and electronic equipment Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention discloses a current source degenerate point transition control circuit, a chip, a current source and electronic equipment, wherein a first current mirror branch circuit and a second current mirror branch circuit are connected in a mirror image mode to form a current mirror so as to receive a power supply; the low potential end of the first current mirror branch and the low potential end of the second current mirror branch are grounded; the input end of the current transition module is connected to the power supply input end of the first current mirror branch, the output end of the current transition module is connected to the connection point of the P-type transistor and the N-type transistor in the first current mirror branch, and the control end of the current transition module is connected to the power supply; when the power input end of the first current mirror branch receives power, current flows between the input end and the output end of the current transition module; when the control voltage exceeds a threshold, the current transition module disconnects the input and output of the current transition module. On the one hand, the dependence on the resistance is smaller; on the other hand, the current source chip can also be made compact and cost-effective.
Description
Technical Field
The invention relates to the technical field of current source circuits, in particular to a current source degenerate point transition control circuit, a chip, a current source and electronic equipment.
Background
The low power consumption current source is generally applied in a low power consumption chip and is used for supplying power to the whole chip and the subsequent circuit. The required circuit also needs to meet the property that the power consumption is kept low in a wider variation range of the power supply voltage, and the output current does not change along with the variation of the power supply voltage.
The low-power consumption current source generally has two degeneracy points of working states, specifically, the current source transits from a stable state of a current zero point to a stable state of stable output of a power supply, and in order to realize the stable transition of the working state of the current source, a starting circuit is generally required to be added to provide a starting bias, please refer to fig. 1, fig. 1 is a schematic diagram of a current source circuit in the prior art, and the circuit provides an N-type current source to the outside through a transistor M1 and a transistor M2; the current mirror formed by the transistor M3 and the transistor M4 realizes the external P-type current source. The current source provides a starting bias through the transistor M5, so that the current source gets rid of degeneracy point in starting, and the current source transits from a stable state of a current zero point to a stable state of stable output of a power supply, specifically, the transistor M5 is turned on when the power supply VDD is powered on, gates of the transistors M3 and M4 and gates of the transistors M1 and M2 are communicated, thereby providing a bias voltage for a current mirror, and the output of the current source is not influenced by the transistor M5 which is turned off after the output of the current mirror is stable. Because the power supply has a larger variation range (1V-5.5V) under the application of low power consumption, the power supply has different power supply voltagesVoltage va=vdd-VGS of node a at supply voltage M4 Voltage vb=vgs of node b M1 The larger the supply voltage; the larger the difference between Va and Vb, the larger the mirror image offset of the current mirror will be, so the current accuracy of the circuit will change more with the change of the power supply voltage.
Since the transistor M5 is turned off with low power consumption, the following relationship needs to be satisfied:
I M6 *R 2 >VDD-VGS M4 -VGS M5
wherein I is M6 VGS is the current flowing through transistor M6 M4 、VGS M5 The gate-source voltages of transistors M4, M5, respectively, thus, it can be seen that when the VDD voltage is large, a large resistor R2, e.g., I, is required to achieve low power consumption M6 Is 10na, vdd=5.5V VGS M4 ＝VGS M5 =1v, where the resistance of R2 needs to be around 350M, this results in a large cost.
Therefore, how to realize a stable transition from a stable state of a current zero point to a stable state of a power supply stable output by a low-power-consumption current source at a degenerate point, and reduce the cost are technical problems to be solved urgently.
Disclosure of Invention
Based on the above-mentioned current situation, a main object of the present invention is to provide a current source degenerate point transition control circuit, a chip, a current source and an electronic device, so that a low-power consumption current source can smoothly transition from a stable state of a current zero point to a stable state of a power supply stable output at a degenerate point, and the cost is reduced.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
according to a first aspect, an embodiment of the present invention discloses a current source degeneracy point transition control circuit, including: a first current mirror leg and a second current mirror leg,
the first current mirror branch is connected with the second current mirror branch in a mirror image mode to form a current mirror so as to receive a power supply;
the low potential end of the first current mirror branch and the low potential end of the second current mirror branch are grounded;
the input end of the current transition module is connected to the power supply input end of the first current mirror branch, the output end of the current transition module is connected to the connection point of the P-type transistor and the N-type transistor in the first current mirror branch, and the control end of the current transition module is connected to the power supply; the input end and the output end of the current transition module are communicated when the control voltage of the control end of the current transition module is smaller than a threshold value, and are disconnected when the control voltage is larger than the threshold value; the current transition module is realized by an active device;
when the power input end of the first current mirror branch receives power, current flows between the input end and the output end of the current transition module so as to provide bias current for the first current mirror branch; when the control voltage exceeds a threshold value, the current transition module disconnects the input end and the output end of the current transition module so that the first current mirror branch and the second current mirror branch work in a state of outputting a stable power supply.
In a second aspect, an embodiment of the present invention discloses a current source for providing an operating power supply for a post-stage circuit, the current source comprising:
the current source degeneracy point transition control circuit disclosed in the first aspect above.
In a third aspect, embodiments of the present invention disclose a current source chip on which the current source degeneracy point transition control circuit disclosed in the first aspect above, or the current source disclosed in the second aspect above, is integrated.
In a fourth aspect, an embodiment of the present invention discloses an electronic device having a current source, including the current source degeneracy point transition control circuit disclosed in the first aspect, or the current source disclosed in the second aspect.
According to the current source degeneracy point transition control circuit, the chip, the current source and the electronic equipment disclosed by the embodiment of the invention, for the current mirror formed by mirror connection of the first current mirror branch and the second current mirror branch, the input end of the current transition module is connected to the power input end of the first current mirror branch, the output end of the current transition module is connected to the connection point of the P-type transistor and the N-type transistor in the first current mirror branch, the input end and the output end of the current transition module are communicated when the control voltage of the control end of the current transition module is smaller than a threshold value, therefore, when the power supply is electrified, the current transition module can provide bias current for the first current mirror branch, so that the current mirror can transition from a zero point stable state to a state of outputting a stable power supply, and the control end of the current transition module is connected to the power supply, therefore, the potential of the control end of the current transition module can rise along with the connection of the power supply, and is disconnected when the control voltage is larger than the threshold value, namely, the current mirror can stably work under the state of outputting the stable power supply, the stable state, the current mirror is smoothly switched from the current zero point stable state to the stable output state of the power supply, the stable state is not dependent on the stable state, and the stable power consumption of the stable state is realized, and the current source is small, on the aspect is small, and the transition process is realized; on the other hand, the active device can be formed in the chip in an etching mode, and no additional configuration space is needed for placing the resistor, so that the area of the resistor can be saved, the area of the chip is reduced, and the current source chip is small and exquisite and saves cost.
Other advantages of the present invention will be set forth in the description of specific technical features and solutions, by which those skilled in the art should understand the advantages that the technical features and solutions bring.
Drawings
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the figure:
FIG. 1 is a schematic diagram of a current source circuit in the prior art;
fig. 2 is a schematic diagram of a current source degenerate point transition control circuit according to the present embodiment.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in order to avoid obscuring the present invention, and in order to avoid obscuring the present invention, well-known methods, procedures, flows, and components are not presented in detail.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In order to realize that a low-power consumption current source stably transits from a stable state of a current zero point to a stable state of a power supply stable output at a degenerate point, and reduce cost, the embodiment discloses a current source degenerate point transition control circuit, please refer to fig. 2, fig. 2 is a schematic diagram of a current source degenerate point transition control circuit disclosed in the embodiment, the current source degenerate point transition control circuit comprises a first current mirror branch 1, a second current mirror branch 2 and a current transition module 3, wherein:
the first current mirror branch 1 and the second current mirror branch 2 are connected in a mirror image mode to form a current mirror so as to receive a power supply VDD; in a specific embodiment, the first current mirror branch 1 and the second current mirror branch 2 may be implemented by P-type transistors and N-type transistors respectively, which are connected in series, and the P-type transistors and the N-type transistors respectively form a high potential end and a low potential end of the first current mirror branch 1 and the second current mirror branch 2, and in a specific embodiment, the high potential end of the first current mirror branch 1 and the high potential end of the second current mirror branch 2 respectively form power supply input ends of the two branches, so as to receive the power supply VDD, and the low potential end of the first current mirror branch 1 and the low potential end of the second current mirror branch 2 are grounded to GND.
Referring to fig. 2, an input end of a current transition module 3 is connected to a power input end of the first current mirror branch 1, an output end of the current transition module 3 is connected to a connection point of a P-type transistor and an N-type transistor in the first current mirror branch 1, and a control end of the current transition module 3 is connected to a power VDD; the input end and the output end of the current transition module 3 are communicated when the control voltage of the control end of the current transition module 3 is smaller than a threshold value, and are disconnected when the control voltage is larger than the threshold value; wherein the current transition module 3 is implemented by an active device; when the power supply input end of the first current mirror branch 1 receives the power supply VDD, current flows between the input end and the output end of the current transition module 3 to provide bias current for the first current mirror branch 1; when the control voltage exceeds the threshold value, the current transition module 3 disconnects the input and output terminals of the current transition module 3 so that the first current mirror leg 1 and the second current mirror leg 2 operate in a state of outputting a stable power supply. In this embodiment, the current transition module 3 is implemented by an active device, so the above operation can be implemented by the switching property of the active device, and the active device of the current transition module 3 may be, for example, a depletion transistor whose threshold voltage is negative, that is, the depletion transistor is turned on when the control electrode of the depletion transistor has no voltage, and turned off when the control electrode has a voltage. In this embodiment, when the control voltage at the control end of the current transition module 3 is smaller than the threshold value, a bias current path is provided for the first current mirror branch 1, and when the current flows through the current transition module 3, the control voltage at the control end of the current transition module 3 gradually rises along with the increase of the current, and when the control voltage rises to the threshold value, the current transition module 3 is gradually closed, so that the current transition module 3 is stopped from working, and the current source circuit normally works in a stable state of stable output of the power supply.
In a specific embodiment, the current source degeneracy point transition control circuit further includes: a pull-up resistor R2, wherein one end of the pull-up resistor R2 is connected to the power supply VDD, and the power supply input end of the first current mirror branch 1 and the power supply input end of the second current mirror branch 2 are connected to the other end of the pull-up resistor R2 so as to receive the power supply VDD; the control end of the current transition module 3 is connected to the other end of the pull-up resistor R2 so as to be connected to the power supply VDD through the pull-up resistor R2; the potential at the other end of the pull-up resistor R2 provides a control voltage for the current transition module 3. In this embodiment, the control terminal of the current transition module 3 is connected to the other end of the pull-up resistor R2, and when the power supply VDD flows through the pull-up resistor R2, the voltage at the other end of the pull-up resistor R2 gradually increases along with the input of VDD, thereby providing the control terminal of the current transition module 3 with the gradually increasing control voltage.
In an alternative embodiment, the current transition module 3 comprises: the threshold voltage of the transition transistor MN4 is a negative value, the first pole of the transition transistor MN4 is the input end of the current transition module 3, the second pole of the transition transistor MN4 is the output end of the current transition module 3, and the control pole of the transition transistor MN4 is used as the control end of the current transition module 3. In a specific embodiment, the transition transistor MN4 may be a depletion transistor, the threshold voltage of the depletion transistor is negative, and the threshold value is generally about-200 mV, so when the power supply VDD is not powered, the transition transistor MN4 will be in a normally-on state, and when the power supply input end of the first current mirror branch 1 is connected to the power supply VDD, the current flowing out from the power supply input end of the first current mirror branch 1 flows through the first pole and the second pole of the transition transistor MN4, so that the current source circuit breaks the steady state of the current zero point, and the current source circuit works in a state where the current flows; when a current flows through the pull-up resistor R2, the potential at the other end of the pull-up resistor R2 gradually rises, so that the transition transistor MN4 is turned off when the potential rises to the threshold voltage, and then the transition transistor MN4 is turned off, so that the current source is switched from the steady state of the current zero point to the steady state of the power supply steady output. In this embodiment, the pull-up resistor R2 only needs to be able to raise the potential, and since the threshold voltage of the transition transistor is negative, the resistance of the pull-up resistor R2 is greatly reduced, and the start-up circuit does not consume power after the start-up is completed.
In order to increase the negative feedback loop gain of the current mirror, in an alternative embodiment, referring to fig. 2, the current source degenerate point transition control circuit further includes: and one end of the gain amplifying module 4 is connected to the power input ends of the first current mirror branch 1 and the second current mirror branch 2, and the other end of the gain amplifying module 4 is grounded and used for increasing the negative feedback loop gain of the current mirror. Thus, the power supply rejection ratio of the current source circuit is significantly enhanced, so that the output current variation is small at a wide range of variation in the power supply voltage.
In an embodiment, referring to fig. 2, the first current mirror leg 1 includes: a first P-type transistor MP1 and a first N-type transistor MN1; the second current mirror leg 2 comprises: a third P-type transistor MP3 and a third N-type transistor MN3; in this embodiment, the first pole of the first P-type transistor MP1 is the power input end of the first current mirror branch 1, the second pole of the first P-type transistor MP1 is connected to the first pole of the first N-type transistor MN1, and the second pole of the first N-type transistor MN1 is grounded; the first pole of the third P-type transistor MP3 is the power input end of the second current mirror branch 2, the second pole of the third P-type transistor MP3 is connected to the first pole of the third N-type transistor MN3, and the second pole of the third N-type transistor MN3 is grounded; the gate of the first P-type transistor MP1 is mirrored to the gate of the third P-type transistor MP3, and the gate of the first N-type transistor MN1 is mirrored to the gate of the third N-type transistor MN 3. In a specific implementation process, for the embodiment with the pull-up resistor R2, the first pole of the first P-type transistor MP1 and the first pole of the third P-type transistor MP3 are connected to the power supply VDD via the pull-up resistor R2, that is, the first pole of the first P-type transistor MP1 and the first pole of the third P-type transistor MP3 are connected to the other end of the pull-up resistor R2, and one end of the pull-up resistor R2 is connected to the power supply VDD; of course, since one end of the gain amplification module 4 is connected to the power input ends of the first current mirror branch 1 and the second current mirror branch 2, one end of the gain amplification module 4 is also connected to the power supply VDD via the pull-up resistor R2.
In an embodiment, referring to fig. 2, the gain amplifying module 4 includes: a second P-type transistor MP2 and a second N-type transistor MN2, wherein a first pole of the second P-type transistor MP2 is connected to the power input terminals of the first current mirror leg 1 and the second current mirror leg 2; the control electrode of the first P-type transistor MP1 is connected to the second electrode of the second P-type transistor MP 2; the control electrode of the second P-type transistor MP2 is connected with the control electrode of the third P-type transistor MP 3; the control electrode of the third P-type transistor MP3 is connected to the second electrode of the third P-type transistor MP3 to form a bias node of the P-type transistor; the first pole of the second N-type transistor MN2 is connected to the second pole of the second P-type transistor MP2, the control pole of the first N-type transistor MN1 is connected to the control pole of the second N-type transistor MN2 and the control pole of the third N-type transistor MN3, and the second poles of the first N-type transistor MN1, the second pole of the second N-type transistor MN2 and the third N-type transistor MN3 are grounded.
To achieve loop stabilization, in an alternative embodiment, the gain amplification module 4 comprises: one end of the first capacitor C1 is connected to the first pole of the second P-type transistor MP2, and the other end of the first capacitor C1 is connected to a connection point between the control pole of the first P-type transistor MP1 and the second pole of the second P-type transistor MP 2.
In an alternative embodiment, to achieve a current mirror mismatch, the second current mirror leg 2 further comprises:
the high potential end of the first resistor R1 is the power input end of the second current mirror branch 2, the low potential end of the first resistor R1 is connected with the first pole of the third P-type transistor MP3, and the first pole of the third P-type transistor MP3 receives an input power through the first resistor R1.
In a specific embodiment, for an embodiment without the gain amplification module 4, the width-to-length ratio of the first P-type transistor MP1 is equal to the width-to-length ratio of the third P-type transistor MP 3; the width-to-length ratio of the first N-type transistor MN1 is k times the width-to-length ratio of the third N-type transistor MN3, where k is a natural number greater than 1. After the current source is switched from the stable state of the current zero point to the stable state of the power stable output, the width-to-length ratio of the first P-type transistor MP1 and the width-to-length ratio of the third P-type transistor MP3 are 1:1, therefore, the two branch currents of the P-tube current mirror are equal; the width-to-length ratio of the first N-type transistor MN1 is k times that of the third N-type transistor MN3, and the current source current generated at this time is iout= (Vgsmn 1-Vgsmn 3)/R1, so as to obtain a self-bias current source, where Vgsmn1 is the gate-source voltage of the first N-type transistor MN1 and Vgsmn3 is the gate-source voltage of the third N-type transistor MN 3.
For the embodiment with gain amplification module 4, the aspect ratio of the first P-type transistor MP1, the aspect ratio of the second P-type transistor MP2, and the aspect ratio of the third P-type transistor MP3 are 1:1:1, first N-type crystalThe width-to-length ratio of the transistor MN1 is K times that of the second N-type transistor MN2, the width-to-length ratios of the second N-type transistor MN2 and the third N-type transistor MN3 are equal, and the generated current source current is iout= (Vgsmn 1-Vgsmn 2)/R1, wherein Vgsmn1 and Vgsmn2 are gate-source voltages of the first N-type transistor MN1 and the second N-type transistor MN2 respectively, and when the output current is 10nA, the resistor R1 only needs about 5M; because of mismatch of the current mirror, compared with the unipolar current mirror in the conventional structure, MP2 and MN2 gain amplifying modules are added in the circuit structure of the embodiment of FIG. 2, so that the gain of the negative feedback loop feeding back the current mirror is increased by gm NM2 *Ro MN2 //Ro MP2 Wherein gm is NM2 Is the gate-source voltage, ro, of the second N-type transistor MN2 MN2 Is the equivalent output impedance, ro, of the second N-type transistor MN2 MP2 The gain is far greater than 1 for the equivalent output impedance of the second P-type transistor MP2, which results in a significant enhancement of the power supply rejection ratio of the new structure, and thus results in less current variation of the output of the circuit structure over a wide range of power supply voltages.
The embodiment also discloses a low-power consumption current source, which comprises the current source degeneracy point transition control circuit disclosed in the embodiment, and is connected between the power supply VDD and the ground GND, wherein the self-bias current source Iout is led out through the mirror image second current mirror branch 2.
In order to further enhance the power supply rejection ratio and reduce the influence of voltage variation on the output current of the current source, in an alternative embodiment, the first current mirror leg 1, the second current mirror leg 2 and the gain amplifying module 4 respectively comprise a plurality of transistors, and the first current mirror leg 1, the second current mirror leg 2 and the gain amplifying module 4 are implemented by adopting a cascode structure. Specifically, the number of the N-tubes in the first current mirror branch 1, the number of the N-tubes in the second current mirror branch 2 and the number of the N-tubes in the gain amplification module 4 are two, the N-tubes in the respective branches/modules adopt a common-source common-gate connection method to realize a common-source common-gate structure, that is, a first pole and a second pole of the two N-tubes are sequentially connected between the P-tube and the GND in series, the gates of the N-tubes in different branches/modules are connected together, and the sources are grounded. In this embodiment, the first current mirror branch 1, the second current mirror branch 2 and the gain amplifying module 4 are implemented by a cascode structure, so that the power supply rejection ratio can be further enhanced, and the influence of voltage variation on the output current of the current source is reduced.
For ease of understanding by those skilled in the art, the operation of the current source degeneration point transition control circuit disclosed in fig. 2 is described below:
referring to fig. 2, in the degenerate point transition control circuit using the transition transistor MN4 as the reference current source, the threshold voltage of the transition transistor MN4 is negative, the threshold is generally about-200 mV, and when a current flows, the power supply can transition from the state of the current zero point to the stable state, specifically as follows:
before the power supply VDD is electrified, the current source circuit is in an initial state without electricity, at the moment, all transistors in the current source circuit do not work, and at the moment, the current is 0; when the power supply VDD starts to be powered on, the pull-up resistor R2, the transition transistor MN4 and the first N-type transistor MN1 form a current starting path, a normal current flowing path (current flows from VDD to ground GND through the transition transistor MN4 and the first N-type transistor MN 1) is provided during power on until the voltage generated by the current flowing through the pull-up resistor R2 is higher than the threshold voltage of the transition transistor MN4, the transition transistor MN4 is automatically turned off, so that degenerate point state switching (i.e. power supply starting) is completed, and the precision of the reference current is not affected during the starting process; in this embodiment, since the third P-type transistor MP3 is already biased, the transition transistor MN4 is connected to the node where the first P-type transistor MP1 is connected to the bias voltage of the N-type transistor MN1;
when the current source circuit is started, the starting current is Istart= -VGS when the power supply is larger MN4 R2, wherein VGS MN4 The threshold value of the gate-source voltage of the transition transistor MN4 is negative (the value is about-200 mV in the general process); when the starting is completed, the sum of the currents of the first P-type transistor MP1, the second P-type transistor MP2 and the third P-type transistor MP3 is larger than the starting current Istart, namely the transition transistor MN4 can be automatically turned off, so that the accurate value of the reference current source is not affected, and when the reference current source is 10nA, the pull-up resistor R2 is only required to be 7M, and R2 is greatly reducedThe area of the circuit board is reduced and the start-up circuit does not consume power after the start-up is completed (because the transition transistor MN4 has been turned off).
The current source circuit is started, the circuit gets rid of the degenerate working point with the current of 0, the current source starts to work normally, and when the width-to-length ratio of the first P-type transistor MP1, the width-to-length ratio of the second P-type transistor MP2 and the width-to-length ratio of the third P-type transistor MP3 are 1:1: in the step 1, the currents of the three branches of the P-tube current mirror 1 are equal; the width-to-length ratio of the first N-type transistor MN1 is K times that of the second N-type transistor MN2, the width-to-length ratios of the second N-type transistor MN2 and the third N-type transistor MN3 are equal, and the generated current source current is iout= (Vgsmn 1-Vgsmn 2)/R1, wherein Vgsmn1 and Vgsmn2 are gate-source voltages of the first N-type transistor MN1 and the second N-type transistor MN2 respectively, and when the output current is 10nA, the resistor R1 only needs about 5M; because of mismatch of the current mirror, compared with the unipolar current mirror in the conventional structure, MP2 and MN2 gain amplifying circuits are added in the circuit structure of the embodiment of FIG. 2, so that the gain of the negative feedback loop feeding back the current mirror is increased by gm MN2 *Ro MN2 //Ro MP2 Wherein gm is NM2 Is the gate-source voltage, ro, of the second N-type transistor MN2 MN2 Is the equivalent output impedance, ro, of the second N-type transistor MN2 MP2 The gain is much greater than 1 for the equivalent output impedance of the second P-type transistor MP2, which results in a significant increase in the power supply rejection ratio of the new structure, and thus results in less current variation of the circuit structure of the embodiment of fig. 2 output over a wide range of power supply voltages.
The embodiment also discloses a current source chip, on which the current source degeneracy point transition control circuit disclosed in the above embodiment is integrated, or the current source disclosed in the above embodiment.
The embodiment also discloses an electronic device with a current source, which comprises the current source degenerate point transition control circuit disclosed in the embodiment or the current source disclosed in the embodiment.
According to the current source degeneracy point transition control circuit, the chip, the current source and the electronic equipment disclosed by the embodiment of the invention, for the current mirror formed by mirror connection of the first current mirror branch and the second current mirror branch, the input end of the current transition module is connected to the power input end of the first current mirror branch, the output end of the current transition module is connected to the connection point of the P-type transistor and the N-type transistor in the first current mirror branch, the input end and the output end of the current transition module are communicated when the control voltage of the control end of the current transition module is smaller than a threshold value, therefore, when the power supply is electrified, the current transition module can provide bias current for the first current mirror branch, so that the current mirror can transition from a zero point stable state to a state of outputting a stable power supply, and the control end of the current transition module is connected to the power supply, therefore, the potential of the control end of the current transition module can rise along with the connection of the power supply, and is disconnected when the control voltage is larger than the threshold value, namely, the current mirror can stably work under the state of outputting the stable power supply, the stable state, the current mirror is smoothly switched from the current zero point stable state to the stable output state of the power supply, the stable state is not dependent on the stable state, and the stable power consumption of the stable state is realized, and the current source is small, on the aspect is small, and the transition process is realized; on the other hand, the active device can be formed in the chip in an etching mode, and no additional configuration space is needed for placing the resistor, so that the area of the resistor can be saved, the area of the chip is reduced, and the current source chip is small and exquisite and saves cost.
Those skilled in the art will appreciate that the above-described preferred embodiments can be freely combined and stacked without conflict. In which the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures, for example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. The numbering of the steps herein is for convenience of illustration and reference only and is not intended to limit the order in which the steps are performed, the particular order of execution being determined by the technology itself, and the skilled artisan can determine various allowable, reasonable orders based on the technology itself.
Those skilled in the art will appreciate that the above-described preferred embodiments can be freely combined and stacked without conflict.
It will be understood that the above-described embodiments are merely illustrative and not restrictive, and that all obvious or equivalent modifications and substitutions to the details given above may be made by those skilled in the art without departing from the underlying principles of the invention, are intended to be included within the scope of the appended claims.
Claims (12)
1. A current source degeneracy point transition control circuit, comprising: a first current mirror branch (1) and a second current mirror branch (2),
the first current mirror branch circuit (1) and the second current mirror branch circuit (2) are connected in a mirror image mode to form a current mirror so as to receive a power supply (VDD);
the low potential end of the first current mirror branch (1) and the low potential end of the second current mirror branch (2) are Grounded (GND);
the input end of the current transition module (3) is connected to the power supply input end of the first current mirror branch circuit (1), the output end of the current transition module (3) is connected to a connection point of a P-type transistor and an N-type transistor in the first current mirror branch circuit (1), and the control end of the current transition module (3) is connected to the power supply (VDD); the input end and the output end of the current transition module (3) are communicated when the control voltage of the control end of the current transition module (3) is smaller than a threshold value, and are disconnected when the control voltage is larger than the threshold value; wherein the current transition module (3) is implemented by an active device;
when the power supply input end of the first current mirror branch circuit (1) receives a power supply (VDD), current flows between the input end and the output end of the current transition module (3) so as to provide bias current for the first current mirror branch circuit (1); when the control voltage exceeds a threshold value, the current transition module (3) disconnects the input end and the output end of the current transition module (3) so that the first current mirror branch (1) and the second current mirror branch (2) work in a state of outputting a stable power supply.
2. The current source degeneration point transition control circuit of claim 1, further comprising:
a pull-up resistor (R2) having one end connected to a power supply (VDD), the power supply input of the first current mirror leg (1) and the power supply input of the second current mirror leg (2) being connected to the other end of the pull-up resistor (R2) to receive the power supply (VDD);
the control end of the current transition module (3) is connected to the other end of the pull-up resistor (R2) so as to be connected to the power supply (VDD) through the pull-up resistor (R2); the potential at the other end of the pull-up resistor (R2) provides the control voltage for the current transition module (3).
3. A current source degeneration point transition control circuit according to claim 1 or 2, wherein,
the current transition module (3) comprises:
the threshold voltage of the transition transistor (MN 4) is a negative value, a first pole of the transition transistor (MN 4) is an input end of the current transition module (3), and a second pole of the transition transistor (MN 4) is an output end of the current transition module (3).
4. The current source degeneration point transition control circuit of claim 1 or 2, further comprising:
and one end of the gain amplifying module (4) is connected to the power input ends of the first current mirror branch (1) and the second current mirror branch (2), and the other end of the gain amplifying module (4) is grounded and is used for increasing the negative feedback loop gain of the current mirror.
5. The current source degeneration point transition control circuit of claim 4,
the first current mirror leg (1) comprises: a first P-type transistor (MP 1) and a first N-type transistor (MN 1);
the second current mirror leg (2) comprises: a third P-type transistor (MP 3) and a third N-type transistor (MN 3);
a first pole of the first P-type transistor (MP 1) is a power input end of the first current mirror branch (1), a second pole of the first P-type transistor (MP 1) is connected to a first pole of the first N-type transistor (MN 1), and a second pole of the first N-type transistor (MN 1) is grounded;
the first pole of the third P-type transistor (MP 3) is the power input end of the second current mirror branch (2), the second pole of the third P-type transistor (MP 3) is connected to the first pole of the third N-type transistor (MN 3), and the second pole of the third N-type transistor (MN 3) is grounded;
the control electrode of the first P-type transistor (MP 1) is mirror image with the control electrode of the third P-type transistor (MP 3), and the control electrode of the first N-type transistor (MN 1) is mirror image with the control electrode of the third N-type transistor (MN 3).
6. The current source degeneration point transition control circuit of claim 5,
the gain amplification module (4) comprises: a second P-type transistor (MP 2) and a second N-type transistor (MN 2);
-a first pole of the second P-type transistor (MP 2) is connected to the power supply inputs of the first current mirror leg (1) and the second current mirror leg (2); -the control electrode of the first P-type transistor (MP 1) is connected to the second electrode of the second P-type transistor (MP 2); the control electrode of the second P-type transistor (MP 2) is connected with the control electrode of the third P-type transistor (MP 3); a control electrode of the third P-type transistor (MP 3) is connected to a second electrode of the third P-type transistor (MP 3) to form a bias node of the P-type transistor;
the first pole of the second N-type transistor (MN 2) is connected to the second pole of the second P-type transistor (MP 2), the control pole of the first N-type transistor (MN 1) is connected with the control pole of the second N-type transistor (MN 2) and the control pole of the third N-type transistor (MN 3), and the second pole of the first N-type transistor (MN 1), the second pole of the second N-type transistor (MN 2) and the second pole of the third N-type transistor (MN 3) are grounded.
7. The current source degeneracy point transition control circuit of claim 6, characterized in that the gain amplification module (4) comprises:
and one end of the first capacitor (C1) is connected with the first pole of the second P-type transistor (MP 2), and the other end of the first capacitor (C1) is connected with a connection point of the control pole of the first P-type transistor (MP 1) and the second pole of the second P-type transistor (MP 2).
8. The current source degenerate point transition control circuit as recited in claim 5, wherein the second current mirror leg (2) further comprises:
the high potential end of the first resistor (R1) is the power input end of the second current mirror branch circuit (2), the low potential end of the first resistor (R1) is connected with the first pole of the third P-type transistor (MP 3), and the first pole of the third P-type transistor (MP 3) receives an input power through the first resistor (R1).
9. A current source for providing an operating power supply for a subsequent stage circuit, the current source comprising:
a current source degeneracy-point transition control circuit as defined in any one of claims 1-8.
10. The current source of claim 9, comprising a current source degeneracy point transition control circuit as recited in claim 4;
the first current mirror branch circuit (1), the second current mirror branch circuit (2) and the gain amplification module (4) respectively comprise a plurality of transistors, and the first current mirror branch circuit (1), the second current mirror branch circuit (2) and the gain amplification module (4) are realized by adopting a cascode structure.
11. A current source chip having integrated thereon a current source degeneration point transition control circuit according to any one of claims 1-7, or a current source according to claim 9 or 10.
12. An electronic device with a current source, characterized by comprising a current source degenerated point transition control circuit according to any of claims 1-8, or a current source according to claim 9 or 10.
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| CN201097250Y (en) * | 2007-09-20 | 2008-08-06 | 华中科技大学 | High-power restraint standard source with gap |
| CN102385405A (en) * | 2010-08-27 | 2012-03-21 | 杭州中科微电子有限公司 | General band gap reference starting circuit |
| CN214253044U (en) * | 2020-12-08 | 2021-09-21 | 珠海零边界集成电路有限公司 | Current source circuit and electronic equipment |
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| US11789481B2 (en) * | 2021-08-10 | 2023-10-17 | Psemi Corporation | Current mirror pre-bias for increased transition speed |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201097250Y (en) * | 2007-09-20 | 2008-08-06 | 华中科技大学 | High-power restraint standard source with gap |
| CN102385405A (en) * | 2010-08-27 | 2012-03-21 | 杭州中科微电子有限公司 | General band gap reference starting circuit |
| CN214253044U (en) * | 2020-12-08 | 2021-09-21 | 珠海零边界集成电路有限公司 | Current source circuit and electronic equipment |
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