CN116633116B - Low-power consumption current source, current source circuit, chip and electronic equipment with low-power consumption current source circuit - Google Patents
Low-power consumption current source, current source circuit, chip and electronic equipment with low-power consumption current source circuit Download PDFInfo
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- CN116633116B CN116633116B CN202310904194.7A CN202310904194A CN116633116B CN 116633116 B CN116633116 B CN 116633116B CN 202310904194 A CN202310904194 A CN 202310904194A CN 116633116 B CN116633116 B CN 116633116B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0032—Control circuits allowing low power mode operation, e.g. in standby mode
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
- Amplifiers (AREA)
Abstract
The invention provides a low-power-consumption current source, a current source circuit, a chip and an electronic device with the same, wherein the low-power-consumption current source circuit comprises: the power supply input end of the P-tube current mirror is connected to the power supply, and the P-tube current mirror is used for being led out of the power supply by mirror image so as to provide power supply outwards; the N-tube current mirror is connected between the P-tube current mirror and the ground, and the N-tube current mirror and the P-tube current mirror form a current source; the degeneracy point switching module is connected between the bias node of the P-tube current mirror and the ground, and keeps a normally-on state before the stable output power supply of the current source. The starting power consumption of the current source circuit is reduced, and the area of the resistor is saved.
Description
Technical Field
The invention relates to the technical field of current sources, in particular to a low-power-consumption current source, a current source circuit, a chip and electronic equipment with the low-power-consumption current source circuit.
Background
In a low-power chip, a current source which is usually low in power consumption needs to be designed to supply power for the whole chip analog circuit so as to provide current bias. The low-power consumption chip is generally applied in the field of batteries, and because the voltage of the battery is related to the material and the number of nodes, the circuit is required to meet the requirement that the power supply voltage has the property of keeping low power consumption in a wider variation range, and the output current does not change along with the variation of the power supply voltage.
In the prior art, please refer to fig. 1, fig. 1 is a schematic diagram of a current source circuit in the prior art, and there is a degeneracy point in the current source, that is, two working states of the current source are switched from a stable state of a current zero point to a stable state of a stable output of the power source, in order to realize stable switching of the working states of the current source, a start-up circuit is usually required, and a transistor M5 in fig. 1 isThe starting bias is provided for the current source, so that the degeneracy point in starting is eliminated, the transistor M5 is turned on when the power supply VDD is powered up, the gates of the transistors M3 and M4 and the gates of the transistors M1 and M2 are communicated, the bias voltage is provided for the current mirror, and the output of the current source is not influenced after the output of the current mirror is stable, the transistor M5 is turned off. The circuit provides an N-type current source through the transistor M1 and the transistor M2; the current mirror formed by the transistor M3 and the transistor M4 realizes the external P-type current source. Because the power supply has a larger variation range (1 v-5.5 v) under low power consumption application, the voltage va=vdd-VGS of the node a at different power supply voltages M4 Voltage vb=vgs of node b M1 The larger the supply voltage; the larger the difference between Va and Vb, the larger the mirror image offset of the current mirror will be, so the current accuracy of the circuit will change more with the change of the power supply voltage.
Since the transistor M5 is turned off with low power consumption, the following relationship needs to be satisfied:
I M6 *R 2 > VDD-VGS M4 -VGS M5
wherein I is M6 VGS is the current flowing through transistor M6 M4 、VGS M5 The gate-source voltages of transistors M4, M5, respectively, thus, it can be seen that when the VDD voltage is large, a large resistor R2, e.g., I, is required to achieve low power consumption M6 Is 10na, vdd=5.5V VGS M4 =VGS M5 =1v, where the resistance of R2 needs to be around 350M, this results in a large cost.
Therefore, how to reduce the power consumption of degenerate point state switching of the current source circuit and save the area of the resistor is a technical problem to be solved.
Disclosure of Invention
Based on the above-mentioned current situation, a main object of the present invention is to provide a low-power-consumption current source, a current source circuit, a chip and an electronic device with the same, so as to reduce the starting power consumption of the current source circuit and save the area of a resistor.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
in a first aspect, an embodiment of the present invention discloses a current source circuit, including:
the power supply input end of the P-tube current mirror is connected to the power supply, and the P-tube current mirror is used for being led out of the power supply by mirror image so as to provide power supply outwards;
the N-tube current mirror is connected between the P-tube current mirror and the ground, and the N-tube current mirror and the P-tube current mirror form a current source;
the degeneracy point switching module is connected between the bias node of the P-tube current mirror and the ground, and keeps a normally-on state before the stable output power supply of the current source.
In a second aspect, an embodiment of the present invention discloses a low power consumption current source, including:
the current source circuit disclosed in the first aspect, wherein the P-tube current mirror is implemented by a cascode structure.
In a third aspect, an embodiment of the present invention discloses a low power consumption current source chip, on which the current source circuit disclosed in the first aspect or the low power consumption current source disclosed in the second aspect is integrated.
In a fourth aspect, an embodiment of the present invention discloses an electronic device with a low power consumption current source, including the current source circuit disclosed in the first aspect, or the low power consumption current source disclosed in the second aspect.
According to the low-power consumption current source, the current source circuit, the chip and the electronic equipment with the low-power consumption current source, the degeneracy point switching module is connected between the bias node of the P-tube current mirror and the ground, and the degeneracy point switching module is kept in a normally-on state before a stable output power supply of the current source, so that a current path can be provided for the bias node of the P-tube current mirror, namely, when the P-tube current mirror is connected with the power supply, current flowing out of the bias node of the P-tube current mirror can flow through the degeneracy point switching module, so that the current source can be smoothly started to work when the current flowing out of the bias node of the P-tube current mirror exceeds a threshold value, and when the current flowing out of the bias node of the P-tube current mirror exceeds the threshold value, the degeneracy point switching module is disconnected, so that the degeneracy point of the current source can be removed, the current source can be smoothly switched from the stable state of a current zero point to the stable state of the power supply, extra power consumption is avoided, and the state switching is performed through the current size, so that the dependency on the resistance is small, and the area of the resistor can be saved.
Other advantages of the present invention will be set forth in the description of specific technical features and solutions, by which those skilled in the art should understand the advantages that the technical features and solutions bring.
Drawings
Embodiments of the present invention will be described below with reference to the accompanying drawings. In the figure:
FIG. 1 is a schematic diagram of a current source circuit in the prior art;
fig. 2 is a schematic diagram of a current source circuit according to the present embodiment;
fig. 3 is a schematic diagram of another current source circuit disclosed in this embodiment;
fig. 4 is a schematic diagram of a low-power consumption current source circuit according to the present embodiment.
Detailed Description
The present invention is described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth in order to avoid obscuring the present invention, and in order to avoid obscuring the present invention, well-known methods, procedures, flows, and components are not presented in detail.
Moreover, those of ordinary skill in the art will appreciate that the drawings are provided herein for illustrative purposes and that the drawings are not necessarily drawn to scale.
Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, it is the meaning of "including but not limited to".
In the description of the present invention, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "a plurality" is two or more.
In order to reduce power consumption of degenerate point state switching and save area of resistor of the current source circuit, the present embodiment discloses a current source circuit, please refer to fig. 2, fig. 2 is a schematic diagram of a current source circuit disclosed in the present embodiment, the current source circuit includes: a P-tube current mirror 1, an N-tube current mirror 2 and a degenerate point switching module 3, wherein:
the power input end of the P-tube current mirror 1 is connected to the power supply VDD, in this embodiment, the P-tube current mirror 1 is used for being mirrored to draw power to provide power to the outside, and in particular, may provide power for the later-stage circuit. In this embodiment, the P-tube current mirror 1 is a current mirror formed of P-type transistors.
The N-tube current mirror 2 is connected between the P-tube current mirror 1 and the ground GND, and the N-tube current mirror 2 and the P-tube current mirror 1 form a current source. In this embodiment, the N-tube current mirror 2 is a current mirror formed of an N-type transistor.
Referring to fig. 2, the degenerated point switching module 3 is connected between the bias node of the P-tube current mirror 1 and the ground GND, in the embodiment of fig. 2, the bias node of the P-tube current mirror 1 is the point B shown in fig. 2, the degenerated point switching module 3 is kept in a normally-on state before the stable output power of the current source, when the P-tube current mirror 1 is connected to the power supply VDD, the current flowing out of the bias node B of the P-tube current mirror 1 flows through the degenerated point switching module 3, and when the current flowing out of the bias node B of the P-tube current mirror 1 exceeds the threshold value, the degenerated point switching module 3 is turned off to switch the stable state of the current zero point of the current source to the stable state of the stable output of the power source. Specifically, the degenerate point switching module 3 is kept in a normally-on state, and is configured to provide a current path for the bias node B of the P-tube current mirror 1, and when a current flows through the degenerate point switching module 3, the degenerate point switching module 3 is gradually turned off with an increase of the current, so that the current source circuit is stopped from working, and the current source circuit is enabled to normally work in a stable state where a power supply stably outputs. Specifically, when the P-tube current mirror 1 is connected to the power supply VDD, the current flowing out of the bias node B of the P-tube current mirror 1 flows through the degenerate point switching module 3, so that the current source circuit breaks the steady state of the current zero point, and the current source circuit works in a state that the current flows through, when the current flowing out of the bias node B of the P-tube current mirror 1 exceeds a threshold value, the current source circuit can stably output the power supply, and at the moment, the degenerate point switching module 3 is disconnected, so that the steady state of the current zero point of the current source is switched to the steady state of the power supply for stable output. In this embodiment, the degenerate point switching module 3 is formed by active devices, and the on/off of the degenerate point switching module 3 can be realized by a switch mode, and since the active devices can be etched in the circuit board together with other active devices, the control modes such as resistance will not occupy additional circuit board area, so that the chip size can be effectively reduced.
In a specific embodiment, the degenerate point switch module 3 comprises: a first pole of the depletion transistor MN4 is connected to the bias node B of the P-tube current mirror 1, and a second pole of the depletion transistor MN4 is connected to one end of the pull-up resistor R2; the other end of the pull-up resistor R2 is grounded to the gate of the depletion transistor MN 4. In this embodiment, when the P-tube current mirror 1 is connected to the power supply VDD, the current flowing from the bias node B of the P-tube current mirror 1 flows through the first pole and the second pole of the depletion transistor MN4, so that the potential at one end of the pull-up resistor R2 gradually increases, and the depletion transistor MN4 is turned off when the potential rises to the threshold voltage of the depletion transistor MN4, so that the degeneracy point switching module 3 is turned off. Specifically, the threshold voltage of the depletion transistor is negative, and the threshold value is generally about-200 mV, so that when the power supply VDD is not powered, the depletion transistor MN4 is in a normally-on state, and therefore, when the P-tube current mirror 1 is connected to the power supply VDD, the current flowing out from the bias node B of the P-tube current mirror 1 flows through the first pole and the second pole of the depletion transistor MN4, so that the current source circuit breaks the steady state of the current zero point, and the current source circuit works in a state that the current flows through; when a current flows through the pull-up resistor R2, the potential at one end of the pull-up resistor R2 gradually rises, so that the depletion transistor MN4 is turned off when the potential at one end of the pull-up resistor R2 rises to the threshold voltage, and then the depletion transistor MN4 is turned off, so that the current source is switched from the steady state of the current zero point to the steady state of the power supply steady output. In this embodiment, the pull-up resistor R2 only needs to be able to raise the potential, and since the threshold voltage of the depletion transistor is negative, the resistance of the pull-up resistor R2 is greatly reduced, and the start-up circuit does not consume power after the start-up is completed.
In an embodiment, referring to fig. 2, the P-transistor current mirror 1 includes a first P-type transistor MP1 and a third P-type transistor MP3, and the N-transistor current mirror 2 includes a first N-type transistor MN1 and a third N-type transistor MN3, wherein: the first pole of the first P-type transistor MP1 and the first pole of the third P-type transistor MP3 are connected to the power supply VDD, the control pole of the first P-type transistor MP1 is connected to the control pole of the third P-type transistor MP3, and the control pole of the first P-type transistor MP1 is connected to the second pole of the first P-type transistor MP1 to form the bias node B of the P-transistor current mirror 1; the first pole of the first N-type transistor MN1 is connected to the second pole of the first P-type transistor MP1, the first pole of the third N-type transistor MN3 is connected to the second pole of the third P-type transistor MP3, the control pole of the first N-type transistor MN1 is connected to the control pole of the third N-type transistor MN3, the second pole of the first N-type transistor MN1 and the second pole of the third N-type transistor MN3 are connected to one end of the pull-up resistor R2, and the control pole of the third N-type transistor MN3 is connected to the first pole of the third N-type transistor MN3 to form the bias node of the N-transistor current mirror 2 (as indicated by the point a in fig. 2). In this embodiment, since the third N-type transistor MN3 is already biased, the first pole of the depletion transistor MN4 should be connected to the first N-type transistor MN1 to provide the bias current for the first N-type transistor MN 1.
In an alternative embodiment, to implement a current mirror mismatch, the current source circuit further comprises: the second pole of the first N-type transistor MN1 is connected to one end of the pull-up resistor R2 through the first resistor R1.
In a specific embodiment, the width-to-length ratio of the first P-type transistor MP1 is equal to the width-to-length ratio of the third P-type transistor MP 3; the width-to-length ratio of the first N-type transistor MN1 is k times the width-to-length ratio of the third N-type transistor MN3, where k is a natural number greater than 1. After the current source is switched from the stable state of the current zero point to the stable state of the power stable output, the width-to-length ratio of the first P-type transistor MP1 and the width-to-length ratio of the third P-type transistor MP3 are 1:1, therefore, the two branch currents of the P-tube current mirror are equal; the width-to-length ratio of the first N-type transistor MN1 is k times that of the third N-type transistor MN3, and the current source current generated at this time is iout= (Vgsmn 1-Vgsmn 3)/R1, so as to obtain a self-bias current source, where Vgsmn1 is the gate-source voltage of the first N-type transistor MN1 and Vgsmn3 is the gate-source voltage of the third N-type transistor MN 3.
In order to increase the negative feedback loop gain of the current mirror, in an alternative embodiment, please refer to fig. 2 and 3, fig. 3 is a schematic diagram of another current source circuit disclosed in this embodiment, the current source circuit further includes: and the gain amplifying circuit is connected between the P-tube current mirror 1 and the N-tube current mirror 2 and is used for increasing the gain of the negative feedback loop. Thus, the power supply rejection ratio of the current source circuit is significantly enhanced, so that the output current variation is small at a wide range of variation in the power supply voltage.
In an embodiment, referring to fig. 3, the gain amplifying circuit includes: a second P-type transistor MP2 and a second N-type transistor MN2, wherein:
the first pole of the first P-type transistor MP1, the first pole of the second P-type transistor MP2 and the first pole of the third P-type transistor MP3 are connected to the power supply VDD, the control pole of the first P-type transistor MP1, the control pole of the second P-type transistor MP2 are connected to the control pole of the third P-type transistor MP3, and the control pole of the third P-type transistor MP3 is connected to the second pole of the third P-type transistor MP3 to form the bias node a of the P-type transistor current mirror 1;
the first pole of the first N-type transistor MN1 is connected to the second pole of the first P-type transistor MP1, the first pole of the second N-type transistor MN2 is connected to the second pole of the second P-type transistor MP2, the first pole of the third N-type transistor MN3 is connected to the second pole of the third P-type transistor MP3, the control pole of the first N-type transistor MN1 is connected with the control pole of the second N-type transistor MN2, the second pole of the first N-type transistor MN1, the second pole of the second N-type transistor MN2 and the second pole of the third N-type transistor MN3 are connected to one end of a pull-up resistor R2, and the control pole of the third N-type transistor MN3 is connected to the first pole of the second N-type transistor MN 2.
To achieve loop stability, in an alternative embodiment, the gain amplification circuit further comprises: the first capacitor C1, the first capacitor C1 is connected between the control electrode of the third N-type transistor MN3 and one end of the pull-up resistor R2.
For the convenience of understanding of those skilled in the art, the following description will be given of the operation of the current source circuit disclosed in fig. 2 and 3:
referring to fig. 2, in the control circuit for degenerate point state switching with the depletion transistor MN4 as the reference current source, the threshold voltage of the depletion transistor MN4 is negative, the threshold is generally about-200 mV, and when a current flows, state switching can be performed at the degenerate point, and the state of the current zero point is eliminated, specifically as follows:
before the power supply VDD is electrified, the current source circuit is in an initial state without electricity, at the moment, all transistors in the current source circuit do not work, and at the moment, the current is 0; when the power supply VDD starts to be powered on, the first P-type transistor MP1, the depletion transistor MN4 and the pull-up resistor R2 form a current start-up path, and a normal current flow path is provided during power-on until the voltage generated by the current flowing through the pull-up resistor R2 is higher than the threshold voltage of the depletion transistor MN4, the depletion transistor MN4 will be automatically turned off, so that degenerate point state switching (i.e. power supply start-up) is completed, and the precision of the reference current will not be affected during the start-up process; in this embodiment, since the third N-type transistor MN3 is already biased, the depletion transistor MN4 is connected to the node where the first N-type transistor MN1 is connected to the bias voltage Vb of the P-tube current mirror;
when the current source circuit is started, the starting current (drain current of depletion transistor MN4, flowing through pull-up resistor R2) at the time of large power supply is Istart= -VGS MN4 R2, wherein VGS MN4 The threshold of the depletion transistor MN4 is negative (general processThis value is about-200 mV); when the starting is completed, the current sum of the first N-type transistor MN1 and the third N-type transistor MN3 is larger than the starting current Istart, and the depletion transistor MN4 can be automatically turned off, so that the accurate value of the reference current source is not affected, and therefore, when the reference current source is 10nA, the pull-up resistor R2 is only 10M, the resistance value of the pull-up resistor R2 is greatly reduced, the area of a circuit board is reduced, and the starting circuit does not consume power consumption after the starting is completed (because the depletion transistor MN4 is already turned off).
The current source circuit is started, the current source circuit gets rid of the degenerate working point with the current of 0, the current source starts to work normally, and when the width-to-length ratio of the first P-type transistor MP1 and the width-to-length ratio of the third P-type transistor MP3 are 1: in the step 1, the currents of the two branches of the P-tube current mirror 1 are equal; the width-to-length ratio of the first N-type transistor MN1 is K times that of the third N-type transistor MN3, and the current source current generated at this time is iout= (Vgsmn 1-Vgsmn 3)/R1, so as to obtain a self-bias current source, where Vgsmn1 and Vgsmn3 are gate-source voltages of the first N-type transistor MN1 and the third N-type transistor MN3 respectively, and when in practical application, mirror-image with the P-tube current mirror 1 can lead out the self-bias current source Iout.
With respect to the embodiment of fig. 2, a gain amplifying circuit is added in fig. 3, please refer to fig. 3, and the operation procedure is as follows:
before the power supply VDD is electrified, the current source circuit is in an initial state without electricity, at the moment, all transistors in the current source circuit do not work, and at the moment, the current is 0; when the power supply VDD starts to be powered on, the first P-type transistor MP1, the depletion transistor MN4 and the pull-up resistor R2 form a current start-up path, and a normal current flow path is provided during power-on until the voltage generated by the current flowing through the pull-up resistor R2 is higher than the threshold voltage of the depletion transistor MN4, the depletion transistor MN4 will be automatically turned off, so that degenerate point state switching (i.e. power supply start-up) is completed, and the precision of the reference current will not be affected during the start-up process; in this embodiment, since the first N-type transistor MN1 is already biased, the depletion transistor MN4 is connected to the node where the third N-type transistor MN3 is connected to the bias voltage Va of the P-tube current mirror;
when the current source circuit is started, the starting current (drain current of depletion transistor MN4, flowing through pull-up resistor R2) at the time of large power supply is Istart= -VGS MN4 R2, wherein VGS MN4 The threshold value of the depletion transistor MN4 is negative (the value is about-200 mV in the general process); when the starting is completed, the current sum of the first N-type transistor MN1, the second N-type transistor MN2 and the third N-type transistor MN3 is larger than the starting current Istart, and the depletion transistor MN4 can be automatically turned off, so that the accurate value of the reference current source is not affected, and when the reference current source is 10nA, the pull-up resistor R2 is only 7M, the resistance value of the R2 is greatly reduced, the area of a circuit board is reduced, and the starting circuit does not consume power consumption after the starting is completed (because the depletion transistor MN4 is already turned off).
The current source circuit is started, the circuit gets rid of the degenerate working point with the current of 0, the current source starts to work normally, and when the width-to-length ratio of the first P-type transistor MP1, the width-to-length ratio of the second P-type transistor MP2 and the width-to-length ratio of the third P-type transistor MP3 are 1:1: in the step 1, the currents of the three branches of the P-tube current mirror 1 are equal; the width-to-length ratio of the first N-type transistor MN1 is K times that of the second N-type transistor MN2, the width-to-length ratios of the second N-type transistor MN2 and the third N-type transistor MN3 are equal, and the generated current source current is iout= (Vgsmn 1-Vgsmn 2)/R1, wherein Vgsmn1 and Vgsmn2 are gate-source voltages of the first N-type transistor MN1 and the second N-type transistor MN2 respectively, and when the output current is 10nA, the resistor R1 only needs about 5M; because of mismatch of the current mirror, when the power supply voltage VDD is large, the voltage difference between the bias node Va and the bias nodes Vb and Vc (where vb=vc) is large, and compared with the unipolar current mirror in the conventional structure, the circuit structure of the embodiment of fig. 3 adds the MP2 and MN2 gain amplifying circuits, so that the gain of the negative feedback loop feeding back the current mirror is increased by gm NM2 *Ro MN2 //Ro MP2 Wherein gm is NM2 Is the gate-source voltage, ro, of the second N-type transistor MN2 MN2 Is the equivalent output impedance, ro, of the second N-type transistor MN2 MP2 Is the equivalent output impedance of the second P-type transistor MP2, the gain is much greater than 1,this allows the power supply rejection ratio of the new structure to be significantly enhanced, so that the circuit configuration of the embodiment of fig. 3 will have less current variation in output over a wide range of power supply voltages.
The embodiment also discloses a low-power consumption current source, which comprises the current source circuit disclosed in the embodiment, and is connected between the power supply VDD and the ground GND, wherein the self-bias current source Iout is led out through the mirror P-tube current mirror 1.
To further enhance the power supply rejection ratio, the effect of voltage variations on the current source output current is reduced, in an alternative embodiment the P-tube current mirror 1 is implemented by a cascode structure. Referring to fig. 4, fig. 4 is a schematic diagram of a low-power consumption current source circuit according to the present embodiment, and, with respect to the embodiment of fig. 3, the P-tube current mirror 1 in the low-power consumption current source circuit shown in fig. 4 is implemented by a cascode structure (as shown in a dashed box in fig. 4). It should be noted that, in the case where the gain amplifying circuit module exists, the P-type transistor should also implement a cascode structure together with the P-type transistor in the P-tube current mirror 1, and in this embodiment, the device of the cascode structure includes: the first P-type transistor MP1, the second P-type transistor MP2, the third P-type transistor MP3, the fourth P-type transistor MP4, the fifth P-type transistor MP5 and the sixth P-type transistor MP6, wherein the first pole of the first P-type transistor MP1, the first pole of the second P-type transistor MP2 and the first pole of the third P-type transistor MP3 are connected to the power supply VDD; the second pole of the first P-type transistor MP1, the second pole of the second P-type transistor MP2, and the second pole of the third P-type transistor MP3 are respectively connected to the first pole of the fourth P-type transistor MP4, the first pole of the fifth P-type transistor MP5, and the first pole of the sixth P-type transistor MP 6; the second pole of the fourth P-type transistor MP4, the second pole of the fifth P-type transistor MP5 and the second pole of the sixth P-type transistor MP6 are respectively connected to three branches of the N-tube current mirror; the control electrode of the first P-type transistor MP1, the control electrode of the second P-type transistor MP2 and the control electrode of the third P-type transistor MP3 are connected and connected to the second electrode of the third P-type transistor MP 3; the control electrode of the fourth P-type transistor MP4, the control electrode of the fifth P-type transistor MP5 and the control electrode of the sixth P-type transistor MP6 are connected and connected to the second electrode of the sixth P-type transistor MP 6; the first pole of the depletion transistor MN4 is connected to the second pole of the sixth P-type transistor MP6, and the specific connection relationship between other devices is shown in fig. 4, which is not repeated here. In this embodiment, the P-tube current mirror 1 is implemented by a cascode structure, so that the power supply rejection ratio can be further enhanced, and the influence of voltage variation on the output current of the current source is reduced.
The embodiment also discloses a low-power-consumption current source chip, on which the current source circuit disclosed in the above embodiment is integrated, or the low-power-consumption current source disclosed in the above embodiment.
The embodiment also discloses an electronic device with the low-power-consumption current source, which comprises the current source circuit disclosed in the embodiment or the low-power-consumption current source disclosed in the embodiment.
According to the low-power consumption current source, the current source circuit, the chip and the electronic equipment with the low-power consumption current source, the degeneracy point switching module is connected between the bias node of the P-tube current mirror and the ground, and the degeneracy point switching module is kept in a normally-on state before a stable output power supply of the current source, so that a current path can be provided for the bias node of the P-tube current mirror, namely, when the P-tube current mirror is connected with the power supply, current flowing out of the bias node of the P-tube current mirror can flow through the degeneracy point switching module, so that the current source can be smoothly started to work when the current flowing out of the bias node of the P-tube current mirror exceeds a threshold value, and when the current flowing out of the bias node of the P-tube current mirror exceeds the threshold value, the degeneracy point switching module is disconnected, so that the degeneracy point of the current source can be removed, the current source can be smoothly switched from the stable state of a current zero point to the stable state of the power supply, extra power consumption is avoided, and the state switching is performed through the current size, so that the dependency on the resistance is small, and the area of the resistor can be saved.
Furthermore, a primary gain amplifying circuit is added in the current source circuit, so that the power supply rejection ratio of the current source is effectively improved, the current precision under different power supply voltages is ensured, and the application of low power supply voltage is realized on the premise.
Those skilled in the art will appreciate that the above-described preferred embodiments can be freely combined and stacked without conflict. In which the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures, for example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. The numbering of the steps herein is for convenience of illustration and reference only and is not intended to limit the order in which the steps are performed, the particular order of execution being determined by the technology itself, and the skilled artisan can determine various allowable, reasonable orders based on the technology itself.
Those skilled in the art will appreciate that the above-described preferred embodiments can be freely combined and stacked without conflict.
It will be understood that the above-described embodiments are merely illustrative and not restrictive, and that all obvious or equivalent modifications and substitutions to the details given above may be made by those skilled in the art without departing from the underlying principles of the invention, are intended to be included within the scope of the appended claims.
Claims (10)
1. A current source circuit, comprising:
a P-tube current mirror (1) with a power supply input end connected to a power supply (VDD), wherein the P-tube current mirror (1) is used for being mirrored to draw out the power supply so as to provide power to the outside;
an N-tube current mirror (2) connected between the P-tube current mirror (1) and the Ground (GND), wherein the N-tube current mirror (2) and the P-tube current mirror (1) form a current source;
degenerate point switching module (3), comprising: a depletion transistor (MN 4) and a pull-up resistor (R2),
a first pole of the depletion transistor (MN 4) is connected to a bias node of the P-tube current mirror (1), a second pole of the depletion transistor (MN 4) is connected to one end of the pull-up resistor (R2), and the other end of the pull-up resistor (R2) is grounded with a control pole of the depletion transistor (MN 4);
the degeneracy point switching module (3) keeps a normal-on state before a stable output power supply of the current source, when the P-tube current mirror (1) is connected to a power supply (VDD), current flowing out of a bias node of the P-tube current mirror (1) flows through a first pole and a second pole of the depletion transistor (MN 4) so that the potential of one end of the pull-up resistor (R2) is gradually increased, the depletion transistor (MN 4) is disconnected when the potential is increased to the threshold voltage of the depletion transistor (MN 4), and the degeneracy point switching module (3) is disconnected so that the stable state of the current zero point of the current source is switched to the stable state of stable output of the power supply.
2. The current source circuit of claim 1, wherein the P-tube current mirror (1) comprises a first P-type transistor (MP 1) and a third P-type transistor (MP 3), and the N-tube current mirror (2) comprises a first N-type transistor (MN 1) and a third N-type transistor (MN 3), wherein:
-a first pole of the first P-type transistor (MP 1) and a first pole of the third P-type transistor (MP 3) are connected to a power supply (VDD), a control pole of the first P-type transistor (MP 1) is connected to a control pole of the third P-type transistor (MP 3), a control pole of the first P-type transistor (MP 1) is connected to a second pole of the first P-type transistor (MP 1) forming a bias node of the P-tube current mirror (1);
the first pole of the first N-type transistor (MN 1) is connected to the second pole of the first P-type transistor (MP 1), the first pole of the third N-type transistor (MN 3) is connected to the second pole of the third P-type transistor (MP 3), the control pole of the first N-type transistor (MN 1) is connected with the control pole of the third N-type transistor (MN 3), the second pole of the first N-type transistor (MN 1) and the second pole of the third N-type transistor (MN 3) are connected with one end of the pull-up resistor (R2), and the control pole of the third N-type transistor (MN 3) is connected to the first pole of the third N-type transistor (MN 3) to form a bias node of the N-tube current mirror (2).
3. The current source circuit of claim 2, further comprising:
and a first resistor (R1), wherein a second pole of the first N-type transistor (MN 1) is connected with one end of the pull-up resistor (R2) through the first resistor (R1).
4. The current source circuit according to claim 2, wherein,
the aspect ratio of the first P-type transistor (MP 1) and the aspect ratio of the third P-type transistor (MP 3) are equal;
the width-to-length ratio of the first N-type transistor (MN 1) is k times the width-to-length ratio of the third N-type transistor (MN 3), wherein k is a natural number greater than 1.
5. The current source circuit of claim 1, further comprising:
and the gain amplifying circuit is connected between the P-tube current mirror (1) and the N-tube current mirror (2) and is used for increasing the gain of the negative feedback loop.
6. The current source circuit of claim 5, wherein the P-tube current mirror (1) comprises a first P-type transistor (MP 1) and a third P-type transistor (MP 3), the N-tube current mirror (2) comprises a first N-type transistor (MN 1) and a third N-type transistor (MN 3), and the gain amplification circuit comprises a second P-type transistor (MP 2) and a second N-type transistor (MN 2), wherein:
-a first pole of the first P-type transistor (MP 1), -a first pole of the second P-type transistor (MP 2), and-a first pole of the third P-type transistor (MP 3) being connected to a power supply (VDD), -a control pole of the first P-type transistor (MP 1), -a control pole of the second P-type transistor (MP 2) being connected to a control pole of the third P-type transistor (MP 3), -a control pole of the third P-type transistor (MP 3) being connected to a second pole of the third P-type transistor (MP 3) forming a bias node of the P-tube current mirror (1);
the first pole of the first N-type transistor (MN 1) is connected to the second pole of the first P-type transistor (MP 1), the first pole of the second N-type transistor (MN 2) is connected to the second pole of the second P-type transistor (MP 2), the first pole of the third N-type transistor (MN 3) is connected to the second pole of the third P-type transistor (MP 3), the control pole of the first N-type transistor (MN 1) is connected to the control pole of the second N-type transistor (MN 2), the second pole of the first N-type transistor (MN 1), the second pole of the second N-type transistor (MN 2) and the second pole of the third N-type transistor (MN 3) are connected to one end of the pull-up resistor (R2), and the control pole of the third N-type transistor (MN 3) is connected to the first pole of the second N-type transistor (MN 2).
7. The current source circuit of claim 6, wherein the gain amplification circuit further comprises:
and a first capacitor (C1) connected between the control electrode of the third N-type transistor (MN 3) and one end of the pull-up resistor (R2).
8. A low power current source comprising:
a current source circuit according to any of claims 1-7, wherein the P-tube current mirror (1) is realized by a cascode structure.
9. A low power consumption current source chip, characterized in that a current source circuit according to any of claims 1-7 or a low power consumption current source according to claim 8 is integrated thereon.
10. An electronic device with a low power consumption current source, characterized by comprising a current source circuit according to any of claims 1-7 or a low power consumption current source according to claim 8.
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