CN115047930A - Band gap reference circuit - Google Patents

Band gap reference circuit Download PDF

Info

Publication number
CN115047930A
CN115047930A CN202210580109.1A CN202210580109A CN115047930A CN 115047930 A CN115047930 A CN 115047930A CN 202210580109 A CN202210580109 A CN 202210580109A CN 115047930 A CN115047930 A CN 115047930A
Authority
CN
China
Prior art keywords
tube
electrode
pmos tube
drain electrode
pmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202210580109.1A
Other languages
Chinese (zh)
Other versions
CN115047930B (en
Inventor
孙大鹰
朱凯
王冲
顾文华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing University of Science and Technology
Original Assignee
Nanjing University of Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University of Science and Technology filed Critical Nanjing University of Science and Technology
Priority to CN202210580109.1A priority Critical patent/CN115047930B/en
Publication of CN115047930A publication Critical patent/CN115047930A/en
Application granted granted Critical
Publication of CN115047930B publication Critical patent/CN115047930B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

The application provides a band gap reference circuit, includes: a band-gap reference starting circuit and a reference voltage generating circuit; the band-gap reference starting circuit comprises a delay circuit, a low-current turn-off circuit and an ESD protection unit; the band-gap reference voltage generating circuit comprises an operational transconductance amplifier and a reference voltage core circuit. On one hand, the starting circuit can enable the band gap circuit to work normally without an unbalanced working point and can automatically turn off the starting circuit, so that the static power consumption is reduced; on the other hand, the ESD electrostatic protection unit is designed on the circuit, so that electrostatic damage of the device can be effectively prevented, and the working stability and reliability of the circuit are ensured.

Description

Band gap reference circuit
Technical Field
The application relates to the technical field of analog integrated circuits, in particular to a band-gap reference circuit.
Background
With the rapid development of the integration technology, the bandgap reference is widely applied to various integrated circuits such as analog, analog-digital mixing, power management and the like. The whole performance of the chip is directly affected by the design of the band-gap reference, and a high-precision comparator, an A/D converter, a D/A converter and the like need a band-gap reference source to provide stable and accurate reference voltage. Therefore, the improvement of the performance of the band-gap reference source is significant for improving the reliability and stability of system operation.
The starting circuit of the band-gap reference circuit has the advantages that the condition that the branch current of the band-gap reference circuit is in a zero state (degeneracy point) and the output voltage is constantly zero and cannot work normally is avoided. In the prior art, the starting circuit of the bandgap reference circuit still has a part of current loss after the starting is completed, regardless of whether the starting is started by current mirror image or by output voltage feedback control, etc.
Meanwhile, when the bandgap reference circuit works normally, the risk of damage caused by the ESD surge of the external interface cannot be ignored. The damage of electrostatic discharge to the device is immeasurable, and the electrostatic discharge is the potential killer with the largest quality of electronic products, and can cause the device to be seriously damaged and lose functions, so the ESD protection is a ring for improving the working stability and reliability of the circuit. However, it is possible to prevent the occurrence of,
the ESD protection unit is not designed in the band-gap reference circuit.
Disclosure of Invention
The application discloses a band gap reference circuit, which is used for solving the problem of power consumption in the process that the band gap reference circuit gets rid of a point of coincidence and turns off a starting circuit.
The application provides a band-gap reference circuit, which comprises a band-gap reference starting circuit and a reference voltage generating circuit;
the band-gap reference starting circuit comprises a delay circuit, a low-current turn-off circuit and an ESD protection unit;
the band-gap reference voltage generating circuit comprises an operational transconductance amplifier and a reference voltage core circuit;
the time delay circuit is used for generating time delay through current and starting a circuit turn-off signal;
the low-current turn-off circuit is used for turning off a branch circuit on which a turn-off signal comes;
the ESD protection unit is used for protecting a circuit;
the operational transconductance amplifier is used for playing a clamping function;
the reference voltage core circuit is used for generating a voltage with a zero temperature coefficient.
Optionally, the delay circuit includes:
the PMOS transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a first NMOS (N-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a third NMOS transistor;
the source electrode of the first PMOS tube is connected with a power supply, and the grid electrode of the first PMOS tube is connected with the grid electrodes of a ninth PMOS, a tenth PMOS, a fifteenth PMOS and a sixteenth PMOS;
the grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the first NMOS tube is connected with the ground, and the drain electrode of the first NMOS tube is connected with the ground;
the source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrode of the third PMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the third PMOS tube is connected with the power supply, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube;
the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected with the ground, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with the power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube;
the grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS, the source electrode of the third NMOS tube is connected with the ground, and the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS.
Optionally, the low-current turn-off circuit includes:
a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube and a sixth NMOS tube;
the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the grid electrode and the drain electrode of the seventh PMOS tube, the source electrode of the fifth PMOS tube is connected with the power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube;
the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube;
the grid electrode of the seventh PMOS tube is connected with the drain electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube;
the grid electrode of the eighth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the eighth PMOS tube is connected with the drain electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the drain electrode of the fourth NMOS tube;
the grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the fourth NMOS tube is connected with the ground, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is connected with the ground, and the drain electrode of the sixth NMOS tube is connected with the grid electrodes of the first PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube.
Optionally, the ESD protection unit includes:
and the grid electrode of the fifth NMOS tube is connected to the ground, the source electrode of the fifth NMOS tube is connected to the ground, and the drain electrode of the fifth NMOS tube is connected to the drain electrode of the eighth PMOS tube.
Optionally, the operational transconductance amplifier includes:
a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube;
the grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with the power supply, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the seventh NMOS tube;
the grid electrode of the tenth PMOS tube is connected with the grid electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube is connected with the power supply, and the drain electrode of the tenth PMOS tube is connected with the source electrodes of the eleventh PMOS tube and the twelfth PMOS tube;
the grid electrode of the eleventh PMOS tube is connected with the positive end of a third resistor R, the source electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube;
the grid electrode of the twelfth PMOS tube is connected with the negative end of the first resistor R, the source electrode of the twelfth PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the twelfth NMOS;
the grid electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the ninth PMOS tube;
the grid electrode of the eighth NMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is connected with the ground, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the seventh NMOS tube;
the grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the fourteenth PMOS tube and the drain electrode of the thirteenth PMOS tube, the source electrode of the thirteenth PMOS tube is connected with the power supply, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the ninth NMOS tube;
the grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the thirteenth PMOS tube, the source electrode of the fourteenth PMOS tube is connected with the power supply, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the tenth NMOS tube;
the grid electrode of the ninth NMOS tube is connected with the grid electrodes of the seventh NMOS tube and the tenth NMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the thirteenth PMOS tube;
the grid electrode of the tenth NMOS tube is connected with the grid electrode of the ninth NMOS tube, the source electrode of the tenth NMOS tube is connected with the drain electrode of the twelfth NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube;
the grid electrode of the eleventh NMOS tube is connected with the grid electrode of the twelfth NMOS tube, the source electrode of the eleventh NMOS tube is connected with the ground, and the drain electrode of the eleventh NMOS tube is connected with the source electrode of the ninth NMOS;
the grid electrode of the twelfth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, the source electrode of the twelfth NMOS tube is connected with the ground, and the drain electrode of the twelfth NMOS tube is connected with the source electrode of the tenth NMOS tube.
Optionally, the reference voltage core circuit includes:
a fifteenth PMOS tube, a sixteenth PMOS tube and a first resistor R 1 A second resistor R 2 A third resistor R 3 The first triode and the second triode are connected with the first triode;
the grid electrode of the fifteenth PMOS tube is connected with the grid electrode of a sixteenth PMOS tube, the source electrode of the fifteenth PMOS tube is connected with a power supply, and the drain electrode of the fifteenth PMOS tube is connected with the positive end of a first resistor R;
the grid electrode of the sixteenth PMOS tube is connected with the grid electrode of the fifteenth PMOS tube, the source electrode of the sixteenth PMOS tube is connected with the power supply, and the drain electrode of the sixteenth PMOS tube is connected with the positive end of a second resistor R;
the first resistor R 1 The positive end is connected with the drain electrode of the fifteenth PMOS tube, and the first resistor R 1 The negative end of the first triode is connected with the collector of the first triode;
the second resistor R 2 The positive end of the resistor is connected with the drain electrode of a sixteenth PMOS tube, and the second resistor R 2 The negative end of the first resistor is connected with the positive end of a third resistor;
the third resistor R 3 The positive end is connected with a second resistor R 2 Negative terminal, the third resistor R 3 The negative end of the second triode is connected with the collector of the second triode;
the base electrode of the first triode is connected with the base electrode of the second triode, the emitting electrode of the first triode is grounded, and the collecting electrode of the first triode is connected with the negative end of the first resistor;
the base electrode of the second triode is connected with the base electrode of the first triode, the emitting electrode of the second triode is grounded, and the collecting electrode of the second triode is connected with the negative end of the third resistor.
The band-gap reference circuit comprises a band-gap reference starting circuit and a band-gap reference voltage generating circuit, wherein in the band-gap reference starting circuit, if the grid electrode of a first PMOS (P-channel metal oxide semiconductor) tube is at a high level, the band-gap reference circuit is at a merging point, the circuit cannot normally work to output voltage, the first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube are all turned off, a fifth PMOS tube, a sixth PMOS tube and a seventh PMOS tube have resistance characteristics, the grid electrode of a sixth NMOS tube is at a high level, the drain electrode of the sixth NMOS tube is at a low level, at the moment, the grid electrode of the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube, the sixteenth PMOS tube and the first PMOS tube is at a low level, VB is at a high level, the starting circuit is turned off, the band-gap reference circuit is concurrently broken away from the merging point to normally work, the starting circuit is turned off, and the power consumption of the band-gap reference circuit is reduced.
When the input power voltage suddenly generates a large static overshoot, the ESD protection circuit is formed through the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube and the fifth NMOS tube, and the ESD protection circuit is protected through the reverse diode leakage current of the fifth NMOS tube.
Drawings
Fig. 1 is a schematic structural diagram of a bandgap reference circuit provided in an embodiment of the present application;
FIG. 2 is a waveform diagram of an output of a bandgap reference source according to an embodiment of the present application;
fig. 3 is a waveform diagram of a current of a start-up circuit of a bandgap reference source according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the following drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and are not limiting of the application.
Fig. 1 is a schematic diagram of a bandgap reference structure provided in the present application, which can enable a circuit to get rid of a degenerate state and turn off a start circuit, thereby reducing power consumption.
The reference numerals are explained below:
1. the starting circuit comprises a starting circuit 2, an operational transconductance amplifier 3 and a reference voltage core circuit;
in a bandgap reference start-up circuit, P 1 A first PMOS transistor P 2 A second PMOS transistor P 3 A third PMOS transistor P 4 Fourth PMOS transistor, P 5 A fifth PMOS transistor P 6 A sixth PMOS transistor P 7 A seventh PMOS transistor P 8 Eighth PMOS transistor, N 1 A first NMOS transistor, N 2 A second NMOS transistor, N 3 A third NMOS transistor, N 4 A fourth NMOS transistor, N 5 The fifth NMOS tube, N 6 The sixth NMOS tube;
in the transconductance operational amplifier: p is 9 A ninth PMOS transistor P 10 A tenth PMOS transistor, P 11 Eleventh PMOS transistor, P 12 A twelfth PMOS transistor, P 13 Thirteenth PMOS transistor, P 14 Fourteenth PMOS tube, N 7 A seventh NMOS transistor, N 8 An eighth NMOS transistor, N 9 A ninth NMOS transistor, N 10 A tenth NMOS transistor, N 11 Eleventh NMOS transistor, N 12 A twelfth NMOS tube;
in the reference voltage core circuit: p 15 Fifteenth PMOS transistor, P 16 Sixteenth PMOS tube, R 1 A first resistor, R 2 A second resistor, R 3 A third resistor, Q 1 A first triode, Q 2 And a second triode.
Referring specifically to fig. 1, the bandgap reference circuit provided in this embodiment specifically includes: a band-gap reference starting circuit and a reference voltage generating circuit;
the band-gap reference starting circuit comprises a time delay circuit, a low-current turn-off circuit and an ESD protection unit.
The band-gap reference voltage generating circuit comprises an operational transconductance amplifier and a reference voltage core circuit.
The time delay circuit charges the MOSCAP through current to generate time delay, and generates a starting circuit turn-off signal through the inverter group.
The low-current turn-off circuit is used for temporarily turning off a branch circuit where a turn-off signal comes through two MOS switching tubes when the turn-off signal comes.
The ESD protection unit is used for protecting the circuit. Specifically, the situation that the device is damaged due to overlarge current when the reference is suddenly electrified or static electricity is released is avoided through the GGNMOS.
The operational transconductance amplifier is used for playing a clamping function, particularly, a folded cascode structure is adopted to realize a good clamping function of the circuit, and the working stability of the band-gap reference circuit is ensured.
And the reference voltage core circuit is used for generating a voltage with a zero temperature coefficient. Specifically, the voltage with zero temperature coefficient is generated by the structure with the same branch current and different diode proportions and a certain proportion of resistors.
The delay circuit includes:
the PMOS transistor comprises a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a third NMOS transistor.
The source electrode of the first PMOS tube is connected with a power supply, and the grid electrode of the first PMOS tube is connected with the grid electrodes of the ninth PMOS, the tenth PMOS, the fifteenth PMOS and the sixteenth PMOS.
The grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the first NMOS tube is connected with the ground, and the drain electrode of the first NMOS tube is connected with the ground.
The source electrode of the second PMOS tube is connected with the power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube.
The grid electrode of the third PMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the third PMOS tube is connected with the power supply, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube.
The grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected with the ground, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube.
The grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with the power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube.
The grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS, the source electrode of the third NMOS tube is connected with the ground, and the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS.
The low-current turn-off circuit includes:
a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube and a sixth NMOS tube.
The grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the grid electrode and the drain electrode of the seventh PMOS tube, the source electrode of the fifth PMOS tube is connected with the power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube.
The grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube.
The grid electrode of the seventh PMOS tube is connected with the drain electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube.
The grid electrode of the eighth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the eighth PMOS tube is connected with the drain electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the drain electrode of the fourth NMOS tube.
The grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the fourth NMOS tube is connected with the ground, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube.
The grid electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is connected with the ground, and the drain electrode of the sixth NMOS tube is connected with the grid electrodes of the first PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube.
The ESD protection unit includes:
and the grid electrode of the fifth NMOS tube is connected to the ground, the source electrode of the fifth NMOS tube is connected to the ground, and the drain electrode of the fifth NMOS tube is connected to the drain electrode of the eighth PMOS tube.
The operational transconductance amplifier includes:
a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a thirteenth PMOS transistor, a fourteenth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor.
The grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with the power supply, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the seventh NMOS tube.
The grid electrode of the tenth PMOS tube is connected with the grid electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube is connected with the power supply, and the drain electrode of the tenth PMOS tube is connected with the source electrodes of the eleventh PMOS tube and the twelfth PMOS tube.
The grid electrode of the eleventh PMOS tube is connected with the positive end of the third resistor R, the source electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube.
The grid electrode of the twelfth PMOS tube is connected with the negative end of the first resistor R, the source electrode of the twelfth PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the twelfth NMOS.
The grid electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the ninth PMOS tube.
The grid electrode of the eighth NMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is connected with the ground, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the seventh NMOS tube.
The grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the fourteenth PMOS tube and the drain electrode of the thirteenth PMOS tube, the source electrode of the thirteenth PMOS tube is connected with the power supply, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the ninth NMOS tube.
The grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the thirteenth PMOS tube, the source electrode of the fourteenth PMOS tube is connected with the power supply, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the tenth NMOS tube.
The grid electrode of the ninth NMOS tube is connected with the grid electrodes of the seventh NMOS tube and the tenth NMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the thirteenth PMOS tube.
The grid electrode of the tenth NMOS tube is connected with the grid electrode of the ninth NMOS tube, the source electrode of the tenth NMOS tube is connected with the drain electrode of the twelfth NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube.
The grid electrode of the eleventh NMOS tube is connected with the grid electrode of the twelfth NMOS tube, the source electrode of the eleventh NMOS tube is connected with the ground, and the drain electrode of the eleventh NMOS tube is connected with the source electrode of the ninth NMOS.
The grid electrode of the twelfth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, the source electrode of the twelfth NMOS tube is connected with the ground, and the drain electrode of the twelfth NMOS tube is connected with the source electrode of the tenth NMOS tube.
The reference voltage core circuit includes:
a fifteenth PMOS tube, a sixteenth PMOS tube and a first resistor R 1 A second resistor R 2 A third resistor R 3 A first triode and a second triode。
The grid electrode of the fifteenth PMOS tube is connected with the grid electrode of the sixteenth PMOS tube, the source electrode of the fifteenth PMOS tube is connected with the power supply, and the drain electrode of the fifteenth PMOS tube is connected with the positive end of the first resistor R.
The grid electrode of the sixteenth PMOS tube is connected with the grid electrode of the fifteenth PMOS tube, the source electrode of the sixteenth PMOS tube is connected with the power supply, and the drain electrode of the sixteenth PMOS tube is connected with the positive end of the second resistor R.
A first resistor R 1 The positive terminal is connected with the drain electrode of the fifteenth PMOS tube, and a first resistor R 1 The negative end of the second triode is connected with the collector of the first triode.
A second resistor R 2 The positive end is connected with the drain electrode of the sixteenth PMOS tube, and a second resistor R 2 The negative terminal of the third resistor is connected with the positive terminal of the third resistor.
Third resistor R 3 The positive end is connected with a second resistor R 2 Negative terminal, third resistor R 3 The negative end of the second triode is connected with the collector of the second triode.
The base electrode of the first triode is connected with the base electrode of the second triode, the emitting electrode of the first triode is grounded, and the collecting electrode of the first triode is connected with the negative end of the first resistor.
The base electrode of the second triode is connected with the base electrode of the first triode, the emitting electrode of the second triode is grounded, and the collecting electrode of the second triode is connected with the negative end of the third resistor.
As shown in fig. 2, the output reference voltage is about 1.22V.
As shown in fig. 3, the current consumed by the starting circuit is almost zero, so that the starting circuit is truly turned off, and the power consumption is saved.
Further, a first resistor R 1 And a second resistor R 2 The resistance values are the same, and the third resistor R 3 Resistance value and first resistor R 1 A second resistor R 2 Is adjustable so as to be able to adjust the output voltage V BG The range of (1).
Output voltage V of the band-gap reference circuit BG Comprises the following steps:
Figure BDA0003663443610000081
wherein, Δ V BE Is base-emitter voltage of the triode, n is the number proportionality coefficient of the first triode and the second triode, V T ＝26mV@300K，R 1 Is the resistance value of the first resistor, R 2 Is the resistance of the second resistor.
According to the output voltage V BG It can be seen that the output voltage is adjusted by adjusting R 1 、R 2 The temperature coefficient is kept unchanged under the condition that the output voltage is adjustable by changing the size of the triode or adjusting the number of the triodes.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
According to the technical scheme, the beneficial effects of the application are as follows:
the band gap reference circuit comprises a band gap reference starting circuit and a band gap reference voltage generating circuit, wherein in the band gap reference starting circuit, if the grid electrode of a first PMOS (P-channel metal oxide semiconductor) tube is at a high level, the band gap reference circuit is at a merging point, the circuit can not normally work to output voltage, the first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube are all turned off, a fifth PMOS tube, a sixth PMOS tube and a seventh PMOS tube have resistance characteristics, the grid electrode of the sixth NMOS tube is at a high level, the drain electrode of the sixth NMOS tube is at a low level, at the moment, the grid electrode of the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube, the sixteenth PMOS tube and the first PMOS tube is at a low level, VB is at a high level, the starting circuit is turned off, the band gap reference circuit can break away from the merging point to normally work, the starting circuit is turned off, and the power consumption of the band gap reference circuit is reduced.
When the input power voltage suddenly generates a large static overshoot, the ESD protection circuit is formed through the fifth PMOS tube, the sixth PMOS tube, the seventh PMOS tube and the fifth NMOS tube, and the ESD protection circuit is protected through the reverse diode leakage current of the fifth NMOS tube.

Claims (6)

1. The band-gap reference circuit is characterized by comprising a band-gap reference starting circuit and a reference voltage generating circuit;
the band-gap reference starting circuit comprises a delay circuit, a low-current turn-off circuit and an ESD protection unit;
the band-gap reference voltage generating circuit comprises an operational transconductance amplifier and a reference voltage core circuit;
the time delay circuit is used for generating time delay through current and starting a circuit turn-off signal;
the low-current turn-off circuit is used for turning off a branch circuit on which a turn-off signal comes;
the ESD protection unit is used for protecting a circuit;
the operational transconductance amplifier is used for playing a clamping function;
the reference voltage core circuit is used for generating a voltage with a zero temperature coefficient.
2. The bandgap reference circuit of claim 1, wherein the delay circuit comprises:
the PMOS transistor comprises a first PMOS (P-channel metal oxide semiconductor) transistor, a first NMOS (N-channel metal oxide semiconductor) transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor and a third NMOS transistor;
the source electrode of the first PMOS tube is connected with a power supply, and the grid electrode of the first PMOS tube is connected with the grid electrodes of a ninth PMOS, a tenth PMOS, a fifteenth PMOS and a sixteenth PMOS;
the grid electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube, the source electrode of the first NMOS tube is connected with the ground, and the drain electrode of the first NMOS tube is connected with the ground;
the source electrode of the second PMOS tube is connected with a power supply, the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the second PMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrode of the third PMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the third PMOS tube is connected with the power supply, and the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube;
the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the second NMOS tube is connected with the ground, and the drain electrode of the second NMOS tube is connected with the drain electrode of the third PMOS tube;
the grid electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with the power supply, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube;
the grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS, the source electrode of the third NMOS tube is connected with the ground, and the drain electrode of the third NMOS tube is connected with the drain electrode of the fourth PMOS.
3. The bandgap reference circuit of claim 1, wherein the low current turn-off circuit comprises:
a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a fourth NMOS tube and a sixth NMOS tube;
the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the grid electrode and the drain electrode of the seventh PMOS tube, the source electrode of the fifth PMOS tube is connected with the power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube;
the grid electrode of the sixth PMOS tube is connected with the grid electrode of the seventh PMOS tube, the source electrode of the sixth PMOS tube is connected with the drain electrode of the fifth PMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube;
the grid electrode of the seventh PMOS tube is connected with the drain electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube, and the drain electrode of the seventh PMOS tube is connected with the source electrode of the eighth PMOS tube;
the grid electrode of the eighth PMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the eighth PMOS tube is connected with the drain electrode of the seventh PMOS tube, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifth NMOS tube and the drain electrode of the fourth NMOS tube;
the grid electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube, the source electrode of the fourth NMOS tube is connected with the ground, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube;
the grid electrode of the sixth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the sixth NMOS tube is connected with the ground, and the drain electrode of the sixth NMOS tube is connected with the grid electrodes of the first PMOS tube, the ninth PMOS tube, the tenth PMOS tube, the fifteenth PMOS tube and the sixteenth PMOS tube.
4. The bandgap reference circuit of claim 1, wherein the ESD protection unit comprises:
and the grid electrode of the fifth NMOS tube is connected to the ground, the source electrode of the fifth NMOS tube is connected to the ground, and the drain electrode of the fifth NMOS tube is connected to the drain electrode of the eighth PMOS tube.
5. The bandgap reference circuit of claim 1, wherein the operational transconductance amplifier comprises:
a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventh NMOS tube, an eighth NMOS tube, a thirteenth PMOS tube, a fourteenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a twelfth NMOS tube;
the grid electrode of the ninth PMOS tube is connected with the grid electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with the power supply, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the seventh NMOS tube;
the grid electrode of the tenth PMOS tube is connected with the grid electrode of the ninth PMOS tube, the source electrode of the tenth PMOS tube is connected with the power supply, and the drain electrode of the tenth PMOS tube is connected with the source electrodes of the eleventh PMOS tube and the twelfth PMOS tube;
the grid electrode of the eleventh PMOS tube is connected with the positive end of a third resistor R, the source electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube;
the grid electrode of the twelfth PMOS tube is connected with the negative end of the first resistor R, the source electrode of the twelfth PMOS tube is connected with the drain electrode of the tenth PMOS tube, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the twelfth NMOS;
the grid electrode of the seventh NMOS tube is connected with the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the drain electrode of the seventh NMOS tube is connected with the drain electrode of the ninth PMOS tube;
the grid electrode of the eighth NMOS tube is connected with the drain electrode of the eighth NMOS tube, the source electrode of the eighth NMOS tube is connected with the ground, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the seventh NMOS tube;
the grid electrode of the thirteenth PMOS tube is connected with the grid electrode of the fourteenth PMOS tube and the drain electrode of the thirteenth PMOS tube, the source electrode of the thirteenth PMOS tube is connected with the power supply, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the ninth NMOS tube;
the grid electrode of the fourteenth PMOS tube is connected with the grid electrode of the thirteenth PMOS tube, the source electrode of the fourteenth PMOS tube is connected with the power supply, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the tenth NMOS tube;
the grid electrode of the ninth NMOS tube is connected with the grid electrodes of the seventh NMOS tube and the tenth NMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the thirteenth PMOS tube;
the grid electrode of the tenth NMOS tube is connected with the grid electrode of the ninth NMOS tube, the source electrode of the tenth NMOS tube is connected with the drain electrode of the twelfth NMOS tube, and the drain electrode of the tenth NMOS tube is connected with the drain electrode of the fourteenth PMOS tube;
the grid electrode of the eleventh NMOS tube is connected with the grid electrode of the twelfth NMOS tube, the source electrode of the eleventh NMOS tube is connected with the ground, and the drain electrode of the eleventh NMOS tube is connected with the source electrode of the ninth NMOS;
the grid electrode of the twelfth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, the source electrode of the twelfth NMOS tube is connected with the ground, and the drain electrode of the twelfth NMOS tube is connected with the source electrode of the tenth NMOS tube.
6. The bandgap reference circuit according to claim 1, wherein the reference voltage core circuit comprises:
a fifteenth PMOS tube, a sixteenth PMOS tube and a first resistor R 1 A second resistor R 2 A third resistor R 3 The first triode and the second triode are connected with the first triode;
the grid electrode of the fifteenth PMOS tube is connected with the grid electrode of a sixteenth PMOS tube, the source electrode of the fifteenth PMOS tube is connected with a power supply, and the drain electrode of the fifteenth PMOS tube is connected with the positive end of a first resistor R;
the grid electrode of the sixteenth PMOS tube is connected with the grid electrode of the fifteenth PMOS tube, the source electrode of the sixteenth PMOS tube is connected with the power supply, and the drain electrode of the sixteenth PMOS tube is connected with the positive end of the second resistor R;
the first resistor R 1 The positive end is connected with the drain electrode of the fifteenth PMOS tube, and the first resistor R 1 The negative end of the first triode is connected with the collector of the first triode;
the second resistor R 2 The positive end is connected with the drain electrode of the sixteenth PMOS tube, and the second resistor R 2 The negative end of the third resistor is connected with the positive end of a third resistor;
the third resistor R 3 The positive end is connected with a second resistor R 2 Negative terminal, the third resistor R 3 The negative end of the second triode is connected with the collector of the second triode;
the base electrode of the first triode is connected with the base electrode of the second triode, the emitting electrode of the first triode is grounded, and the collecting electrode of the first triode is connected with the negative end of the first resistor;
the base electrode of the second triode is connected with the base electrode of the first triode, the emitting electrode of the second triode is grounded, and the collecting electrode of the second triode is connected with the negative end of the third resistor.
CN202210580109.1A 2022-05-26 2022-05-26 Band gap reference circuit Active CN115047930B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210580109.1A CN115047930B (en) 2022-05-26 2022-05-26 Band gap reference circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210580109.1A CN115047930B (en) 2022-05-26 2022-05-26 Band gap reference circuit

Publications (2)

Publication Number Publication Date
CN115047930A true CN115047930A (en) 2022-09-13
CN115047930B CN115047930B (en) 2024-05-17

Family

ID=83158998

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210580109.1A Active CN115047930B (en) 2022-05-26 2022-05-26 Band gap reference circuit

Country Status (1)

Country Link
CN (1) CN115047930B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180640A (en) * 2005-12-27 2007-07-12 Seiko Epson Corp Voltage generation circuit, regulator circuit, and integrated circuit device
CN103001200A (en) * 2012-12-14 2013-03-27 北京大学 Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit
KR20190068952A (en) * 2017-12-11 2019-06-19 단국대학교 산학협력단 Band-Gap Reference Circuit
CN110703841A (en) * 2019-10-29 2020-01-17 湖南国科微电子股份有限公司 Starting circuit of band-gap reference source, band-gap reference source and starting method
CN113985957A (en) * 2021-12-27 2022-01-28 唯捷创芯(天津)电子技术股份有限公司 Overshoot-free quick-start band gap reference circuit, chip and electronic equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007180640A (en) * 2005-12-27 2007-07-12 Seiko Epson Corp Voltage generation circuit, regulator circuit, and integrated circuit device
CN103001200A (en) * 2012-12-14 2013-03-27 北京大学 Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit
KR20190068952A (en) * 2017-12-11 2019-06-19 단국대학교 산학협력단 Band-Gap Reference Circuit
CN110703841A (en) * 2019-10-29 2020-01-17 湖南国科微电子股份有限公司 Starting circuit of band-gap reference source, band-gap reference source and starting method
CN113985957A (en) * 2021-12-27 2022-01-28 唯捷创芯(天津)电子技术股份有限公司 Overshoot-free quick-start band gap reference circuit, chip and electronic equipment

Also Published As

Publication number Publication date
CN115047930B (en) 2024-05-17

Similar Documents

Publication Publication Date Title
CN110362144B (en) Low-temperature drift high-power-supply rejection-ratio band-gap reference circuit based on exponential compensation
US20090268360A1 (en) Protection circuit
JP2597941B2 (en) Reference circuit and control method of output current
CN110320954B (en) Low-temperature drift band gap reference circuit based on concave-convex curvature compensation
WO2020156588A1 (en) Voltage reference circuit and low-power-consumption power source system
CN111045470B (en) Band-gap reference circuit with low offset voltage and high power supply rejection ratio
US20220413539A1 (en) Low noise bandgap reference architecture
CN115903985A (en) Current limiting circuit suitable for LDO circuit with wide input voltage range
JPS6326895B2 (en)
TWI716323B (en) Voltage generator
CN105867499A (en) Circuit and method for achieving low pressure and high precision of reference voltage source
CN115047930A (en) Band gap reference circuit
CN111427406B (en) Band gap reference circuit
WO2022110734A1 (en) Voltage generation module and power supply management chip
CN112649657B (en) Undervoltage indicating system
CN214253044U (en) Current source circuit and electronic equipment
CN111198588B (en) Band-gap reference circuit
CN114356016A (en) Low-power-consumption CMOS ultra-wide temperature range transient enhanced LDO circuit
CN114489222A (en) Band-gap reference circuit for power supply chip
CN112181042A (en) Negative voltage reference circuit suitable for wide voltage range
CN112306142A (en) Negative voltage reference circuit
CN101907901A (en) Band gap circuit
US6396319B2 (en) Semiconductor integrated circuit with quick charging/discharging circuit
CN113126688A (en) Reference generation circuit for inhibiting overshoot
CN115576383B (en) Band gap reference circuit and band gap reference chip

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant