CN112649657B - Undervoltage indicating system - Google Patents
Undervoltage indicating system Download PDFInfo
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- CN112649657B CN112649657B CN202011337904.5A CN202011337904A CN112649657B CN 112649657 B CN112649657 B CN 112649657B CN 202011337904 A CN202011337904 A CN 202011337904A CN 112649657 B CN112649657 B CN 112649657B
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- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
- G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
- G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
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Abstract
The invention is suitable for the technical field of integrated circuits, and provides an undervoltage indicating system, which comprises a voltage bias circuit, a band gap reference circuit, a starting circuit and an undervoltage indicating circuit, wherein the starting circuit is connected with the voltage bias circuit; the under-voltage indicating circuit collects a second starting voltage output signal of the starting circuit through a second starting voltage output signal end and outputs an under-voltage indicating output signal; when the undervoltage indication output signal is at a low level, the rear-stage circuit works normally, and when the undervoltage indication output signal is overturned from the low level to a high level, the rear-stage circuit is switched off. The invention can multiplex the starting circuit, realize the under-voltage indication function of the reference voltage output by the band-gap reference circuit, protect the post-stage circuit, and has simple circuit structure and low design complexity.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an undervoltage indicating system.
Background
The voltage reference circuit is a basic module of the integrated circuit and provides reference voltage for other modules in the integrated circuit. The bandgap reference circuit is a voltage reference circuit that is most widely used because of its advantages such as high precision and high stability.
In an integrated circuit, a reference voltage output by a bandgap reference circuit is often used to provide a voltage reference for other modules of the circuit, so as to ensure the normal operation of the whole circuit. However, if the reference voltage output by the bandgap reference circuit is in an abnormal operating state, the bandgap reference circuit cannot achieve a correct function, and cannot provide a correct voltage reference, so that the subsequent circuit using the reference voltage cannot operate normally.
Disclosure of Invention
The invention mainly aims to provide an undervoltage indicating system to solve the problems that in the prior art, a reference voltage output by a band-gap reference circuit is in an abnormal working state, a correct voltage reference cannot be provided, and a subsequent circuit using the reference voltage cannot work normally.
In order to achieve the above object, a first aspect of the embodiments of the present invention provides an under-voltage indication system, which includes a voltage bias circuit, a bandgap reference circuit, a start-up circuit, and an under-voltage indication circuit;
the voltage bias circuit comprises a bias voltage input signal end and a bias voltage output signal end;
the band-gap reference circuit comprises a first reference voltage input signal end, a second reference voltage input signal end, a reference voltage output signal end and a reference voltage output signal end;
the starting circuit comprises a starting voltage input signal end, a first starting voltage output signal end and a second starting voltage output signal end;
the undervoltage indicating circuit comprises an undervoltage indicating input signal end and an undervoltage indicating output signal end;
the bias voltage output signal end is connected with the first reference voltage input signal end, the bias voltage input signal end is connected with the reference voltage output signal end and is connected with the starting voltage input signal end, the first starting voltage output signal end is connected with the second reference voltage input signal end, the second starting voltage output signal end is connected with the under-voltage indication input signal end, and the under-voltage indication output signal end is connected with a rear-stage circuit; the reference voltage output signal end is connected with the rear-stage circuit and provides a reference voltage signal for the rear-stage circuit;
the undervoltage indicating circuit collects a second starting voltage output signal of the starting circuit through the second starting voltage output signal end and outputs an undervoltage indicating output signal;
when the undervoltage indication output signal is at a low level, the rear-stage circuit works normally, and when the undervoltage indication output signal is overturned from the low level to a high level, the rear-stage circuit is turned off.
With reference to the first aspect of the present invention, in the first embodiment of the present invention, the voltage bias circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor;
the source electrode of the first MOS tube is connected with a power supply, and the grid electrode and the drain electrode of the first MOS tube are connected with each other and then connected with the source electrode of the second MOS tube; the grid electrode and the drain electrode of the second MOS tube are connected with each other and then are connected with the drain electrode of the third MOS tube, and the grid electrode and the drain electrode of the second MOS tube are also used as the bias voltage output signal end and are connected with the first reference voltage input signal end of the band-gap reference circuit after being connected with each other;
the source electrode of the third MOS tube is grounded, and the grid electrode of the third MOS tube is connected with the grid electrode and the drain electrode of the fifth MOS tube and is connected with the drain electrode of the fourth MOS tube; the source electrode of the fifth MOS tube is grounded; and the source electrode of the fourth MOS tube is connected with a power supply, and the grid electrode of the fourth MOS tube is used as the bias voltage input signal end and is connected with the reference voltage output signal end of the band-gap reference circuit.
With reference to the first aspect of the present invention, in a second implementation manner of the present invention, the under-voltage indication circuit includes a first resistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor;
one end of the first resistor is connected with a power supply, and the other end of the first resistor is connected with the grid electrode and the drain electrode of the sixth MOS tube and the grid electrode of the eighth MOS tube; the source electrode of the sixth MOS tube and the source electrode of the eighth MOS tube are grounded; the drain electrode of the eighth MOS tube is connected with the drain electrode of the seventh MOS tube, and the source electrode of the seventh MOS tube is connected with a power supply;
the drain electrode of the eighth MOS tube is connected with the drain electrode of the seventh MOS tube and then is used as the under-voltage indication output signal end; and the grid electrode of the seventh MOS tube is used as the under-voltage indication input signal end and is connected with the second starting voltage output signal end of the starting circuit.
With reference to the first aspect of the present invention, in a third implementation manner of the present invention, the starting circuit includes a second resistor, a ninth MOS transistor, and a tenth MOS transistor.
The source electrode of the ninth MOS tube is connected with a power supply, the grid electrode of the ninth MOS tube is connected with the drain electrode of the tenth MOS tube and one end of the second resistor, the other end of the second resistor is grounded, and the source electrode of the tenth MOS tube is connected with the power supply;
the grid electrode of the tenth MOS tube is used as the starting voltage input signal end and is connected with the reference voltage output signal end of the band-gap reference circuit;
and the grid electrode of the ninth MOS tube is used as the second starting voltage output signal end and is connected with the under-voltage indication input signal end of the under-voltage indication circuit, and the drain electrode of the ninth MOS tube is used as the first starting voltage output signal end and is connected with the second reference voltage input signal end of the band-gap reference circuit.
In a fourth embodiment of the present invention with reference to the first aspect of the present invention, the bandgap reference circuit includes a third resistor, a fourth resistor, a fifth resistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a first triode, a second triode, a third triode, a fourth triode, a fifth triode, and a sixth triode;
the source electrode of the eleventh MOS tube is connected with a power supply, and after the grid electrode and the drain electrode of the eleventh MOS tube are connected with each other, the source electrode of the eleventh MOS tube is connected with the drain electrode of the twelfth MOS tube, the grid electrode of the thirteenth MOS tube and the grid electrode of the fifteenth MOS tube, and after the connection, the source electrode of the eleventh MOS tube is used as the reference voltage output signal end, is connected with the bias voltage input signal end of the voltage bias circuit and is connected with the starting voltage input signal end of the starting circuit; a grid electrode of the twelfth MOS tube is connected with a drain electrode of the fifteenth MOS tube, an emitting electrode of the third triode and a base electrode of the fourth triode, is used as the second reference voltage input signal end after being connected, and is connected with a first starting voltage output signal end of the starting circuit;
the source electrode of the twelfth MOS tube is connected with the collector electrode of the first triode; the source electrode of the thirteenth MOS tube and the source electrode of the fifteenth MOS tube are connected with a power supply, and the drain electrode of the thirteenth MOS tube is connected with the source electrode of the fourteenth MOS tube;
a grid electrode of the fourteenth MOS tube is used as the first reference voltage input signal end and is connected with a bias voltage output signal end of the voltage bias circuit;
the drain electrode of the fourteenth MOS tube is connected with the collector electrode of the second triode and the base electrode of the third triode; the emitter of the first triode is grounded, and the base of the first triode is connected with one end of the third resistor and the collector and the base of the fifth triode; an emitting electrode of the second triode is grounded, and a base electrode of the second triode is connected with one end of the fourth resistor and a collector electrode of the sixth triode; the collector of the third triode is grounded; a collector of the fourth triode is connected with a power supply, and an emitter of the fourth triode is connected with the other end of the third resistor and the other end of the fourth resistor, is used as the reference voltage output signal end and provides a reference voltage signal for a post-stage circuit;
an emitter of the fifth triode is grounded; and an emitter of the sixth triode is connected with one end of the fifth resistor, and the other end of the fifth resistor is grounded.
With reference to the fourth embodiment of the first aspect of the present invention, in a fifth embodiment of the present invention, the third resistor and the fourth resistor have the same resistance value; the emitter areas of the fifth triode and the first triode are equal; the area ratio of the emitting electrodes of the fifth triode and the sixth triode is 1: 8.
With reference to the fifth implementation manner of the first aspect of the present invention, in a sixth implementation manner, before the under-voltage indication circuit acquires the second start-up voltage output signal of the start-up circuit through the second start-up voltage output signal terminal and outputs the under-voltage indication output signal, the under-voltage indication circuit includes:
and adjusting circuit parameters to set the critical voltage value of the undervoltage indication output signal, which is turned from low level to high level.
With reference to the sixth implementation manner of the first aspect of the present invention, in the seventh implementation manner of the present invention, the circuit parameter includes at least one of a ratio of a width-to-length ratio of the tenth MOS transistor to the eleventh MOS transistor, a ratio of a width-to-length ratio of the sixth MOS transistor to the eighth MOS transistor, a resistance value of the first resistor, and a resistance value of the second resistor.
The embodiment of the invention provides an undervoltage indicating system, which comprises a voltage bias circuit, a band-gap reference circuit, a starting circuit and an undervoltage indicating circuit, wherein the undervoltage indicating circuit collects a second starting voltage output signal of the starting circuit through a second starting voltage output signal end and outputs an undervoltage indicating output signal.
Drawings
Fig. 1 is a schematic structural diagram of an undervoltage indication system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a detailed structure of the under-voltage indication system according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Suffixes such as "module", "part", or "unit" used to denote elements are used herein only for the convenience of description of the present invention, and have no specific meaning in themselves. Thus, "module" and "component" may be used in a mixture.
As shown in fig. 1, an under-voltage indication system 100 according to an embodiment of the present invention includes a voltage bias circuit 10, a bandgap reference circuit 20, a start-up circuit 30, and an under-voltage indication circuit 40.
In the embodiment of the present invention, the voltage bias circuit 10, the bandgap reference circuit 20, the start-up circuit 30 and the under-voltage indication circuit 40 are connected in sequence, and the voltage signal transmission relationship will be described in detail below.
In the embodiment of the present invention, the voltage bias circuit 10 includes a bias voltage input signal terminal 11 and a bias voltage output signal terminal 12. The bandgap reference circuit 20 includes a first reference voltage input signal terminal 21, a second reference voltage input signal terminal 22, a reference voltage output signal terminal 23 and a reference voltage output signal terminal 24. The start-up circuit 30 includes a start-up voltage input signal terminal 31, a first start-up voltage output signal terminal 32, and a second start-up voltage output signal terminal 33. Brown-out indication circuit 40 includes a brown-out indication input signal terminal 41 and a brown-out indication output signal terminal 42.
Based on this, in the embodiment of the present invention, the voltage signal transmission relationship of each circuit is:
the bias voltage output signal terminal 12 is connected to the first reference voltage input signal terminal 21, the bias voltage input signal terminal 11 is connected to the reference voltage output signal terminal 23 and to the start voltage input signal terminal 31, the first start voltage output signal terminal 32 is connected to the second reference voltage input signal terminal 22, the second start voltage output signal terminal 33 is connected to the under-voltage indication input signal terminal 41, and the under-voltage indication output signal terminal 42 is connected to the post-stage circuit. The reference voltage output signal terminal 24 is connected to the subsequent stage circuit and provides a reference voltage signal, which is labeled as VREF in fig. 1, to the subsequent stage circuit.
In a specific application, the under-voltage indication principle of the under-voltage indication circuit 40 is as follows:
when the undervoltage indication output signal is at a low level, the rear-stage circuit works normally, and when the undervoltage indication output signal is overturned from the low level to a high level, the rear-stage circuit is switched off.
It can be seen that the brown-out indication system 100 according to the embodiment of the present invention multiplexes the start-up circuit 30, and in detail, the first reference voltage input signal terminal 21 and the second reference voltage input signal terminal 22 of the bandgap reference circuit 20 use the first start-up voltage output signal of the start-up circuit 30 and the bias voltage output signal of the voltage bias circuit 10 to output the reference voltage output signal and the reference voltage output signal, where the reference voltage output signal is a reference voltage signal used by a subsequent circuit, and the reference voltage output signal is applied to the start-up circuit 30 and the voltage bias circuit 10. Then, the start-up circuit 30 outputs a second start-up voltage output signal according to the reference voltage output signal, and informs the undervoltage indication module 40 connected thereto whether the bandgap reference circuit 20 has undervoltage condition, i.e. whether the reference voltage output signal is normal. Finally, the undervoltage indication circuit 40 outputs an undervoltage indication output signal according to whether the bandgap reference circuit 20 is undervoltage or not, and determines whether to turn off the subsequent circuit or not.
As shown in fig. 2, the embodiment of the present invention further shows detailed circuit structures of the voltage bias circuit 10, the bandgap reference circuit 20, the start-up circuit 30, and the under-voltage indication circuit 40, and circuit connection relationships thereof.
In the embodiment of the present invention, the voltage bias circuit 10 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, and a fifth MOS transistor M5.
In fig. 2, the source of the first MOS transistor M1 is connected to the power supply VDD, and the gate and the drain of the first MOS transistor M1 are connected to each other and then connected to the source of the second MOS transistor M2; the grid electrode and the drain electrode of the second MOS transistor M2 are connected with each other and then connected with the drain electrode of the third MOS transistor M3, and the grid electrode and the drain electrode of the second MOS transistor M2 are connected with each other and then used as a bias voltage output signal terminal 12 and connected with a first reference voltage input signal terminal 21 of the band gap reference circuit 20; the source electrode of the third MOS transistor M3 is grounded GND, and the gate electrode of the third MOS transistor M3 is connected with the gate electrode and the drain electrode of the fifth MOS transistor M5 and the drain electrode of the fourth MOS transistor M4; the source electrode of the fifth MOS tube M5 is grounded GND; the source of the fourth MOS transistor M4 is connected to the power supply VDD, and the gate of the fourth MOS transistor M4 is connected to the reference voltage output signal terminal 23 of the bandgap reference circuit 20 as the bias voltage input signal terminal 11.
In the embodiment of the present invention, the undervoltage indication circuit 40 includes a first resistor R1, a sixth MOS transistor M6, a seventh MOS transistor M7, and an eighth MOS transistor M8.
In fig. 2, one end of the first resistor R1 is connected to the power supply VDD, and the other end is connected to the gate and the drain of the sixth MOS transistor M6 and the gate of the eighth MOS transistor M8; the source electrode of the sixth MOS transistor M6 and the source electrode of the eighth MOS transistor M8 are grounded GND; the drain electrode of the eighth MOS transistor M8 is connected to the drain electrode of the seventh MOS transistor M7, and the source electrode of the seventh MOS transistor M7 is connected to the power supply VDD; after the drain of the eighth MOS transistor M8 is connected to the drain of the seventh MOS transistor M7, it serves as an under-voltage indication output signal terminal 42 for outputting an under-voltage indication output signal, which is marked as vrefak in fig. 2; the gate of the seventh MOS transistor M7 is connected to the second start-up voltage output signal terminal 33 of the start-up circuit 30 as the under-voltage indication input signal terminal 41.
In the embodiment of the present invention, the starting circuit 30 includes a second resistor R2, a ninth MOS transistor M9 and a tenth MOS transistor M10.
In fig. 2, the source of the ninth MOS transistor M9 is connected to the power supply VDD, the gate of the ninth MOS transistor M9 is connected to the drain of the tenth MOS transistor M10 and one end of the second resistor R2, the other end of the second resistor R2 is grounded to GND, and the source of the tenth MOS transistor M10 is connected to the power supply VDD; the gate of the tenth MOS transistor M10 is used as the start voltage input signal terminal 31 and is connected to the reference voltage output signal terminal 23 of the bandgap reference circuit 20; the gate of the ninth MOS transistor M9 is connected to the under-voltage indication input signal terminal 41 of the under-voltage indication circuit 40 as the second start-up voltage output signal terminal 32, and the drain of the ninth MOS transistor M9 is connected to the second reference voltage input signal terminal 22 of the bandgap reference circuit 20 as the first start-up voltage output signal terminal 32.
In the embodiment of the present invention, the bandgap reference circuit 20 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a first triode Q1, a second triode Q2, a third triode Q3, a fourth triode Q4, a fifth triode Q5, and a sixth triode Q6;
in fig. 2, the source of the eleventh MOS transistor M11 is connected to the power supply VDD, and the gate and the drain of the eleventh MOS transistor M11 are connected to each other, and then the drain of the twelfth MOS transistor M12, the gate of the thirteenth MOS transistor M13 and the gate of the fifteenth MOS transistor M15 are connected to each other, and connected to each other as the reference voltage output signal terminal 23, and connected to the bias voltage input signal terminal 11 of the voltage bias circuit 10 and to the start voltage input signal terminal 31 of the start circuit 30;
the gate of the twelfth MOS transistor M12 is connected to the drain of the fifteenth MOS transistor M15, the emitter of the third transistor Q3, and the base of the fourth transistor, and is connected to serve as a second reference voltage input signal terminal and connected to the first start voltage output signal terminal 32 of the start circuit 30;
the source electrode of the twelfth MOS tube M12 is connected with the collector electrode of the first triode Q1; the source electrode of the thirteenth MOS tube M13 and the source electrode of the fifteenth MOS tube M15 are connected with a power supply VDD, and the drain electrode of the thirteenth MOS tube M13 is connected with the source electrode of the fourteenth MOS tube M14;
the gate of the fourteenth MOS transistor M14 is used as the first reference voltage input signal terminal 21, and is connected to the bias voltage output signal terminal 12 of the voltage bias circuit 10;
the drain electrode of the fourteenth MOS tube M14 is connected with the collector electrode of the second triode Q2 and the base electrode of the third triode Q3; an emitter of the first triode Q1 is grounded GND, and a base of the first triode Q1 is connected with one end of the third resistor R3 and a collector and a base of the fifth triode Q5; an emitter of the second triode Q2 is grounded GND, and a base of the second triode Q2 is connected with one end of the fourth resistor R4 and a collector of the sixth triode Q5; the collector of the third triode Q3 is grounded GND; the collector of the fourth transistor Q4 is connected to the power supply VDD, and the emitter of the fourth transistor Q4 is connected to the other end of the third resistor R3 and the other end of the fourth resistor R4, and serves as a reference voltage output signal terminal 24 for providing a reference voltage signal VREF for the subsequent circuit.
The reference voltage signal VREF is a reference voltage used by the subsequent circuit.
The emitter of the fifth triode Q5 is grounded GND; an emitter of the sixth transistor Q6 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is grounded to GND.
In the embodiment of the present invention, the resistance values of the third resistor R3 and the fourth resistor R4 are equal; the emitter area ratio of the fifth transistor Q5 to the sixth transistor Q6 is 1: 8.
In a specific application, the critical voltage value at which the under-voltage indication output signal of the under-voltage indication circuit 40 is inverted from the low level to the high level may be set by circuit parameters, and in this embodiment of the present invention, the acquiring, by the under-voltage indication circuit 40, the second start-up voltage output signal of the start-up circuit 30 by the second start-up voltage output signal terminal 33 includes:
and adjusting circuit parameters to set the critical voltage value of the undervoltage indication output signal, which is inverted from low level to high level. The circuit parameters include at least one of the ratio of the width-to-length ratio of the tenth MOS transistor M10 to the eleventh MOS transistor M11, the ratio of the width-to-length ratio of the sixth MOS transistor M6 to the eighth MOS transistor M8, the resistance value of the first resistor R1, and the resistance value of the second resistor R2.
Based on the detailed structure of the undervoltage indication system shown in fig. 2, in the undervoltage indication system shown in fig. 1, the bias voltage input signal terminal 11 of the voltage bias circuit 10 is a gate of the fourth MOS transistor M4 in fig. 2, and the bias voltage output signal terminal 12 is an output terminal after the gate and the drain of the second MOS transistor M2 in fig. 2 are connected;
the first reference voltage input signal terminal 21 of the bandgap reference circuit 20 is a gate of a fourteenth MOS transistor M14 in fig. 2, the second reference voltage input signal terminal 22 is an input terminal to which a gate of a twelfth MOS transistor M12, an emitter of a third transistor Q3, a base of a fourth transistor Q4, and a drain of a fifteenth MOS transistor M15 in fig. 2 are connected, and the reference voltage output signal terminal 23 is an output terminal to which a gate and a drain of an eleventh MOS transistor M12, a drain of a twelfth MOS transistor M12, a gate of a thirteenth MOS transistor M13, and a gate of a fifteenth MOS transistor M15 in fig. 2 are connected.
The start-up voltage input signal terminal 31 of the start-up circuit 30 is the gate of the tenth MOS transistor M10 in fig. 2, the first start-up voltage output signal terminal 32 is the drain of the ninth MOS transistor M9 in fig. 2, and the second start-up voltage output signal terminal 33 is the output terminal of the ninth MOS transistor M9 in fig. 2, in which the gate of the M10, and one end of the R2 are connected.
The under-voltage indication input signal terminal 41 of the under-voltage indication circuit 40 is a gate of the seventh MOS transistor M7 in fig. 2, and the under-voltage indication output signal terminal 42 is an output terminal of the seventh MOS transistor M7 and the eighth MOS transistor M8 in fig. 2 after being connected to each other.
In the embodiment of the present invention, a detailed structure of the undervoltage indication system shown in fig. 2 is further combined to further explain an implementation principle of the undervoltage indication system provided in the embodiment of the present invention:
in the embodiment of the present invention, the third resistor R3, the fourth resistor R4, the fifth resistor R5, the fifth transistor Q5, and the sixth transistor Q6 form a core circuit of the bandgap reference circuit 20, the third resistor R3 and the fourth resistor R4 have equal resistance values, and the emitter area ratio of the fifth transistor Q5 and the sixth transistor Q6 is set to 1:8, so the reference voltage signal VREF in the bandgap reference circuit is represented as:
wherein, VBE5Is the BE junction voltage of the fifth transistor Q5; vTIs a thermal voltage; r3、R5The resistance values of the third resistor R3 and the fifth resistor R5 are respectively.
In practical applications, the influence of the base current is negligible, so the collector currents of the fifth transistor Q5 and the sixth transistor Q6 are equal, and since the emitter areas of the fifth transistor Q5 and the first transistor Q1 are equal in the embodiment of the present invention, the collector currents of the fifth transistor Q5 and the first transistor Q1 are also equal, which is expressed by the formula:
IC(Q1)＝IC(Q5)＝IC(Q6) (2)
wherein, IC(Q1)、IC(Q5)、IC(Q6)Which are the collector currents of the first transistor Q1, the fifth transistor Q5, and the sixth transistor Q6, respectively.
As shown in fig. 2, in the bandgap reference circuit 20, the drain current of the eleventh MOS transistor M11 is equal to the collector current of the first transistor Q1, and in the embodiment of the present invention, the ratio of the width to length of the tenth MOS transistor M10 to the eleventh MOS transistor M11 is M, which can be expressed by the following formula:
wherein, ID(M10)、ID(M11)Drain currents of the tenth MOS transistor M10 and the eleventh MOS transistor M11, respectively.
The first MOS transistor M1 to the fifth MOS transistor M5 form a voltage bias circuit 10, and are used for providing a voltage to the gate of the fourteenth MOS transistor M14 of the bandgap reference circuit 20. The fourth MOS transistor M4 mirrors the current of the eleventh MOS transistor M11, and then mirrors the current to the first MOS transistor M1 and the second MOS transistor M2 through the current mirror composed of the third MOS transistor M3 and the fifth MOS transistor M5, but in the embodiment of the present invention, the magnitude of the bias voltage output signal at the bias voltage output signal end may also be adjusted by adjusting circuit parameters, such as any one of the ratio of the width-to-length ratio of the fourth MOS transistor M4 to the tenth MOS transistor M10, the ratio of the width-to-length ratio of the third MOS transistor M3 to the fifth MOS transistor M5, and the ratio of the width-to-length ratios of the first MOS transistor M1 and the second MOS transistor M2, to provide a proper gate voltage bias for the fourteenth MOS transistor M14.
The ninth MOS transistor M9, the tenth MOS transistor M10, and the second resistor R2 form the start-up circuit 30. When the circuit is just powered on, the output voltage of the second start-up voltage output signal terminal 32 of the start-up circuit 30 is the ground voltage GND, the ninth MOS transistor M9 is turned on, the base voltage of the fourth transistor Q4 is charged high, so that the bandgap reference circuit 20 starts to operate, the eleventh MOS transistor M11 is turned on, the tenth MOS transistor M10 mirrors the drain current of the eleventh MOS transistor M11, the voltage of the first start-up voltage output signal terminal 32 is charged high, and by setting the ratio M of the width-to-length ratio of the tenth MOS transistor M10 to the eleventh MOS transistor M11 and the resistance value of the second resistor R2, the voltage of the second start-up voltage output signal terminal 32 can be charged high to be approximately equal to the power supply voltage VDD, so that the ninth MOS transistor M9 is turned off after the start-up is completed, and the normal operation of the bandgap reference circuit 20 is not affected.
The first resistor R1, the sixth MOS transistor M6, the seventh MOS transistor M7 and the eighth MOS transistor M8 form an undervoltage indication circuit 40, and the first resistor R1 and the sixth MOS transistor M6 form a bias current source for providing a bias current for the eighth MOS transistor M8. When the bandgap reference circuit 20 is in a normal operating state after being started up, the voltage value of the under-voltage indication input signal terminal 41, i.e. the voltage value of the gate of the seventh MOS transistor M7, is approximately equal to the power supply voltage VDD, the seventh MOS transistor M7 is turned off, and the eighth MOS transistor M8 is always in a conducting state, so that the under-voltage indication output signal vrefak is at a low level, and the voltage value thereof is approximately equal to the ground voltage GND, which does not affect the normal operation of the subsequent circuit. When the reference voltage signal VREF of the bandgap reference circuit 20 is lower than the rated value for some reason, according to the formula (3), the drain current of the tenth MOS transistor M10 will decrease, which results in that the output voltage of the second starting voltage output signal terminal 33 of the starting circuit 30 decreases, that is, the gate voltage of the ninth MOS transistor decreases, the seventh MOS transistor M7 is gradually turned on, when the output voltage of the second starting voltage output signal terminal 33 decreases to a certain degree, the drain current of the seventh MOS transistor M7 is greater than the drain current of the eighth MOS transistor M8, then the undervoltage indication output signal vrefouk is inverted from the low level to the high level, thereby turning off the rear-stage circuit, preventing the rear-stage circuit from working abnormally, and the voltage value of VREF at this time is the undervoltage indication point of the bandgap reference circuit. In a specific application, the size of the undervoltage indication point of the bandgap reference circuit can be set by adjusting a plurality of circuit parameters, such as the ratio M of the width-to-length ratio of the tenth MOS transistor M10 to the eleventh MOS transistor M11, the ratio M of the width-to-length ratio of the sixth MOS transistor M6 to the eighth MOS transistor M8, and the resistance values of the first resistor R1 and the second resistor R2.
To sum up, the under-voltage indication system provided by the embodiment of the present invention includes a voltage bias circuit, a bandgap reference circuit, a start circuit, and an under-voltage indication circuit, wherein the under-voltage indication circuit collects a second start voltage output signal of the start circuit through the second start voltage output signal terminal, and outputs an under-voltage indication output signal.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the foregoing embodiments illustrate the present invention in detail, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (9)
1. An undervoltage indicating system is characterized by comprising a voltage bias circuit, a band-gap reference circuit, a starting circuit and an undervoltage indicating circuit;
the voltage bias circuit comprises a bias voltage input signal end and a bias voltage output signal end;
the band-gap reference circuit comprises a first reference voltage input signal end, a second reference voltage input signal end, a reference voltage output signal end and a reference voltage output signal end;
the starting circuit comprises a starting voltage input signal end, a first starting voltage output signal end and a second starting voltage output signal end;
the undervoltage indicating circuit comprises an undervoltage indicating input signal end and an undervoltage indicating output signal end;
the bias voltage output signal end is connected with the first reference voltage input signal end, the bias voltage input signal end is connected with the reference voltage output signal end and is connected with the starting voltage input signal end, the first starting voltage output signal end is connected with the second reference voltage input signal end, the second starting voltage output signal end is connected with the under-voltage indication input signal end, and the under-voltage indication output signal end is connected with a rear-stage circuit; the reference voltage output signal end is connected with a post-stage circuit and provides a reference voltage signal VREF for the post-stage circuit;
the under-voltage indicating circuit collects a second starting voltage output signal of the starting circuit through the second starting voltage output signal end and outputs an under-voltage indicating output signal based on the band-gap reference circuit;
when the undervoltage indication output signal is at a low level, the rear-stage circuit works normally, and when the undervoltage indication output signal is overturned from the low level to a high level, the rear-stage circuit is turned off.
2. The undervoltage indication system of claim 1, wherein the voltage bias circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor;
the source electrode of the first MOS tube is connected with a power supply, and the grid electrode and the drain electrode of the first MOS tube are connected with each other and then connected with the source electrode of the second MOS tube; the grid electrode and the drain electrode of the second MOS tube are connected with each other and then are connected with the drain electrode of the third MOS tube, and the grid electrode and the drain electrode of the second MOS tube are also used as the bias voltage output signal end and are connected with the first reference voltage input signal end of the band-gap reference circuit after being connected with each other;
the source electrode of the third MOS tube is grounded, and the grid electrode of the third MOS tube is connected with the grid electrode and the drain electrode of the fifth MOS tube and is connected with the drain electrode of the fourth MOS tube; the source electrode of the fifth MOS tube is grounded; and the source electrode of the fourth MOS tube is connected with a power supply, and the grid electrode of the fourth MOS tube is used as the bias voltage input signal end and is connected with the reference voltage output signal end of the band-gap reference circuit.
3. The undervoltage indication system of claim 1, wherein the undervoltage indication circuit comprises a first resistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor;
one end of the first resistor is connected with a power supply, and the other end of the first resistor is connected with the grid electrode and the drain electrode of the sixth MOS tube and the grid electrode of the eighth MOS tube; the source electrode of the sixth MOS tube and the source electrode of the eighth MOS tube are grounded; the drain electrode of the eighth MOS tube is connected with the drain electrode of the seventh MOS tube, and the source electrode of the seventh MOS tube is connected with a power supply;
the drain electrode of the eighth MOS tube is connected with the drain electrode of the seventh MOS tube and then is used as the under-voltage indication output signal end; and the grid electrode of the seventh MOS tube is used as the under-voltage indication input signal end and is connected with the second starting voltage output signal end of the starting circuit.
4. The undervoltage indication system of claim 1, wherein the start-up circuit comprises a second resistor, a ninth MOS transistor, and a tenth MOS transistor.
5. The source electrode of the ninth MOS tube is connected with a power supply, the grid electrode of the ninth MOS tube is connected with the drain electrode of the tenth MOS tube and one end of the second resistor, the other end of the second resistor is grounded, and the source electrode of the tenth MOS tube is connected with the power supply;
the grid electrode of the tenth MOS tube is used as the starting voltage input signal end and is connected with the reference voltage output signal end of the band-gap reference circuit;
and the grid electrode of the ninth MOS tube is used as the second starting voltage output signal end and is connected with the under-voltage indication input signal end of the under-voltage indication circuit, and the drain electrode of the ninth MOS tube is used as the first starting voltage output signal end and is connected with the second reference voltage input signal end of the band-gap reference circuit.
6. The undervoltage indication system of claim 1, wherein the bandgap reference circuit comprises a third resistor, a fourth resistor, a fifth resistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a first triode, a second triode, a third triode, a fourth triode, a fifth triode, and a sixth triode;
the source electrode of the eleventh MOS tube is connected with a power supply, and after the grid electrode and the drain electrode of the eleventh MOS tube are connected with each other, the source electrode of the eleventh MOS tube is connected with the drain electrode of the twelfth MOS tube, the grid electrode of the thirteenth MOS tube and the grid electrode of the fifteenth MOS tube, and after the connection, the source electrode of the eleventh MOS tube is used as the reference voltage output signal end, is connected with the bias voltage input signal end of the voltage bias circuit and is connected with the starting voltage input signal end of the starting circuit; a grid electrode of the twelfth MOS tube is connected with a drain electrode of the fifteenth MOS tube, an emitting electrode of the third triode and a base electrode of the fourth triode, is used as the second reference voltage input signal end after being connected, and is connected with a first starting voltage output signal end of the starting circuit;
the source electrode of the twelfth MOS tube is connected with the collector electrode of the first triode; the source electrode of the thirteenth MOS tube and the source electrode of the fifteenth MOS tube are connected with a power supply, and the drain electrode of the thirteenth MOS tube is connected with the source electrode of the fourteenth MOS tube;
a grid electrode of the fourteenth MOS tube is used as the first reference voltage input signal end and is connected with a bias voltage output signal end of the voltage bias circuit;
the drain electrode of the fourteenth MOS tube is connected with the collector electrode of the second triode and the base electrode of the third triode; the emitter of the first triode is grounded, and the base of the first triode is connected with one end of the third resistor and the collector and the base of the fifth triode; an emitting electrode of the second triode is grounded, and a base electrode of the second triode is connected with one end of the fourth resistor and a collector electrode of the sixth triode; the collector of the third triode is grounded; a collector of the fourth triode is connected with a power supply, and an emitter of the fourth triode is connected with the other end of the third resistor and the other end of the fourth resistor, is used as the reference voltage output signal end and provides a reference voltage signal for a post-stage circuit;
an emitter of the fifth triode is grounded; and an emitter of the sixth triode is connected with one end of the fifth resistor, and the other end of the fifth resistor is grounded.
7. The brown-out indication system of claim 5, wherein the third resistance and the fourth resistance are equal in resistance value; the emitter areas of the fifth triode and the first triode are equal; the area ratio of the emitting electrodes of the fifth triode and the sixth triode is 1: 8.
8. The brown-out indication system of claim 6, wherein the brown-out indication circuit collects a second start-up voltage output signal of the start-up circuit through the second start-up voltage output signal terminal, and before outputting the brown-out indication output signal, comprises:
and adjusting circuit parameters to set the critical voltage value of the undervoltage indication output signal, which is turned from low level to high level.
9. The undervoltage indication system of claim 6, wherein the circuit parameter comprises at least one of a ratio of a width-to-length ratio of the tenth MOS transistor to the eleventh MOS transistor, a ratio of a width-to-length ratio of the sixth MOS transistor to the eighth MOS transistor, a resistance of the first resistor, and a resistance of the second resistor.
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| CN101432747A (en) * | 2006-03-10 | 2009-05-13 | 爱特梅尔公司 | Brownout detector system and method |
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