JP7364355B2 - voltage detection circuit - Google Patents

Description

The present invention relates to a voltage detection circuit.

2. Description of the Related Art Voltage detection circuits are used in circuits of various devices including semiconductor integrated circuits and the like, which use the power supply voltage of a power source as an input voltage to detect a low voltage state or a high voltage state in which the target circuit does not operate stably. An example of this type of voltage detection circuit is a UVLO (Under Voltage Lock Out) circuit, which uses a comparator or the like to detect a low voltage state where the input voltage is lower than a predetermined voltage, and It has a function to turn off the operation.

As a voltage detection circuit used in a UVLO circuit, a voltage detection circuit having a bandgap circuit is known, for example, as disclosed in Patent Document 1. The voltage detection circuit of Patent Document 1 utilizes the fact that, in two transistors that constitute a bandgap circuit and have different junction areas, a difference occurs in the current flowing through each transistor depending on the input voltage. In this conventional example, a bandgap output is obtained when the power supply voltage exceeds a predetermined voltage, and this output inverts the logic of the output terminal, thereby indicating that the power supply voltage has increased or decreased relative to the predetermined voltage. Detected. With this configuration, it is not necessary to provide a stabilized power supply that generates the reference voltage and a comparator that compares the input voltage with the reference voltage, and it is possible to perform voltage detection with respect to a predetermined voltage.

Japanese Patent Application Publication No. 1-274071

In the conventional voltage detection circuit as disclosed in Patent Document 1, when the power supply voltage rises, the current flowing through the collectors of the two transistors forming the bandgap circuit increases, so power consumption increases as the voltage rises. go. When such a voltage detection circuit is used in a UVLO circuit, the power supply voltage during normal operation is in a much larger voltage range than the detection voltage for detecting a low voltage state, so the power consumption by the voltage detection circuit during normal operation is large. There is an issue of becoming. In recent years, there has been a demand for further reduction in power consumption of voltage detection circuits in battery-powered devices and the like.

An object of the present invention is to provide a voltage detection circuit that can reduce power consumption.

The present invention provides a first resistor and a second resistor that divide an input voltage applied to a voltage input terminal, bases of which are connected to each other between the first resistor and the second resistor, and a bandgap a first transistor and a second transistor forming a circuit, one of the input parts of the first current mirror circuit is connected to the collector of the first transistor, and the input part of the first current mirror circuit is connected to the collector of the first transistor; is connected to the voltage input terminal, one of the input parts of the second current mirror circuit is connected to the collector of the second transistor, and the other input part of the second current mirror circuit is connected to the voltage input terminal. one of the input parts of the third current mirror circuit is connected to the output part of the first current mirror circuit, the other input part of the third current mirror circuit is grounded, and the emitter of the first transistor is connected to the output part of the first current mirror circuit. grounded via a third resistor and a fourth resistor, the emitter of the second transistor is connected to a connection node between the third resistor and the fourth resistor, and is grounded via the fourth resistor; and a detection output terminal provided at a connection node where a first output section of the second current mirror circuit and a first output section of the third current mirror circuit are connected to each other. However, as the input voltage changes, the voltages at the first output portions of the second current mirror circuit and the third current mirror circuit change, so that the input voltage becomes equal to or higher than a predetermined voltage value or a predetermined voltage. a voltage detection circuit for detecting that the voltage has fallen below a voltage, the second output section of the second current mirror circuit being provided in parallel with the first output section of the second current mirror circuit, and the third current mirror circuit; a second output section of a third current mirror circuit provided in parallel with the first output section of the circuit; and a third current mirror circuit provided between the first resistor and the second resistor; a current limiting element constituting a clamp circuit that clamps the base voltages of the first and second transistors below a predetermined value by limiting the current flowing through the second resistor; and a second output of the second current mirror circuit. A fifth current mirror circuit whose gate is connected to a connection node where the section and the second output section of the third current mirror circuit are connected to each other, whose source is grounded, and whose drain is connected to the voltage input terminal via a fifth resistor. 1 MOSFET, and controls the operation of the clamp circuit according to a change in the voltage of the second output part of the second current mirror circuit and the third current mirror circuit as the input voltage changes; Provided is a voltage detection circuit having the following.

Further, the present invention provides the above voltage detection circuit , in which the current limiting element has a drain connected to the first resistor, and a source connected to the bases of the first transistor and the second transistor, and the current limiting element. a second MOSFET whose gate is connected to the drain of the first MOSFET and the fifth resistor; the first MOSFET is responsive to changes in the input voltage; The gate voltage of the second MOSFET is controlled accordingly, and the second MOSFET has a drain current that changes depending on the gate voltage and limits the current flowing through the first resistor and the second resistor. The present invention provides a voltage detection circuit that operates the clamp circuit at a voltage equal to or higher than a second voltage value that is larger than the first voltage value at which the output voltage of the detection output terminal is inverted.

Further, the present invention provides the above voltage detection circuit, in which the first output section and the second output section of the third current mirror circuit are each constituted by a MOSFET, and the ratio of the gate widths of the two MOSFETs is 1. :N (N>1).

The present invention also provides the above voltage detection circuit, which is provided between the voltage input terminal and the other of the input parts of the first current mirror circuit and the second current mirror circuit, and A voltage detection circuit is provided, further comprising a power supply isolation element that isolates a power supply input section that is the other input section of the circuit and the other input section of the second current mirror circuit.

Further, the present invention provides the above voltage detection circuit, wherein the clamp control element has a gate connected to a connection node between the second output section of the second current mirror circuit and the second output section of the third current mirror circuit. the current limiting element has a first MOSFET whose source is grounded and whose drain is connected to the voltage input terminal via a fifth resistor, and the current limiting element has a drain connected to the first resistor. , a second MOSFET whose source is connected to the bases of the first and second transistors and the second resistor, and whose gate is connected to the drain of the first MOSFET and the fifth resistor. The power supply separation element has a drain connected to the voltage input terminal, a source connected to the other of the input parts of the first current mirror circuit and the second current mirror circuit, and a gate connected to the second MOSFET. A voltage detection circuit is provided, comprising a third MOSFET whose gate is connected to the drain of the first MOSFET and the fifth resistor.

According to the present invention, it is possible to provide a voltage detection circuit that can reduce power consumption.

1 is a diagram showing the configuration of a voltage detection circuit according to a first embodiment; FIG. 2 is a characteristic diagram showing an example of the operating characteristics of the circuit in FIG. 1. FIG. FIG. 7 is a diagram showing the configuration of a voltage detection circuit according to a second embodiment. 1 is a diagram showing the basic configuration of a UVLO circuit. 5 is a characteristic diagram showing an example of the operating characteristics of the circuit of FIG. 4. FIG.

EMBODIMENT OF THE INVENTION Hereinafter, an embodiment (hereinafter referred to as "this embodiment") specifically disclosing a voltage detection circuit according to the present invention will be described in detail with reference to the drawings.

(Background leading to this embodiment)
First, the issue of power consumption in the voltage detection circuit will be explained.

Here, as an example of a voltage detection circuit, a UVLO circuit that detects a rise in the power supply voltage (a rise from around 0V to a predetermined voltage or higher) or a drop in the power supply voltage (a drop from a normally operable voltage to below a predetermined voltage) Assuming the configuration when applied to

In a UVLO circuit, it is desirable that a constant detection voltage can always be detected without being affected by temperature when the power supply voltage rises or falls. On the other hand, since such a UVLO circuit detects the rise of the power supply voltage, it needs to operate normally even when the reference voltage generation circuit is not able to output a sufficient output voltage. For this reason, it may not be possible to adopt a configuration in which a reference voltage with small temperature fluctuation is received from another circuit and the reference voltage is compared with the detected power supply voltage. Therefore, the UVLO circuit often has a configuration using a comparator using a bandgap circuit.

FIG. 4 is a diagram showing the basic configuration of the UVLO circuit. The UVLO circuit is a circuit that includes a first transistor Q1 and a second transistor Q2 that constitute a bandgap circuit, and has a comparator function. The first and second transistors Q1 and Q2 are composed of NPN transistors, and their bases are connected to each other. The emitter area ratio of the first transistor Q1 and the second transistor Q2 is, for example, M:1 (M>1). A first current mirror circuit including PMOS transistors M1 and M2 is connected to the collector of the first transistor Q1, and a second current mirror circuit including PMOS transistors M3 and M4 is connected to the collector of the second transistor Q2. is connected.

The sources of the transistors M1, M2, M3, and M4 are connected to the input terminal (voltage input terminal) VIN of the UVLO circuit, and the input voltage Vin of the power supply voltage supplied to the input terminal VIN is applied. In addition, resistors R1 and R2 for voltage division are connected to the input terminal VIN, and the bases of the first and second transistors Q1 and Q2 are connected to the connection node of the resistors R1 and R2, and a voltage proportional to the input voltage Vin is connected to the input terminal VIN. is applied to the bases of transistors Q1 and Q2.

Resistors R3 and R4 are connected to the emitter of the first transistor Q1, the emitter of the second transistor Q2 is connected to a connection node between the resistors R3 and R4, and the other end of the resistor R4 is grounded. Furthermore, a Zener diode DZ1 is connected to both ends of the resistor R2.

A third current mirror circuit including NMOS transistors M6 and M7 is further connected to the first current mirror circuit including transistors M1 and M2, and the sources of transistors M6 and M7 are grounded. The drain of the transistor M4 and the drain of the transistor M7 are connected, and the output end (detection output end) OUT_UVLO of the UVLO circuit is connected to the connection node between the transistors M4 and M7.

In the above configuration, the collector currents of the first transistor Q1 and the second transistor Q2 are matched at the drains of the transistor M4 and the transistor M7 via current mirror circuits, respectively. As the power supply voltage (input voltage at the input terminal VIN) changes, the base voltages of the first and second transistors Q1 and Q2 change, and this change in base voltage changes the ratio of the collector currents of the transistors Q1 and Q2. . When the input voltage Vin at the input terminal VIN is lower than a predetermined voltage, the collector current of the first transistor Q1 flows more than the collector current of the second transistor Q2. At this time, the drain currents of the transistor M4 and the transistor M7 are drawn into the transistor M7 side, and the output voltage of the output terminal OUT_UVLO becomes Low level.

Here, settings are made such that when the collector currents of the first and second transistors Q1 and Q2 become equal, the output voltage of the output terminal OUT_UVLO of the UVLO circuit switches from Low level to High level. The input voltage of the input terminal VIN at this time, ie, the release voltage Vrin of the UVLO circuit, is expressed by the following equation (1).

In the above equation, the base-emitter potential difference of Vbeq2...Q2 is expressed as VT...VT=kT/q, where k: Boltzmann constant, T: temperature, q: elementary charge, and when temperature Ta=27°C, VT =0.026V. Further, M is the emitter area ratio of Q1 and Q2 (Q1:Q2=M:1 (M>1)).

At this time, by adjusting the resistance ratio of resistors R3 and R4, the amount of temperature change in release voltage Vrin of the UVLO circuit (temperature differential value of Vrin) can be adjusted by adjusting the primary temperature coefficient of base-emitter voltage Vbeq2 of transistor Q2 (for example approximately -2 mV/°C). As a result, the temperature change in the release voltage (detection voltage) Vrin at which the output of the UVLO circuit is switched is suppressed to a small extent, and the temperature characteristic is substantially constant, making it unnecessary to supply a reference voltage from other circuits.

The circuit configuration shown in FIG. 4 has a problem in that the power consumption of the voltage detection circuit, that is, the current consumption of transistors Q1, Q2, etc. of the bandgap circuit increases when the power supply voltage is high. When the temperature characteristics of the UVLO circuit are made flat, the base voltage of the transistors Q1 and Q2 when the output voltage is switched (when the release voltage is reached) is, for example, about 1.25V. When the input voltage of the UVLO circuit becomes higher than the release voltage and the base voltages of transistors Q1 and Q2 rise, the total value of the collector currents of transistors Q1 and Q2 increases. For example, if the base voltage of transistors Q1 and Q2 is 3V, the total value of the collector currents will be about four times the value when the output voltages are switched. When the release voltage of the UVLO circuit is low, or when the power supply voltage during normal operation is high, or when the difference between the input voltage Vin during normal operation and the release voltage Vrin is large, the current consumption of the UVLO circuit further increases. .

FIG. 5 is a characteristic diagram showing an example of the operating characteristics of the circuit shown in FIG. The example in FIG. 5 shows the collector current IcQ2 of the transistor Q2 with respect to the input voltage Vin when the release voltage Vrin of the UVLO circuit is 2.7V and the power supply voltage during normal operation (normal operating voltage) Vop is 12 to 14V. There is.

For example, in the case of a power supply IC for in-vehicle equipment, the normal operating voltage is about 12 to 14V, but in consideration of the battery voltage drop during large power consumption such as when starting the engine, it is necessary to operate at a power supply voltage of about 3V. be. Therefore, the UVLO circuit needs to detect the rise of the power supply voltage at 3V or less, and performs voltage detection by setting the release voltage to 2.7V, for example. In this case, there is a large voltage difference between when the release voltage is detected and when the UVLO circuit is in normal operation, which is a factor that increases the power consumption of the UVLO circuit when it is operating at the normal voltage.

In order to improve the power consumption characteristics of such a voltage detection circuit, it is necessary to provide a clamp circuit to prevent the base voltages of the transistors Q1 and Q2 from rising too high more than necessary. However, with respect to the clamp circuit, it is difficult to obtain a stable clamp voltage with respect to temperature unless an external bandgap circuit or the like is activated. In the circuit configuration of FIG. 4, a Zener diode is used as a clamp circuit, and the clamp voltage Vb of this clamp circuit is approximately 5V. Therefore, the clamp voltage becomes about twice as high as the release voltage of the UVLO circuit, and an increase in current consumption is unavoidable.

In view of the above circumstances, this embodiment shows a configuration example of a voltage detection circuit that can suppress an increase in current consumption in the UVLO circuit and reduce power consumption. The configuration of this embodiment reduces power consumption of circuits such as switching power supplies and composite power supply ICs equipped with UVLO circuits.

In the following embodiments, an example of the configuration and operation of a voltage detection circuit applied to a UVLO circuit will be described as a voltage detection circuit according to the present invention.

(First embodiment)
FIG. 1 is a diagram showing the configuration of a voltage detection circuit according to a first embodiment. The voltage detection circuit of this embodiment constitutes a UVLO circuit. The voltage detection circuit includes a first transistor Q1 and a second transistor Q2 forming a bandgap circuit. The first and second transistors Q1 and Q2 are composed of NPN type transistors, and their bases are connected to each other. The emitter area ratio of the first transistor Q1 and the second transistor Q2 is, for example, M:1. As an example, M is set to about 4. A first current mirror circuit 11 (one of the input parts of the first current mirror circuit) including PMOS transistors (MOSFETs) M1 and M2 is connected to the collector of the first transistor Q1. Further, a second current mirror circuit 12 (one of the input parts of the second current mirror circuit) including PMOS type transistors (MOSFETs) M3 and M4 is connected to the collector of the second transistor Q2.

The input terminal (voltage input terminal) VIN of the voltage detection circuit is connected to the sources of transistors M1, M2, M3, and M4 (the other input section of the first and second current mirror circuits), and the voltage is supplied to the input terminal VIN. An input voltage Vin of a power supply voltage is applied. Further, a first resistor R1, which is a voltage dividing resistor, is connected to the input terminal VIN, and a clamp circuit for limiting the base voltage is connected between the resistor R1 and the bases of the first and second transistors Q1 and Q2. An NMOS type transistor M10 (second MOSFET) is provided. The drain of the transistor M10 is connected to the resistor R1, the source is connected to the bases of the transistors Q1 and Q2, and the second resistor R2, and the other end of the resistor R2 is grounded. The gate of the transistor M10 is connected to the input terminal VIN via a resistor R5, and is pulled up by the resistor R5.

An NMOS transistor M9 (first MOSFET) is provided between the gate of the transistor M10 and the ground, the drain of the transistor M9 is connected to the gate of the transistor M10 and the resistor R5, and the source of the transistor M9 is grounded. Ru. A voltage corresponding to the input voltage Vin is applied to the bases of the first and second transistors Q1 and Q2 from the input terminal VIN via the resistor R1 and the transistor M10. When the drain current flows in the transistor M9 as the input voltage Vin increases, the gate voltage of the transistor M10 is lowered, and as a result, the base voltages of the transistors Q1 and Q2 are also lowered.

A third resistor R3 and a fourth resistor R4 are connected to the emitter of the first transistor Q1, the emitter of the second transistor Q2 is connected to the connection node of the resistors R3 and R4, and the other end of the resistor R4 is grounded. be done. In this way, the bandgap circuit formed by the first and second transistors Q1 and Q2 has a differential input circuit section formed by the above-mentioned connection configuration of the resistors R3 and R4. The resistors R3 and R4 are set by adjusting the resistance ratio so that the release voltage Vrin at which the output of the UVLO circuit is switched has a substantially constant temperature characteristic.

A third current mirror circuit 13 including NMOS transistors M6 and M7 is further connected to the output section of the first current mirror circuit including the transistors M1 and M2, and the sources of the transistors M6 and M7 (the input section of the third current mirror circuit) are connected to the output section of the first current mirror circuit including the transistors M1 and M2. ) is grounded. Then, the drain of the transistor M4 (the first output part of the second current mirror circuit) and the drain of the transistor M7 (the first output part of the third current mirror circuit) are connected to each other, and a voltage is applied to the connection node of the transistors M4 and M7. The output end (detection output end) OUT_UVLO of the detection circuit is connected.

Further, in parallel with the transistor M4, a PMOS type transistor M5, which is the same as the transistor M4, is provided as a second output section of the second current mirror circuit 12. Further, in parallel with the transistor M6, an NMOS transistor M8, which is the same as the transistor M6, is provided as a second output section of the third current mirror circuit 13. The drain of the transistor M5 and the drain of the transistor M8 are connected to each other, and the gate of the transistor M9 is connected to this connection node. Here, the ratio of the gate widths of the transistor M6 and the transistor M8 is, for example, 1:N (N>1). As an example, N=about 1.5 to 2.0 is set, and the gate width ratio is determined so that the drain current of the transistor M8 is greater than the drain current of the transistor M6.

With the above configuration, the voltage at the first output portions of the second current mirror circuit 12 and the third current mirror circuit 13 changes due to a change in the input voltage Vin supplied to the voltage input terminal VIN, so that the input voltage Vin becomes a predetermined value. It is detected that the voltage is higher than or equal to a predetermined voltage value. That is, it detects the rise of the input voltage Vin to above the release voltage Vrin of the UVLO circuit, or the fall of the input voltage Vin to below the release voltage Vrin.

In the above configuration, the collector currents of the first transistor Q1 and the second transistor Q2 are matched at the drains of the transistor M4 and the transistor M7 via current mirror circuits, respectively. As the power supply voltage (input voltage at the input terminal VIN) changes, the base voltages of the first and second transistors Q1 and Q2 change, and this change in base voltage changes the ratio of the collector currents of the transistors Q1 and Q2. . When the input voltage Vin at the input terminal VIN is lower than a predetermined voltage, the collector current of the first transistor Q1 flows more than the collector current of the second transistor Q2. At this time, the drain currents of the transistor M4 and the transistor M7 are drawn into the transistor M7 side, and the output voltage of the output terminal OUT_UVLO becomes Low level.

Then, assume that the input voltage Vin at the input terminal VIN rises from 0V. The base voltages of transistors Q1 and Q2 also increase in proportion to the increase in input voltage Vin. When this base voltage reaches about 0.6V, the collector currents of transistors Q1 and Q2 begin to flow. Since the emitter area of the first transistor Q1 is M times that of the second transistor Q2, when the base voltage is low, the collector current of the first transistor Q1 is larger than the collector current of the second transistor Q2. It flows a lot. Here, since the resistor R3 is provided at the emitter of the first transistor Q1, the difference in collector current decreases as the base voltage increases. As the collector current of the second transistor Q2 increases, the drain current of the transistor M4 increases. When the collector current of the first transistor Q1 and the collector current of the second transistor Q2 become the same, the output voltage of the output terminal OUT_UVLO switches from low level to high level, and the rise of the input voltage Vin of the input terminal VIN is suppressed. To detect. The input voltage Vin at this time becomes the release voltage Vrin of the UVLO circuit.

At this point in time when the output voltage is switched, the drain current of the transistor M8 is set to be N times larger than the drain current of the transistor M6. Therefore, the current that the transistor M8 sinks is larger than the current that the transistor M5 sources, and the gate voltage of the transistor M9 is at a low level, so that the transistor M9 is in an OFF state. The gate voltage of the transistor M10 at this time is equal to the input voltage Vin at the input terminal VIN. Here, the transistor M9, which is the first MOSFET, functions as a clamp control element that controls the gate voltage of the transistor M10, which is the second MOSFET, and switches the operation of the clamp circuit. Further, the transistor M10, which is the second MOSFET, has a drain current that changes depending on the gate voltage, and functions as a current limiting element that limits the current flowing through the first resistor R1 and the second resistor R2. This constitutes a clamp circuit that limits the base voltages of the first and second transistors.

When the input voltage Vin at the input terminal VIN further increases, the collector current of the first transistor Q1 becomes smaller than the collector current of the second transistor Q2, and the current sourced by the transistor M5 increases. Eventually, the gate voltage of transistor M9 switches to High level, and the drain current of transistor M9 begins to flow. This lowers the gate voltage of the transistor M10, reduces the drain current of the transistor M10, and lowers the base voltages of the first and second transistors Q1 and Q2. Due to this series of feedback effects, when the input voltage Vin at the input terminal VIN exceeds a predetermined second voltage value, the base voltages of the first and second transistors Q1 and Q2 converge to a constant value. As a result, since the base voltages of the first and second transistors Q1 and Q2 are suppressed, an increase in their collector currents is also suppressed, and the current consumption of the entire voltage detection circuit including the UVLO circuit does not increase beyond a predetermined value.

As mentioned above, when the base voltages of the first and second transistors Q1 and Q2 converge to a constant value, that is, when the base voltage starts to be clamped, the power supply voltage (the input voltage at the input terminal VIN) is defined as the clamp voltage Vcin. do. The clamp voltage Vcin is approximated by the following equation (2) when the base currents of the transistors Q1 and Q2 are negligibly small compared to the currents flowing through the resistors R1 and R2.

In the above equation, the base-emitter potential difference of Vbeq2...Q2 is expressed as VT...VT=kT/q, where k: Boltzmann constant, T: temperature, q: elementary charge, and when temperature Ta=27°C, VT =0.026V. Also, M...emitter area ratio of Q1 and Q2 (Q1:Q2=M:1 (M>1)), N...ratio of gate widths of M6 and M8 (M6:M8=1:N (N>1)) It is. The ratio N of the gate widths of the transistors M6 and M8 is, for example, about N=1.5 to 2.0, and taking into consideration the characteristic variations of the current mirror circuit, temperature characteristics, etc., the clamp voltage Vcin is always higher than the release voltage Vrin. Set the voltage to be high.

FIG. 2 is a characteristic diagram showing an example of the operating characteristics of the circuit shown in FIG. The example in FIG. 2 shows the collector current IcQ2 of the transistor Q2 with respect to the input voltage Vin when the release voltage Vrin of the UVLO circuit is 2.7V and the power supply voltage during normal operation (normal operating voltage) Vop is 12 to 14V. There is.

The input voltage Vin rises from 0V, exceeds the release voltage Vrin, and the output voltage switches from Low level to High level. When the input voltage Vin reaches the clamp voltage Vcin, the base voltages of the transistors Q1 and Q2 are controlled to be below a predetermined value, suppressing the increase in the base voltage and also suppressing the increase in the collector current IcQ2. Even in a state where the input voltage Vin of the power supply voltage is 12 to 14 V of the normal operating voltage Vop, the collector current IcQ2 does not flow much, and the current consumption of the UVLO circuit can be reduced.

The configuration of this embodiment does not require a reference voltage for the clamp circuit that suppresses the rise in the base voltage of transistors Q1 and Q2 from other than the UVLO circuit, so the circuit operates stably even at a small voltage when the power supply voltage rises. be able to. Further, the elements for determining the clamp voltage Vcin by the transistor M10 serving as the clamp circuit are transistors M5, M6, and M8, which are constructed of the same type of transistors as the transistors M4, M6, and M7 that invert the output of the UVLO circuit. These transistors utilize the voltage difference between the base-emitter voltage Vbe of the NPN transistors Q1 and Q2, which detects the release voltage Vrin of the UVLO circuit. At this time, the characteristic variations of each transistor show the same tendency. Therefore, regardless of variations in the characteristics of the elements, the clamp voltage Vcin that starts clamping the base voltages of the transistors Q1 and Q2 can be reliably set to the release voltage Vrin of the UVLO circuit (the input voltage when the output voltage of the output terminal OUT_UVLO is switched). Can be set to a higher voltage.

(Second embodiment)
FIG. 3 is a diagram showing the configuration of a voltage detection circuit according to the second embodiment. The second embodiment is an example in which a part of the configuration of the first embodiment shown in FIG. 1 is changed. Here, the description will focus on the parts that are different from the first embodiment, and the description of the similar configurations and operations will be omitted.

In the voltage detection circuit of the second embodiment, the sources of transistors M1 and M2 and the sources of transistors M3, M4, and M5 constituting the current mirror circuit, that is, the power input section of the current mirror circuit, are separated from the input terminal VIN. connection is not made directly. An NMOS transistor M11 (third MOSFET) is provided between the input terminal VIN and the sources of the transistors M1, M2, M3, M4, and M5, and the drain of the transistor M11 is connected to the input terminal VIN, and the source is connected to the sources of transistors M1 to M5. The gate of the transistor M11 and the gate of the transistor M10 are connected to the input terminal VIN via a resistor R5. The transistor M11, which is the third MOSFET, functions as a power isolation element that isolates the voltage input terminal from the power input portions of the first current mirror circuit and the second current mirror circuit. The other configurations are similar to the first embodiment.

In the above configuration, when the base voltages of transistors Q1 and Q2 increase as the input voltage Vin increases, when the input voltage Vin exceeds the clamp voltage Vcin, the base voltages of the transistors Q1 and Q2 are set to be below a predetermined value. controlled. At this time, the source voltages of the transistors M1, M2, and the transistors M3, M4, and M5 are similarly controlled by the transistor M11 to be equal to or lower than a predetermined value, thereby suppressing an increase in the source voltages.

In the first embodiment shown in FIG. 1, when a high voltage is applied to the input terminal VIN, the transistors Q1 and Q2 and the transistors M1 to M10 also need to be elements with high breakdown voltage to withstand the high voltage. In contrast, in the second embodiment, the voltages applied to each element of transistors Q1 and Q2, transistors M1 and M2, and transistors M3, M4, and M5, that is, the power supply voltage of the UVLO circuit, are controlled to be below a predetermined value. Ru. Therefore, an element with a small element layout size and low breakdown voltage can be used, and the layout area of the UVLO circuit can be reduced.

Note that another voltage limiting element or circuit is additionally provided at the input section of the voltage detection circuit to clamp the input voltage Vin applied to the input terminal VIN so that it does not exceed the voltage range during normal operation. It may be configured to limit the value to a predetermined value or less.

As described above, in the voltage detection circuit of this embodiment, the current mirror circuit in the UVLO circuit is provided with the second output section (transistors M5, M8), and the output current of the second output section divides the voltage at the input section of the UVLO circuit. The current of the current limiting element (transistor M10) inserted between the resistors R1 and R2 is controlled. Thereby, the base voltages of the first and second transistors Q1 and Q2 in the input section of the UVLO circuit are controlled so as not to rise above a predetermined value.

In addition, in the configuration of the second embodiment, the input voltage to the voltage dividing resistors R1 and R2, which are the parts that detect the voltage applied to the input terminal VIN, and the power supply voltage of the UVLO circuit (power supply voltage of the current mirror circuit) The power supply voltage of the UVLO circuit is also controlled by the output current of the second output section.

With this configuration, the base voltage of the first and second transistors Q1 and Q2 that constitute the bandgap circuit can be suppressed to a predetermined value or less with respect to the input voltage during normal operation, and the current consumption of the UVLO circuit can be suppressed. , the power consumption of the entire circuit can be reduced. At this time, since the base voltages of the first and second transistors Q1 and Q2 are suppressed by the current flowing through the transistors M5 and M8 of the second output part in the own circuit, they are affected by variations in the characteristics of the elements. Never. For example, when the release voltage (detection voltage) Vrin of the UVLO circuit changes depending on the characteristics of the element, the clamp voltage Vcin also changes in conjunction with the release voltage Vrin. Therefore, it is possible to always appropriately detect the release voltage Vrin and suppress current consumption. Furthermore, by suppressing the power supply voltage of the UVLO circuit to a predetermined value or less, the voltage detection circuit can be constructed using elements with low breakdown voltage, the circuit area can be reduced, and the device equipped with the voltage detection circuit can be downsized.

In the present embodiment, the voltage detection circuit includes a second output section (transistor M5) provided in parallel with the first output section (transistor M4) of the second current mirror circuit 12, and a first output section (transistor M5) of the third current mirror circuit 13. It has a second output section (transistor M8) provided in parallel with the output section (transistor M7). Furthermore, by limiting the current flowing through the first resistor R1 and the second resistor R2 between the first resistor R1 and the second resistor R2, the bases of the first and second transistors Q1 and Q2 are It has a current limiting element (transistor M10) that constitutes a clamp circuit that clamps the voltage below a predetermined value. Further, the second current mirror circuit 12 and the third current mirror circuit 12 and the third current mirror circuit 12 are connected to the connection node where the second output part of the second current mirror circuit 12 and the second output part of the third current mirror circuit 13 are connected to each other. It has a clamp control element (transistor M9) that controls the operation of the clamp circuit by changing the voltage of the second output part of the current mirror circuit 13.

Further, the clamp control element has a gate connected to a connection node between the second output part of the second current mirror circuit 12 and the second output part of the third current mirror circuit 13, a source connected to the ground, and a drain connected to the fifth output part. It has a first MOSFET (transistor M9) connected to the voltage input terminal VIN via a resistor R5. Further, the current limiting element has a drain connected to the first resistor R1, a source connected to the bases of the first and second transistors Q1 and Q2, and the second resistor R2, and a gate connected to the first MOSFET. It has a second MOSFET (transistor M10) connected to the drain and the fifth resistor R5. The first MOSFET controls the gate voltage of the second MOSFET according to changes in input voltage, and the drain current of the second MOSFET changes according to the gate voltage. This limits the current flowing through the resistor R2. The clamp circuit is operated at a voltage equal to or higher than a second voltage value (clamp voltage Vcin) which is larger than the first voltage value (release voltage Vrin of the UVLO circuit) at which the output voltage of the detection output terminal OUT_UVLO is inverted. At this time, the ratio of the gate widths of the input part (transistor M6) and first output part (transistor M7) of the third current mirror circuit 13 to the second output part (transistor M8) is 1:N (N>1 ).

In the above configuration, the input voltage Vin at the voltage input terminal VIN increases from 0V, and when it reaches the release voltage Vrin, the drain current of the transistor M4 becomes larger than that of the transistor M7, and the output voltage at the detection output terminal OUT_UVLO is inverted. By this, the rise of the input voltage is detected. At this point, the drain current of transistor M8 is larger than that of transistors M5, M6, and M7. Then, when the input voltage Vin further increases and reaches the clamp voltage Vcin, the drain current of the transistor M5 becomes larger than that of the transistor M8, the first MOSFET (transistor M9) is turned on, and the second MOSFET (transistor M10) is turned on. ), and as a result, the base voltages of the first and second transistors Q1 and Q2 are suppressed to below a predetermined value. This limits the current flowing through the first resistor R1 and the second resistor R2, reducing current consumption.

In the voltage detection circuit, the power input terminal of the first current mirror circuit 11 and the second current mirror circuit 12 is connected between the voltage input terminal VIN and the power input section of the first current mirror circuit 11 and the second current mirror circuit 12. It further includes a power supply isolation element (transistor M11) that isolates the parts. The power supply isolation element has a drain connected to the voltage input terminal VIN, a source connected to the power input parts of the first current mirror circuit 11 and the second current mirror circuit 12, and a gate connected to the first MOSFET along with the gate of the second MOSFET. It has a third MOSFET (transistor M11) connected to the drain of the MOSFET and the fifth resistor R5. As a result, the voltage input terminal VIN is separated from the power input portions of the first current mirror circuit 11 and the second current mirror circuit 12 by the power supply separation element, and the voltage is applied to the first current mirror circuit 11 and the second current mirror circuit 12. The power supply voltage is suppressed to a predetermined value or less. Therefore, the voltage detection circuit can be constructed using elements with low breakdown voltage.

Although various embodiments have been described above with reference to the drawings, it goes without saying that the present invention is not limited to such examples. It is clear that those skilled in the art can come up with various changes or modifications within the scope of the claims, and these naturally fall within the technical scope of the present invention. Understood. Further, each component in the above embodiments may be arbitrarily combined without departing from the spirit of the present invention.

INDUSTRIAL APPLICATION This invention has the effect of being able to reduce the power consumption in a voltage detection circuit, and is useful for the voltage detection circuit which detects a predetermined voltage, for example in a UVLO circuit etc.

Q1, Q2: Transistor (NPN type)
M1, M2, M3, M4, M5: Transistor (PMOS type)
M6, M7, M8, M9, M10, M11: Transistor (NMOS type)
R1, R2, R3, R4, R5: Resistor VIN: Input terminal (voltage input terminal)
OUT_UVLO: Output end (detection output end)
11: First current mirror circuit 12: Second current mirror circuit 13: Third current mirror circuit

Claims (5)

a first resistor and a second resistor that divide the input voltage applied to the voltage input terminal;
a first transistor and a second transistor whose bases are connected to each other between the first resistor and the second resistor and configure a bandgap circuit;
One of the input parts of the first current mirror circuit is connected to the collector of the first transistor, and the other input part of the first current mirror circuit is connected to the voltage input terminal,
One of the input parts of the second current mirror circuit is connected to the collector of the second transistor, and the other input part of the second current mirror circuit is connected to the voltage input terminal,
One of the input parts of the third current mirror circuit is connected to the output part of the first current mirror circuit, and the other input part of the third current mirror circuit is grounded,
The emitter of the first transistor is grounded via a third resistor and a fourth resistor, and the emitter of the second transistor is connected to a connection node between the third resistor and the fourth resistor. a differential input circuit section grounded via a fourth resistor;
a detection output terminal provided at a connection node where the first output section of the second current mirror circuit and the first output section of the third current mirror circuit are connected to each other;
As the input voltage changes, the voltages at the first output portions of the second current mirror circuit and the third current mirror circuit change, so that the input voltage is greater than or equal to a predetermined voltage value or less than or equal to a predetermined voltage value. A voltage detection circuit that detects when
a second output section of a second current mirror circuit provided in parallel with the first output section of the second current mirror circuit;
a second output section of a third current mirror circuit provided in parallel with the first output section of the third current mirror circuit;
The base voltage of the first and second transistors is reduced by providing between the first resistor and the second resistor, and limiting the current flowing through the first resistor and the second resistor. a current limiting element that constitutes a clamp circuit that clamps the current below a predetermined value;
A gate is connected to a connection node where a second output part of the second current mirror circuit and a second output part of the third current mirror circuit are connected to each other, a source is grounded, and a drain is connected to a connection node through a fifth resistor. a first MOSFET connected to the voltage input terminal, and the clamp a clamp control element that controls the operation of the circuit;
Voltage detection circuit. The voltage detection circuit according to claim 1,
The current limiting element has a drain connected to the first resistor, a source connected to the bases of the first transistor and the second transistor, and the second resistor, and a gate connected to the first MOSFET. a second MOSFET connected to the drain of the transistor and the fifth resistor;
The first MOSFET controls the gate voltage of the second MOSFET according to the change in the input voltage, and the drain current of the second MOSFET changes according to the gate voltage, and the first MOSFET controls the gate voltage of the second MOSFET according to the change in the input voltage. and limiting the current flowing through the second resistor, and operating the clamp circuit at a voltage equal to or higher than a second voltage value that is larger than the first voltage value at which the output voltage at the detection output terminal is inverted;
Voltage detection circuit. The voltage detection circuit according to claim 1 or 2,
The first output section and the second output section of the third current mirror circuit are each constituted by a MOSFET, and the ratio of the gate widths of the two MOSFETs is 1:N (N>1).
Voltage detection circuit. The voltage detection circuit according to claim 1,
provided between the voltage input terminal and the other of the input parts of the first current mirror circuit and the second current mirror circuit, the other of the input parts of the first current mirror circuit and the input of the second current mirror circuit; further comprising a power isolation element that isolates the power input section, which is the other of the sections ;
Voltage detection circuit. The voltage detection circuit according to claim 4,
The clamp control element has a gate connected to a connection node between the second output part of the second current mirror circuit and the second output part of the third current mirror circuit, a source connected to the ground, and a drain connected to the fifth resistor. a first MOSFET connected to the voltage input terminal via
The current limiting element has a drain connected to the first resistor, a source connected to the bases of the first and second transistors and the second resistor, and a gate connected to the drain of the first MOSFET. a second MOSFET connected to the fifth resistor;
The power supply separation element has a drain connected to the voltage input terminal, a source connected to the other of the input parts of the first current mirror circuit and the second current mirror circuit, and a gate connected to the gate of the second MOSFET. a third MOSFET connected to the drain of the first MOSFET and the fifth resistor;
Voltage detection circuit.

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