CN104113041A - Under-voltage protection circuit for Ethernet power supply - Google Patents

Abstract

The invention provides an under-voltage protection circuit for Ethernet power supply. The under-voltage protection circuit for the Ethernet power supply comprises: a resistor voltage dividing circuit which adjusts and overturns a threshold voltage and generates a first output voltage and a second output voltage; a voltage selection circuit which is connected with the resistor voltage dividing circuit and selects one voltage value from the first output voltage and the second output voltage; a band gap comparison circuit which is connected with the voltage selection circuit, takes the voltage value selected by the voltage selection circuit or the voltage value of a protection circuit preventing operation caused by pulses of power supply voltages as an input voltage, and generates an under-voltage protection circuit UVLO signal; and a feedback control loop which is arranged between the resistor voltage dividing circuit and the band gap comparison circuit, outputs a quite high first output voltage when UVLO signal output has high level and the UVLO signal passes through the voltage selection circuit, and outputs a quite low second output voltage when the UVLO signal output has low level, such that a band gap comparison structure decreases the circuit area and accelerates the circuit response speed.

Description

A kind of under-voltage protecting circuit for Power over Ethernet

Technical field

The present invention relates to protective circuit field, particularly relate to a kind of under-voltage protecting circuit for Power over Ethernet.

Background technology

In recent years along with the application of internet voice protocol VoIP and WLAN WLAN is more and more extensive, provide the demand of electric power more and more urgent by Ethernet itself, Power over Ethernet PoE technology is in transmission data, electric power support can also be provided, therefore obtained rapid popularization, PoE technology is more and more applied to the network equipment.

Just because of being widely used of PoE technology, people are also more and more higher to the requirement of its stability, to ensure that PoE power supply can also normally work the voltage fluctuation in the situation that.After power supply unit PSE completes detection to powered device PD, classification, know the definite power rank of PD, PSE can raise supplying voltage, starts the power supply for PD, thereby realizes the supply voltage rising of starting from scratch; When supply voltage is charged to after the cut-in voltage of chip, circuit is normally worked; Due to the work of internal module, now the load current of system becomes large, and chip power voltage can produce fluctuation, and particularly the mains ripple meeting of chip high voltage district is larger.If the too low meeting of supply voltage causes very large power loss; therefore in order to ensure high voltage integrated circuit energy steady operation after chip is opened; also for fear of the infringement of chip fluctuation system, we generally introduce under-voltage protecting circuit chip power voltage are monitored simultaneously.

At present, as shown in Figure 1, this under-voltage protecting circuit comprises power supply voltage divider, reference voltage source, comparator and logical circuit to more common under-voltage protecting circuit.Chip is by power supply voltage divider sampling supply voltage, when sampled voltage V1 exceedes cut-in voltage V _{uVLO_R}, UVLO upset is low level, chip enable; When sampled voltage V2 is lower than supply voltage V _dD(off), the upset of under-voltage protecting circuit UVLO signal is high level, and chip turn-offs.This under-voltage protecting circuit uses independently reference voltage source and comparator, causes the response time longer, takies larger area and power consumption is large.

Summary of the invention

The object of the present invention is to provide a kind of under-voltage protecting circuit for Power over Ethernet, solve traditional under-voltage circuit and use independently reference voltage source and comparator, cause the response time longer, the large and large problem of power consumption of area occupied.

In order to solve the problems of the technologies described above, a kind of under-voltage protecting circuit for Power over Ethernet that the embodiment of the present invention provides, wherein, comprising:

For regulating the resistor voltage divider circuit of turnover door voltage limit, and produce the first output voltage and the second output voltage;

Voltage selecting circuit, is connected with described resistor voltage divider circuit, selects a magnitude of voltage from described the first output voltage and described the second output voltage;

Band gap comparison circuit, be connected with described voltage selecting circuit, the magnitude of voltage of protective circuit that causes operation for described magnitude of voltage that described voltage selecting circuit is selected or using the pulse that prevents supply voltage, as input voltage, produces a under-voltage protecting circuit UVLO signal;

Be arranged at the feedback control loop between described resistor voltage divider circuit and described band gap comparison circuit, for in the time that described UVLO signal is output as high level, described UVLO signal is through described voltage selecting circuit, export higher described the first output voltage, when described UVLO signal is output as low level, export lower described the second output voltage.

Wherein, the described under-voltage protecting circuit for Power over Ethernet also comprises: biasing circuit, and wherein said biasing circuit comprises: the first biasing circuit and comparative voltage produce circuit;

Wherein said the first biasing circuit comprises: the 30 PMOS transistor (M0), the 2nd PMOS transistor (M2), the 3rd PMOS transistor (M3), a PMOS transistor (M1) and the 4th electric capacity (C4)

Wherein said the 30 PMOS transistor (M0) grounded-grid, source electrode and the substrate of described the 30 PMOS transistor (M0) are connected in internal power source voltage (V _cC), the drain electrode of described the 30 PMOS transistor (M0) is connected with the drain electrode of described the 2nd PMOS transistor (M2), and the drain electrode of described the 2nd PMOS transistor (M2) is connected on the grid of described the 2nd PMOS transistor (M2);

The source electrode of described the 2nd PMOS transistor (M2) and substrate ground connection;

The source electrode of described the 3rd PMOS transistor (M3) and substrate ground connection;

The grid of described the 3rd PMOS transistor (M3) is by described the 4th electric capacity (C4) ground connection, and the grid of described the 2nd PMOS transistor (M2) and the transistorized grid of described the 3rd PMOS (M3) provide the first bias current (inp1) for described band gap comparison circuit;

The grid of described the 2nd PMOS transistor (M2) is connected with the grid of a described PMOS transistor (M1) by diode, the drain electrode of a described PMOS transistor (M1) is connected with the drain electrode of described the 3rd PMOS transistor (M3), and the source electrode of a described PMOS transistor (M1) and substrate are connected in described internal power source voltage (V _cC), the grid of a described PMOS transistor (M1) provides described the first bias current (inp1);

Wherein said comparative voltage produces circuit and comprises: the 6th PMOS transistor (M6), the 7th PMOS transistor (M7), the 8th PMOS transistor (M8), the 9th PMOS transistor (M9) and the first electric capacity (C1), a described PMOS transistor (M1) of described the first biasing circuit forms mirror current source with described the 6th PMOS transistor (M6), and described the first bias current (inp1) that the grid of a described PMOS transistor (M1) provides is given the grid of described the 6th PMOS transistor (M6);

The source electrode of described the 6th PMOS transistor (M6) and substrate are connected in described internal power source voltage (V _cC), the source electrode of described the 7th PMOS transistor (M7) and substrate are connected in described internal power source voltage (V _cC), the grid of described the 7th grid of PMOS transistor (M7) and the 15 PMOS transistor (M15) of described band gap comparison circuit is connected, and described the 15 PMOS transistor M15 grid produces self-bias voltage V _biasthe drain electrode of described the 7th PMOS transistor (M7) is connected with the drain electrode of described the 6th PMOS transistor (M6), the drain electrode of described the 7th PMOS transistor (M7) is connected with the source electrode of described the 8th PMOS transistor (M8), the substrate of described the 8th PMOS transistor (M8) is connected in the source electrode of described the 8th PMOS transistor (M8), and the second bias voltage (V is exported in the drain electrode of described the 6th PMOS transistor (M6) _bias2);

The grid short circuit of the transistorized drain electrode of described the 8th PMOS (M8) and described the 8th PMOS transistor (M8), the drain electrode (M8) of described the 8th PMOS pipe is connected in the source electrode of described the 9th PMOS pipe (M9), and the substrate of described the 9th PMOS pipe (M9) is connected in the source electrode of described the 9th PMOS pipe (M9);

The drain electrode of the grid of described the 9th PMOS pipe (M9) and described the 9th PMOS pipe (M9) is by the first electric capacity (C1) ground connection.

Further, described resistor voltage divider circuit comprises: the 3rd resistance (R3), and the 4th resistance (R4) and the 5th resistance (R5), wherein said the 3rd resistance (R3) one end is connected in described supply voltage (V _dD), and described the 3rd resistance (R3) other end is series at one end of described the 4th resistance (R4), between described the 3rd resistance (R3) and described the 4th resistance (R4), form described the first output voltage (V1), described the first output voltage (V1) is as the input voltage of described voltage selecting circuit;

Described the 5th resistance (R5) one end is series at the other end of described the 4th resistance (R4), and the other end ground connection of described the 5th resistance (R5), between described the 4th resistance (R4) and described the 5th resistance (R5), form described the second output voltage (V2), described the first output voltage (V2) is as the input voltage of described voltage selecting circuit.

Further, described voltage selecting circuit comprises: the 4th PMOS transistor (M4), the 5th PMOS transistor (M5) and the first inverter (INV1),

The grid of wherein said the 5th PMOS transistor (M5) is connected in the input of described the first inverter (INV1);

The grid of described the 4th PMOS transistor (M4) is connected in the output of described the first inverter (INV1);

The drain electrode of described the 4th PMOS transistor (M4) is connected with described second output voltage (V2) of described resistor voltage divider circuit;

The drain electrode of described the 5th PMOS transistor (M5) is connected with described first output voltage (V1) of described resistor voltage divider circuit;

The source electrode of described the 5th PMOS transistor (M5) is connected in the source electrode of the 4th PMOS transistor (M4), and the substrate of the substrate of described the 5th PMOS transistor (M5) and the 4th PMOS transistor (M4) is cascaded, the substrate of described the 5th PMOS transistor (M5) is connected in the source electrode of described the 5th PMOS transistor (M5), and the grid of described the 5th source electrode of PMOS transistor (M5) and the 12 PMOS transistor (M12) of described band gap comparison circuit is connected, exported the output voltage (Vin) of described voltage selecting circuit by the source electrode of described the 5th PMOS transistor (M5), described output voltage (Vin) provides input voltage as described band gap comparison circuit.

Further, described in, prevent described supply voltage (V _dD) pulse cause that the protective circuit of operation comprises: ten three PMOS transistor (M13), ten one PMOS transistor (M11) and the ten PMOS transistor (M10) in parallel with described the 12 PMOS transistor (M12) of described band gap comparison circuit

Wherein said the 11 PMOS transistor (M11) and described the tenth PMOS transistor (M10) are all connected in parallel on described internal power source voltage (V _cC) and the source electrode of described the 13 PMOS transistor (M13) between, the source electrode of wherein said the 11 PMOS transistor (M11) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the 11 PMOS transistor (M11) is connected with the source electrode of described the 13 PMOS transistor (M13), described the 11 drain electrode of PMOS transistor (M11) and the source electrode of described the 13 PMOS transistor (M13), the grid of described the 11 PMOS transistor (M11) is connected with the grid of a PMOS transistor (M1) of described the first biasing circuit, and described the 11 PMOS transistor (M11) produces the 4th image current (I of the 4th mirror current source branch road _c4);

The source electrode of described the tenth PMOS transistor (M10) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the tenth PMOS transistor (M10) is connected in the source electrode of described the 13 PMOS transistor (M13), and the drain electrode of described the tenth PMOS transistor (M10) produces the 5th image current (I of the 5th image current branch road _c5);

Described the 13 PMOS transistor (M13) drain electrode and described the 12 PMOS transistor (M12) drain electrode earth, the grid of described the 13 PMOS transistor (M13) accesses the second bias voltage (V _bias2) make comparisons with the input voltage of the grid access of described the 12 PMOS transistor (M12), the source electrode of described the 13 PMOS transistor (M13) is parallel to the source electrode of described the 12 PMOS transistor (M12), the substrate of described the 13 PMOS transistor (M13) is connected in the source electrode of described the 13 PMOS transistor (M13), the substrate of described the 12 PMOS transistor (M12) is connected in the source electrode of described the 12 PMOS transistor (M12), described the second bias voltage (V _bias2) with described input voltage relatively after by the source electrode output voltage of described the 12 PMOS transistor (M12).

Further, described band gap comparison circuit comprises: produce the band-gap reference structure of reference voltage, load circuit, second level output circuit, startup clamp circuit and the logical circuit of generation current source branch current.

Further, described logical circuit comprises Schmidt trigger (SMT) and the second inverter (INV2),

Wherein, the input of described Shi Misi trigger (SMT) is connected with the output of the drain electrode of described the 19 PMOS transistor (M19) of the described second level output circuit of described band gap comparison circuit; the UVLO signal of the described under-voltage protecting circuit of output after described the second inverter (INV2); and described the second inverter (INV2) is connected with described the first inverter (INV1), described UVLO signal feedback is given to the input of described the first inverter (INV1).

Further, described band-gap reference structure comprises: the 14 PMOS transistor (M14), the 17 PMOS transistor (M17), the first triode (Q1), the second triode (Q2), the first resistance (R1) and the second resistance (R2)

Wherein, the source electrode of described the 14 PMOS transistor (M14) and substrate are connected in described internal power source voltage (V _cC);

The drain electrode of described the 14 PMOS transistor (M14) is connected in the source electrode of described the 17 PMOS transistor (M17), and the substrate of described the 17 PMOS transistor (M17) is connected in the source electrode of described the 17 PMOS transistor (M17);

The grid of described the 14 PMOS transistor (M14) is connected with the grid of a described PMOS transistor (M1) of described the first biasing circuit, and produces the 3rd image current (I of the 3rd mirror current source branch road _c3);

The base stage of described the second triode (Q2) is connected with the source electrode of the 13 PMOS transistor (M13), and the base stage of described the second triode (Q2) is connected voltage input end as a comparison with the base stage of described the first triode (Q1);

The collector electrode of described the second triode (Q2) is connected with the drain electrode of the 15 PMOS transistor (M15) of described load circuit, produces the second image current (I of the second mirror current source branch road _c2);

The collector electrode of described the first triode (Q1) is connected with the drain electrode of the 16 PMOS transistor (M16) of described load circuit, produces the first mirror image current (I of the first mirror current source branch road _c1);

The emitter of described the second triode (Q2) is connected to the emitter of described the first triode (Q1) through described the second resistance (R2), the source electrode of the 17 PMOS transistor (M17) that the emitter of described the first triode (Q1) connects through described the first resistance (R1), the substrate of the 17 PMOS transistor (M17) is connected in the source electrode of described the 17 PMOS transistor (M17), the grid of the 17 PMOS transistor (M17) and the equal ground connection of drain electrode.

Further, the load circuit of described generation current source branch current comprises:

The 16 PMOS transistor (M16), the 15 PMOS transistor (M15) and the second electric capacity (C2);

Wherein said the 16 PMOS transistor M16 and described the 15 PMOS transistor M15 form mirror current source, the self-bias voltage V that described the 15 PMOS transistor M15 grid produces _biasbe input to the grid of the 16 PMOS transistor M16, the source electrode of described the 16 PMOS transistor (M16) and substrate are connected in described internal power source voltage (V _cC);

The source electrode of described the 15 PMOS transistor (M15) and substrate are connected in described internal power source voltage (V _cC), the grid of described the 15 PMOS transistor (M15) is connected in the drain electrode of described the 15 PMOS transistor (M15), and the grid of described the 15 PMOS transistor (M15) is connected with the grid that described comparative voltage produces the 7th PMOS transistor (M7) of circuit;

Described the 15 PMOS transistor (M15) forms mirror current source with described the tenth PMOS transistor (M10), the self-bias voltage V that described the 15 PMOS transistor M15 grid produces _biasbe input to the grid of the tenth PMOS transistor M10.

Further, described second level output circuit comprises: the 19 PMOS transistor (M19), the 20 PMOS transistor (M20), the 21 PMOS transistor (M21) and the 29 PMOS transistor (M29), wherein said the 15 PMOS transistor (M15) forms mirror current source with described the 29 PMOS transistor (M29), and the source electrode of described the 29 PMOS transistor (M29) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the 29 PMOS transistor (M29) is connected with the drain electrode of described the 20 PMOS transistor (M20), the self-bias voltage V that described the 15 PMOS transistor M15 grid produces _biasbe input to the grid of the 29 PMOS transistor M29, produce the 6th image current (I of the 6th image current branch road _c6);

Described the 20 PMOS transistor (M20) forms mirror current source with described the 21 PMOS transistor (M21), and described the 20 PMOS transistor (M20) produces the 7th image current (I _c7), the grid of described the 20 PMOS transistor (M20) is connected with the grid of described the 21 PMOS transistor (M21), the grid of described the 20 PMOS transistor (M20) is connected with the drain electrode of described the 20 PMOS transistor (M20), the source electrode of described the 20 PMOS transistor (M20) and substrate ground connection, the source electrode of described the 21 PMOS transistor (M21) and substrate ground connection, described the 20 PMOS transistor (M20) produces the 8th image current (I _c8);

The grid of described the 19 PMOS transistor (M19) is connected with the collector electrode of described first triode (Q1) of described band-gap reference structure, and the source electrode of described the 19 PMOS transistor (M19) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the 19 PMOS transistor (M19) is connected with the drain electrode of described the 21 PMOS transistor (M21), produces the output voltage of second level output circuit.

Further, described startup clamp circuit comprises: the 18 PMOS transistor (M18), the 22 PMOS transistor (M22), the 23 PMOS transistor (M23), the 24 PMOS transistor (M24), the 25 PMOS transistor (M25), the 26 PMOS transistor (M26), the 27 PMOS transistor (M27), the 28 PMOS transistor (M28), the 3rd electric capacity (C3) and the 5th electric capacity (C5)

The drain electrode of wherein said the 18 PMOS transistor (M18) is connected with the grid of described the 19 PMOS transistor (M19) of described second level output circuit, and the drain electrode of described the 19 PMOS transistor (M19) is parallel to the 5th electric capacity (C5) described in a ground connection; The source electrode of described the 18 PMOS transistor (M18) and substrate are connected in described internal power source voltage (V _cC), being connected of described the 18 grid of PMOS transistor (M18) and the drain electrode of described the 27 PMOS transistor (M27);

The source electrode of described the 22 PMOS transistor (M22) and substrate are connected in described internal power source voltage (V _cC), the grid of the PMOS transistor (M1) that the grid of described the 22 PMOS transistor (M22) is connected with described the first biasing circuit connects, and the drain electrode of described the 22 PMOS transistor (M22) is connected with the source electrode of described the 25 PMOS transistor (M25);

The substrate of described the 25 PMOS transistor (M25) is connected in described internal power source voltage (V _cC), the drain electrode of described the 25 PMOS transistor (M25) is connected with the drain electrode of described the 26 PMOS transistor (M26), the drain electrode of described the 25 PMOS transistor (M25) is connected with the grid of described the 23 PMOS transistor (M23), the grid of described the 25 PMOS transistor (M25) is connected with the grid of described the 26 PMOS transistor (M26), and the grid of described the 26 PMOS transistor (M26) is by described the 3rd electric capacity (C3) ground connection;

The source electrode of described the 26 PMOS transistor (M26) and substrate ground connection;

The drain electrode of described the 23 PMOS transistor (M23) is parallel to the drain electrode of described the 19 PMOS transistor (M19) of described second level output, the substrate ground connection of described the 23 PMOS transistor (M23), the source electrode of described the 23 PMOS transistor (M23) is connected with the drain electrode of described the 24 PMOS transistor (M24);

The source electrode of described the 24 PMOS transistor (M24) and substrate ground connection, the grid of described the 24 PMOS transistor (M24) is connected with the grid of described the 2nd PMOS transistor M2 of described the first biasing circuit;

The source electrode of described the 27 PMOS transistor (M27) and substrate are connected in described internal power source voltage (V _cC), the grid of described the 27 PMOS transistor (M27) is connected with the grid that described comparative voltage produces described the 7th PMOS transistor (M7) of circuit, the drain electrode of described the 27 PMOS transistor (M27) is connected with described the 28 PMOS transistor (M28) drain electrode, and the grid of described the 26 PMOS transistor (M26) is parallel to described the 28 PMOS transistor (M28) drain electrode;

The source electrode of described the 28 PMOS transistor (M28) and substrate ground connection, the grid of described the 28 PMOS transistor (M28) is connected with the grid of a PMOS transistor M2 described in described the first biasing circuit.

The beneficial effect of technique scheme of the present invention is as follows:

In the solution of the present invention, produce two magnitudes of voltage by resistor voltage divider circuit, select the input voltage of a magnitude of voltage as band gap comparison circuit by voltage selecting circuit, by recently preventing that the pulse of supply voltage from causing operation mutually with the magnitude of voltage of protective circuit, produce after a under-voltage protecting circuit UVLO signal by band gap comparison circuit simultaneously, return to UVLO signal and monitor the low and high level of UVLO signal by feedback control loop, the fail safe starting with protection subsequent module, realized like this function of band-gap reference circuit and comparator by band gap comparison circuit, optimizing circuit structure, dwindle circuit area, when reducing power consumption, also accelerate the response speed of circuit.The DC chopper DC/DC controller power source voltage that to realize PoE interface and fixing DC voltage conversion be variable direct voltage is monitored, simultaneously in order to realize high conversion efficiency and to obtain with all very little turnover door voltage limits of the variation of input voltage and temperature.

Brief description of the drawings

Fig. 1 is the general under-voltage protecting circuit figure of prior art;

Fig. 2 is the electric current I of the embodiment of the present invention _c1, electric current I _c2with input voltage V _dgraph of a relation;

Fig. 3 is the schematic block diagram of the under-voltage protecting circuit of the embodiment of the present invention;

Fig. 4 is the circuit diagram of the under-voltage protecting circuit of the embodiment of the present invention.

Description of reference numerals:

1-resistor voltage divider circuit, 2-voltage selecting circuit, 3-band gap comparison circuit, 31-band-gap reference structure, 32-logical circuit, 4-biasing circuit.

Embodiment

For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.

The present invention is directed to traditional under-voltage circuit in prior art and use independently reference voltage source and comparator; cause the response time longer; the large and large problem of power consumption of area occupied; a kind of under-voltage protecting circuit for Power over Ethernet is provided; by having, comparator and reference voltage source are made to band gap comparison circuit 3 circuit, make under-voltage protecting circuit there is reversal rate faster, and power consumption is very low; and by the existence of protective circuit, prevent supply voltage V _dDpulse causes misoperation.

It should be noted that V of the present invention _dDfor chip external power supply pin, V _dDproduce internal power source voltage V through inner low pressure source generating circuit _cC.

As shown in Figures 2 to 4, the under-voltage protecting circuit for Power over Ethernet that the embodiment of the present invention provides, wherein, comprising:

For regulating the resistor voltage divider circuit 1 of turnover door voltage limit, and produce the first output voltage and the second output voltage;

Voltage selecting circuit 2, is connected with described resistor voltage divider circuit 1, selects a magnitude of voltage from described the first output voltage and described the second output voltage;

Band gap comparison circuit 3, be connected with described voltage selecting circuit 2, the magnitude of voltage of protective circuit that causes operation for described magnitude of voltage that described voltage selecting circuit 2 is selected or using the pulse that prevents supply voltage, as input voltage, produces a under-voltage protecting circuit UVLO signal;

Be arranged at the feedback control circuit between described resistor voltage divider circuit 1 and described band gap comparison circuit 3, for in the time that described UVLO signal is output as high level, described UVLO signal is through described voltage selecting circuit 2, export higher described the first output voltage, when described UVLO signal is output as low level, export lower described the second output voltage.

Described voltage selecting circuit 2 selects the magnitude of voltage of protective circuit that the magnitude of voltage of resistor voltage divider circuit 1 or selection prevent that the pulse of supply voltage from causing operation as the input voltage of band gap comparison circuit 3, produce after under-voltage protecting circuit UVLO signal, by feedback control loop, UVLO signal is returned to voltage selecting circuit 2, then voltage selecting circuit 2 can be selected the first output voltage that magnitude of voltage is higher or export the input of the second lower output voltage as band gap comparison circuit 3, and in the time that the output under-voltage protecting circuit UVLO of band gap comparison circuit 3 signal is low level, chip internal basic module does not start, play the object of under-voltage protection, in the time that the output under-voltage protecting circuit UVLO of band gap comparison circuit 3 signal is high level, chip enable, inner basic module starts.Like this comparator is combined with reference voltage source, the band gap comparison circuit 3 of composition, circuit structure is obviously simplified, and has reduced area, has reduced cost; Again through over under-voltage protection circuit turnover door voltage limit adjustable and warm float little; When supply voltage occurs when under-voltage, not producing reference voltage, a large amount of stand-by power consumptions are saved.

In order to power to band gap comparison circuit 3, the therefore under-voltage protecting circuit for Power over Ethernet of the embodiment of the present invention, also comprises:

Biasing circuit 4, wherein said biasing circuit 4 comprises: the first biasing circuit and comparative voltage produce circuit;

Wherein said the first biasing circuit comprises: the 30 PMOS transistor M0, the 2nd PMOS transistor M2, the 3rd PMOS transistor M3, a PMOS transistor (M1) and the 4th capacitor C 4, wherein said the 30 PMOS transistor M0 grounded-grid, source electrode and the substrate of described the 30 PMOS transistor M0 are connected in internal power source voltage V _cC, the drain electrode of described the 30 PMOS transistor M0 is connected with the drain electrode of described the 2nd PMOS transistor M2, and the drain electrode of described the 2nd PMOS transistor M2 is connected on the grid of described the 2nd PMOS transistor M2; The grounded-grid of wherein said the 30 PMOS transistor M0, source electrode and substrate are connected in supply voltage V _cC, described the 30 PMOS transistor M0 is in normal open state;

The source electrode of described the 2nd PMOS transistor M2 and substrate ground connection;

The source electrode of described the 3rd PMOS transistor M3 and substrate ground connection;

The grid of described the 3rd PMOS transistor M3 is by the 4th capacitor C 4 ground connection, and the grid of described the 2nd PMOS transistor M2 and the transistorized grid M3 of described the 3rd PMOS provide the first bias current inp1 for described band gap comparison circuit 3;

The grid of described the 2nd PMOS transistor M2 is connected with the grid of a described PMOS transistor M1 by diode, the drain electrode of a described PMOS transistor M1 is connected with the drain electrode of described the 3rd PMOS transistor M3, and the source electrode of a described PMOS transistor M1 and substrate are connected in described internal power source voltage V _cC, the grid of a described PMOS transistor M1 provides described the first bias current inp1;

Wherein said comparative voltage produces circuit and comprises: the 6th PMOS transistor M6, the 7th PMOS transistor M7, the 8th PMOS transistor M8, the 9th PMOS transistor M9 and the first capacitor C 1, a described PMOS transistor M1 of described the first biasing circuit and described the 6th PMOS transistor M6 form mirror current source, and described the first bias current inp1 that the grid of a described PMOS transistor M1 provides is to the grid of described the 6th PMOS transistor M6;

The source electrode of described the 6th PMOS transistor M6 and substrate are connected in described internal power source voltage V _cC, the source electrode of described the 7th PMOS transistor M7 and substrate are connected in described internal power source voltage V _cC, the grid of described the 7th grid of PMOS transistor (M7) and the 15 PMOS transistor (M15) of described band gap comparison circuit 3 is connected, and described the 15 PMOS transistor M15 grid produces self-bias voltage V _biasthe drain electrode of described the 7th PMOS transistor M7 is connected with the drain electrode of described the 6th PMOS transistor M6, the drain electrode of described the 7th PMOS transistor M7 is connected with the source electrode of described the 8th PMOS transistor M8, the substrate of described the 8th PMOS transistor M8 is connected in the source electrode of described the 8th PMOS transistor M8, and the second bias voltage V is exported in the drain electrode of described the 6th PMOS transistor M6 _bias2;

The grid short circuit of described the 8th PMOS transistorized drain electrode M8 and described the 8th PMOS transistor M8, the drain electrode M8 of described the 8th PMOS pipe is connected in the source electrode of described the 9th PMOS pipe M9, and the substrate of described the 9th PMOS pipe M9 is connected in the source electrode of described the 9th PMOS pipe M9;

The drain electrode of the grid of described the 9th PMOS pipe M9 and described the 9th PMOS pipe M9 is by the first capacitor C 1 ground connection.

Above-mentioned when after chip power, the 6th PMOS transistor M6 mirror current source charges to fast the first capacitor C 1, when band gap comparison circuit 3 starts, and the 7th PMOS transistor M7 conducting, after the electric current charging to the first capacitor C 1 increases, the second bias voltage V _bias2charging more fast.If supply voltage V _dDthat rises is slow, the second bias voltage V so _bias2voltage rise specific output voltage Vin fast, V _dcontrolled by output voltage V in, overturn point is controlled by output voltage V in; But as supply voltage V _dDproduce a pulse, supply voltage V _dDrise rapidly, ratio the second bias voltage V that output voltage V in rises _bias2hurry up, so now, V _dvoltage by the second bias voltage V _bias2determine, in the time that it rises to certain fixed value, band gap comparison circuit 3 is overturn, trailing edge is also so, has therefore prevented supply voltage V _dDcause misoperation because of pulse.

For the supply voltage V that samples _dD, the therefore under-voltage protecting circuit for Power over Ethernet of the embodiment of the present invention, described resistor voltage divider circuit 1 comprises: the 3rd resistance R 3, the four resistance R 4 and the 5th resistance R 5, wherein said the 3rd resistance R 3 one end are connected in described supply voltage V _dD, and described the 3rd resistance R 3 other ends are series at one end of described the 4th resistance R 4, between described the 3rd resistance R 3 and described the 4th resistance R 4, form described the first output voltage V 1, and described the first output voltage V 1 is as the input voltage of described voltage selecting circuit 2;

Described the 5th resistance R 5 one end are series at the other end of described the 4th resistance R 4, and the other end ground connection of described the 5th resistance R 5, between described the 4th resistance R 4 and described the 5th resistance R 5, form described the second output voltage V 2, described the first output voltage V 2 is as the input voltage of described voltage selecting circuit 2.

Divider resistance by regulating resistance bleeder circuit 1 also can regulate and spin upside down threshold voltage, and the output signal U VLO of band gap comparison circuit 3 turns back to again voltage selecting circuit 2; In the time that UVLO signal overturns, voltage selecting circuit 2 is upset thereupon also, and from divider resistance, the signal Vin of output also changes thereupon, and this signal is the input signal of UVLO circuit, can be also V _dDthe Vin of the dividing potential drop of signal, therefore turnover door voltage limit changes thereupon.

The under-voltage protecting circuit for Power over Ethernet of another embodiment of the present invention, described voltage selecting circuit 2 comprises: the 4th PMOS transistor M4, the 5th PMOS transistor M5 and the first inverter INV1,

The grid of wherein said the 5th PMOS transistor M5 is connected in the input of described the first inverter INV1;

The grid of described the 4th PMOS transistor M4 is connected in the output of described the first inverter INV1;

The drain electrode of described the 4th PMOS transistor M4 is connected with described second output voltage V 2 of described resistor voltage divider circuit 1;

The drain electrode of described the 5th PMOS transistor M5 is connected with described first output voltage V 1 of described resistor voltage divider circuit 1;

The source electrode of described the 5th PMOS transistor M5 is connected in the source electrode of the 4th PMOS transistor M4, and the substrate of the substrate of described the 5th PMOS transistor M5 and the 4th PMOS transistor M4 is cascaded, the substrate of described the 5th PMOS transistor M5 is connected in the source electrode of described the 5th PMOS transistor M5, and the grid of described the 5th source electrode of PMOS transistor M5 and the 12 PMOS transistor M12 of described band gap comparison circuit 3 is connected, exported the output voltage (Vin) of described voltage selecting circuit by the source electrode of described the 5th PMOS transistor M5, described output voltage (Vin) provides input voltage as described band gap comparison circuit 3.

In order to prevent described supply voltage V _dDpulse cause operation, the therefore under-voltage protecting circuit for Power over Ethernet of the embodiment of the present invention, described in prevent described supply voltage V _dDpulse cause that the protective circuit of operation comprises: ten three PMOS transistor M13, ten one PMOS transistor (M11) and the ten PMOS transistor (M10) in parallel with described the 12 PMOS transistor M12 of described band gap comparison circuit 3

Wherein said the 11 PMOS transistor (M11) and described the tenth PMOS transistor (M10) are all connected in parallel on described internal power source voltage (V _cC) and the source electrode of described the 13 PMOS transistor (M13) between, the source electrode of wherein said the 11 PMOS transistor (M11) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the 11 PMOS transistor (M11) is connected with the source electrode of described the 13 PMOS transistor (M13), described the 11 drain electrode of PMOS transistor (M11) and the source electrode of described the 13 PMOS transistor (M13), the grid of described the 11 PMOS transistor (M11) is connected with the grid of a PMOS transistor (M1) of described the first biasing circuit, and described the 11 PMOS transistor (M11) produces the 4th image current (I of the 4th mirror current source branch road _c4);

The source electrode of described the tenth PMOS transistor (M10) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the tenth PMOS transistor (M10) is connected in the source electrode of described the 13 PMOS transistor (M13), and the drain electrode of described the tenth PMOS transistor (M10) produces the 5th image current (I of the 5th image current branch road _c5); Wherein said the tenth PMOS transistor M10 has accelerated supply voltage band gap comparison circuit 3 level reversal rates while arriving rising threshold voltage, has reduced the response time of comparator, and the bias current that described the 11 PMOS transistor M11 provides is the 4th image current I _c4.

Described the 13 PMOS transistor M13 drain electrode and described the 12 PMOS transistor M12 drain electrode earth, the grid of described the 13 PMOS transistor M13 accesses the second bias voltage V _bias2make comparisons with the input voltage that the grid of described the 12 PMOS transistor M12 accesses, the source electrode of described the 13 PMOS transistor M13 is parallel to the source electrode of described the 12 PMOS transistor M12, the substrate of described the 13 PMOS transistor M13 is connected in the source electrode of described the 13 PMOS transistor M13, the substrate of described the 12 PMOS transistor M12 is connected in the source electrode of described the 12 PMOS transistor M12, described the second bias voltage V _bias2with described input voltage relatively after by the source electrode output voltage of described the 12 PMOS transistor M12.

The present invention is not directly inputted to band gap comparison circuit 3 by resistor voltage divider circuit 1 output, but it is first input to the 12 PMOS transistor M12, because the 12 PMOS transistor M12 is source follower, and the level of lifting input signal, the voltage V that D is ordered _dalong with supply voltage V _dDincrease and increase, like this because input voltage is first input to the 12 PMOS pipe M12, by the principle of source class follower, V _d=Vin+V _gS12, represent that input voltage, by after M12, has boosted, therefore by the overturn point prerequisite of UVLO circuit, reduce cut-in voltage V _{uVLO_R}value, make supply voltage V _dDafter powering on, start fast.

The 13 PMOS pipe M13 by with the comparison of input voltage, prevent supply voltage V _dDpulse causes misoperation.

Due to the present invention, reference voltage source is combined with comparator and forms band gap comparison circuit 3 circuit; therefore the under-voltage protecting circuit for Power over Ethernet of the embodiment of the present invention, described band gap comparison circuit 3 comprises: produce the band-gap reference structure 31 of reference voltage, load circuit, second level output circuit, startup clamp circuit and the logical circuit 32 of generation current source branch current.

Wherein said logical circuit 32 comprises Schmidt trigger SMT and the second inverter INV2; wherein; the input of described Shi Misi trigger SMT is connected with the output of the drain electrode of described the 19 PMOS transistor M19 of the described second level output circuit of described band gap comparison circuit 3; after described the second inverter INV2, export the UVLO signal of described under-voltage protecting circuit; and described the second inverter INV2 is connected with described the first inverter INV1, described UVLO signal feedback is given to the input of described the first inverter INV1.

Wherein said band-gap reference structure 31 comprises: the 14 PMOS transistor M14, the 17 PMOS transistor M17, the first triode Q1, the second triode Q2, the first resistance R 1 and the second resistance R 2,

Wherein, the source electrode of described the 14 PMOS transistor M14 and substrate are connected in described internal power source voltage V _cC;

The drain electrode of described the 14 PMOS transistor M14 is connected in the source electrode of described the 17 PMOS transistor M17, and the substrate of described the 17 PMOS transistor M17 is connected in the source electrode of described the 17 PMOS transistor M17;

The grid of described the 14 PMOS transistor M14 is connected with the grid of a described PMOS transistor M1 of described the first biasing circuit, and produces the 3rd image current I of the 3rd mirror current source branch road _c3;

The base stage of described the second triode Q2 is connected with the source electrode of the 13 PMOS transistor M13, and the base stage of described the second triode Q2 is connected voltage input end as a comparison with the base stage of described the first triode Q1;

The collector electrode of described the second triode Q2 is connected with the drain electrode of the 15 PMOS transistor M15 of described load circuit, produces the second image current I of the second mirror current source branch road _c2;

The collector electrode of described the first triode Q1 is connected with the drain electrode of the 16 PMOS transistor M16 of described load circuit, produces the first mirror image current I of the first mirror current source branch road _c1;

The emitter of described the second triode Q2 is connected to the emitter of described the first triode Q1 through described the second resistance R 2, the source electrode of the 17 PMOS transistor M17 that the emitter of described the first triode Q1 connects through described the first resistance R 1, the substrate of the 17 PMOS transistor M17 is connected in the source electrode of described the 17 PMOS transistor M17, the grid of the 17 PMOS transistor M17 and the equal ground connection of drain electrode.

Form the core texture of band gap comparison circuit 3 by the 14 PMOS transistor M14, the 17 PMOS transistor M17, the second triode Q2, the first triode Q1, the second resistance R 2 and the first resistance R 1, produce reference voltage, also can greatly accelerate supply voltage band gap comparison circuit 3 level reversal rates while arriving rising threshold value through the circuit of optimizing, reduce the response time of comparator simultaneously.

As shown in Figure 2, i _c1, i _c2with input voltage V _drelation.When circuit has just powered on, V _dDvoltage slowly rises, at the beginning V _dvoltage is less than band gap comparison circuit 3 turnover door voltage limit V _tH(I _c1=I _c2time V _dvalue), I _c2be greater than I _c1, therefore A point voltage is higher than B point voltage, UVLO signal output low level; As signal V _dfrom low while increasing gradually, current i _c1, i _c2all increase i _c2the slope of curve compares i _c1the slope of curve is little, works as V _dDrise to V _{uVLO_R}, work as V _dreach the upset thresholding V of band-gap reference comparator _tHtime, i _c1=i _c2, A point voltage equates with B point voltage, is now the critical condition of upset; In the time of the critical condition of upset, Δ V _bE=V _bE1-V _bE2=i _c2r2=V _tln (4), V _bE1, V _bE2be respectively the transmitter-base voltage of the first triode Q1, the second triode Q2 pipe, separate i _c2=V _tln (4)/R2, the electric current of establishing again M14 is i _c3so in the time of overturn point, flowing through the electric current that C orders is 2i _c2+ i _c3, in the time of overturn point critical condition, be not to have I _c1, I _c2two-way electric current, now I _c1=I _c2, add I _c3branch current.Can learn thus, the voltage that C is ordered is:

$V_C=\sqrt{\frac{2({2i}_{c2}+i_{c3})}{{\mathrm{\μ}}_p{C}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_{2237}}}+\left|V_{\mathrm{THP}}\right|---\left(1\right)$

Wherein, i _c2=V _tln (4)/R2, i _c3it is current mirror image current.

The base voltage of the first triode Q1 is exactly turnover door voltage limit V _tH,

$V_{\mathrm{TH}}=V_{\mathrm{BE}1}+{2i}_{c2}R1+\sqrt{\frac{2({2i}_{c2}+i_{c3})}{{\mathrm{\μ}}_p{C}_{\mathrm{ox}}{\left(\frac{W}{L}\right)}_{17}}}+\left|V_{\mathrm{THP}}\right|---\left(2\right)$

Wherein, i _c2=V _tln (4)/R2, i _c3it is current mirror image current.

So the turnover door voltage limit of band gap comparison circuit 3 just equals V _tH, in formula (2), i _c3negative temperature coefficient, but 2i _c2+ i _c3be positive temperature coefficient, and in (2), Section 1 is V _bE1negative temperature coefficient, latter three is positive temperature coefficient, therefore through reasonably regulating the turnover door voltage limit that just can obtain with temperature, independent of power voltage.

Work as V _dDbe greater than V _{uVLO_R}, UVLO signal upset output high level.Wherein i _c2the slope of curve compares i _c1the reason that the slope of curve is little is voltage V _dbe transported to the base stage of the first triode Q1, the second triode Q2, in band-gap reference structure 31, the emitter area of getting the first triode Q1 and the second triode Q2 is than being 1:4, and two transistorized mutual conductance relations are so:

4gm1＝gm2 (1)

Due to the emitter-base bandgap grading feedback effect of the first resistance R 1 and the second resistance R 2, so the equivalent transconductance of the first triode Q1 and the second triode Q2 is:

$G_{m2}=\frac{g_{m2}}{1+g_{m2}(R1+R2)}---\left(2\right)$

By g in (2) formula _m2with (1) formula substitution arrangement:

$G_{m2}=\frac{g_{m1}}{\frac{1}{4}+g_{m1}(R1+R2)}=\frac{g_{m1}}{1+g_{m1}R1+g_{m1}R2+\frac{1}{4}-1}---\left(3\right)$

And

$G_{m1}=\frac{g_{m1}}{1+g_{m1}{R1}_{}}---\left(4\right)$

General gm1R2 > > 1, the Gm1 > Gm2 of selecting.So, as the supply voltage V of chip _dDwhen fluctuation, the collector current I of the first triode Q1 _c1with respect to the collector current I of the second triode Q2 _c2it is large that variable quantity is wanted.Therefore I at the beginning, _c2be greater than I _c1, and M15, M16 breadth length ratio are the same, are therefore greater than the pressure drop by M16 by the pressure drop of M15, and therefore B point voltage is less than A point.

Exactly because Gm1 > Gm2, so the collector current I of the first triode Q1 _c1with respect to the collector current I of the second triode Q2 _c2it is large that variable quantity is wanted, therefore in the time that their base stage is inputted identical voltage, and I _c2slope ratio I _c1slope little.

The under-voltage protecting circuit for Power over Ethernet of another embodiment of the present invention, the load circuit of described generation current source branch current comprises:

The 16 PMOS transistor (M16), the 15 PMOS transistor M15 and the second capacitor C 2;

Wherein said the 16 PMOS transistor M16 and described the 15 PMOS transistor M15 form mirror current source, the self-bias voltage V that described the 15 PMOS transistor M15 grid produces _biasbe input to the grid of the 16 PMOS transistor M16, the source electrode of described the 16 PMOS transistor M16 and substrate are connected in described internal power source voltage V _cC;

The source electrode of described the 15 PMOS transistor M15 and substrate are connected in described internal power source voltage V _cC, the grid of described the 15 PMOS transistor M15 is connected in the drain electrode of described the 15 PMOS transistor M15, and the grid of described the 15 PMOS transistor M15 is connected with the grid that described comparative voltage produces the 7th PMOS transistor M7 of circuit;

Described the 15 PMOS transistor M15 and described the tenth PMOS transistor M10 form mirror current source, the self-bias voltage V that described the 15 PMOS transistor M15 grid produces _biasbe input to the grid of the tenth PMOS transistor M10.

As shown in Figure 4, when band gap comparison circuit 3 starts, after the 15 PMOS transistor M15 branch road conducting, the voltage V that its automatic biasing produces _biasbe input to the grid of the tenth PMOS transistor M10, composition mirror, its image current source image is given the tenth PMOS transistor M10, and the tenth PMOS transistor M10 conducting, has accelerated V _drising, accelerated again supply voltage band gap comparison circuit 3 level reversal rates while arriving rising threshold value, accelerated the upset of this band gap comparison circuit 3, greatly reduced the response time of comparator.

The under-voltage protecting circuit for Power over Ethernet of another embodiment of the present invention; described second level output circuit comprises: the 19 PMOS transistor M19, the 20 PMOS transistor M20, the 21 PMOS transistor M21 and the 29 PMOS transistor M29; wherein said the 15 PMOS transistor M15 and described the 29 PMOS transistor M29 form mirror current source, and the source electrode of described the 29 PMOS transistor M29 and substrate are connected in described internal power source voltage V _cC, the drain electrode of described the 29 PMOS transistor M29 is connected with the drain electrode of described the 20 PMOS transistor M20, the self-bias voltage V that the 15 PMOS transistor M15 grid produces _biasbe input to the grid of the 29 PMOS transistor M29, produce the 6th image current I of the 6th image current branch road _c6;

Described the 20 PMOS transistor M20 and described the 21 PMOS transistor M21 form mirror current source, and described the 20 PMOS transistor M20 produces the 7th image current I _c7the grid of described the 20 PMOS transistor M20 is connected with the grid of described the 21 PMOS transistor M21, the grid of described the 20 PMOS transistor M20 is connected with the drain electrode of described the 20 PMOS transistor M20, the source electrode of described the 20 PMOS transistor M20 and substrate ground connection, the source electrode of described the 21 PMOS transistor M21 and substrate ground connection, described the 20 PMOS transistor M20 produces the 8th image current I _c8;

The collector electrode of described the 19 grid of PMOS transistor M19 and the described first triode Q1 of described band-gap reference structure 31 is connected, and the source electrode of described the 19 PMOS transistor M19 and substrate are connected in described internal power source voltage V _cC, the drain electrode of described the 19 PMOS transistor M19 is connected with the drain electrode of described the 21 PMOS transistor M21, produces the output voltage of second level output circuit.

The under-voltage protecting circuit for Power over Ethernet of another embodiment of the present invention; described startup clamp circuit comprises: the 18 PMOS transistor M18; the 22 PMOS transistor M22, the 23 PMOS transistor M23, the 24 PMOS transistor M24; the 25 PMOS transistor M25; the 26 PMOS transistor M26, the 27 PMOS transistor M27, the 28 PMOS transistor M28; the 3rd capacitor C 3 and the 5th capacitor C 5

The drain electrode of wherein said the 18 PMOS transistor M18 is connected with the grid of described the 19 PMOS transistor M19 of described second level output circuit, and the drain electrode of described the 19 PMOS transistor M19 is parallel to the 5th capacitor C 5 described in a ground connection; The source electrode of described the 18 PMOS transistor M18 and substrate are connected in described internal power source voltage V _cC, being connected of described the 18 grid of PMOS transistor M18 and the drain electrode of described the 27 PMOS transistor M27;

The source electrode of described the 22 PMOS transistor M22 and substrate are connected in described internal power source voltage V _cC, the grid of the PMOS transistor M1 that the grid of described the 22 PMOS transistor M22 is connected with described the first biasing circuit connects, and the drain electrode of described the 22 PMOS transistor M22 is connected with the source electrode of described the 25 PMOS transistor M25;

The substrate of described the 25 PMOS transistor M25 is connected in described internal power source voltage V _cCthe drain electrode of described the 25 PMOS transistor M25 is connected with the drain electrode of described the 26 PMOS transistor M26, the drain electrode of described the 25 PMOS transistor M25 is connected with the grid of described the 23 PMOS transistor M23, the grid of described the 25 PMOS transistor M25 is connected with the grid of described the 26 PMOS transistor M26, and the grid of described the 26 PMOS transistor M26 is by described the 3rd capacitor C 3 ground connection;

The source electrode of described the 26 PMOS transistor M26 and substrate ground connection;

The drain electrode of described the 23 PMOS transistor M23 is parallel to the drain electrode of described the 19 PMOS transistor M19 of described second level output, the substrate ground connection of described the 23 PMOS transistor M23, the source electrode of described the 23 PMOS transistor M23 is connected with the drain electrode of described the 24 PMOS transistor M24;

The source electrode of described the 24 PMOS transistor M24 and substrate ground connection, the grid of described the 24 PMOS transistor M24 is connected with the grid of described the 2nd PMOS transistor M2 of described the first biasing circuit;

The source electrode of described the 27 PMOS transistor M27 and substrate are connected in described internal power source voltage V _cCthe grid of described the 27 PMOS transistor M27 is connected with the grid that described comparative voltage produces described the 7th PMOS transistor M7 of circuit, the drain electrode of described the 27 PMOS transistor M27 is connected with described the 28 PMOS transistor M28 drain electrode, and the grid of described the 26 PMOS transistor M26 is parallel to described the 28 PMOS transistor M28 drain electrode;

The source electrode of described the 28 PMOS transistor M28 and substrate ground connection, the grid of described the 28 PMOS transistor M28 is connected with the grid of the 2nd PMOS transistor M2 described in described the first biasing circuit.

In the time that circuit just powers on, the 24 PMOS transistor M24, the 28 PMOS transistor the 28 PMOS transistor M28 are mirrored conducting, the 27 not conducting of PMOS transistor M27, VF is low level so, therefore the 18 PMOS transistor M18, the 23 PMOS transistor M23, the 25 PMOS transistor M25 conducting, forcing A point voltage is high level, and the second level output voltage that E is ordered is low level, and it is low level that its object is forced output signal U VLO exactly.

The branch pressure voltage output V of resistor voltage divider circuit 1 _dthe comparative voltage input that is connected to band gap comparison circuit 3, the output of band gap comparison circuit 3 is passed to the input of logical circuit 32, exports the output UVLO of under-voltage protecting circuit after the shaping of logical circuit 32; UVLO signal feeds back to again resistor voltage divider circuit 1, and when band gap comparison circuit 3 is exported high level, resistor voltage divider circuit 1 is through the higher branch pressure voltage of either-or switch output of voltage selecting circuit 2.Thereby realize, PoE interface and DC/DC controller power source voltage are monitored, realized high conversion efficiency simultaneously and obtain with all very little turnover door voltage limits of the variation of input voltage and temperature.Band gap comparison circuit 3 has been realized the function of band-gap reference circuit and comparator, has not only optimized circuit structure but also has dwindled circuit area, reduced power consumption simultaneously, has also accelerated the response speed of circuit.

The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (11)

1. for a under-voltage protecting circuit for Power over Ethernet, it is characterized in that, comprising:

For regulating the resistor voltage divider circuit of turnover door voltage limit, and produce the first output voltage and the second output voltage;

Voltage selecting circuit, is connected with described resistor voltage divider circuit, selects a magnitude of voltage from described the first output voltage and described the second output voltage;

Band gap comparison circuit, be connected with described voltage selecting circuit, the magnitude of voltage of protective circuit that causes operation for described magnitude of voltage that described voltage selecting circuit is selected or using the pulse that prevents supply voltage, as input voltage, produces a under-voltage protecting circuit UVLO signal;

Be arranged at the feedback control loop between described resistor voltage divider circuit and described band gap comparison circuit, for in the time that described UVLO signal is output as high level, described UVLO signal is through described voltage selecting circuit, export higher described the first output voltage, when described UVLO signal is output as low level, export lower described the second output voltage.

2. the under-voltage protecting circuit for Power over Ethernet according to claim 1, is characterized in that, also comprises: biasing circuit, and wherein said biasing circuit comprises: the first biasing circuit and comparative voltage produce circuit;

Wherein said the first biasing circuit comprises: the 30 PMOS transistor (M0), the 2nd PMOS transistor (M2), the 3rd PMOS transistor (M3), a PMOS transistor (M1) and the 4th electric capacity (C4)

Wherein said the 30 PMOS transistor (M0) grounded-grid, source electrode and the substrate of described the 30 PMOS transistor (M0) are connected in internal power source voltage (V _cC), the drain electrode of described the 30 PMOS transistor (M0) is connected with the drain electrode of described the 2nd PMOS transistor (M2), and the drain electrode of described the 2nd PMOS transistor (M2) is connected on the grid of described the 2nd PMOS transistor (M2);

The source electrode of described the 2nd PMOS transistor (M2) and substrate ground connection;

The source electrode of described the 3rd PMOS transistor (M3) and substrate ground connection;

The grid of described the 3rd PMOS transistor (M3) is by described the 4th electric capacity (C4) ground connection, and the grid of described the 2nd PMOS transistor (M2) and the transistorized grid of described the 3rd PMOS (M3) provide the first bias current (inp1) for described band gap comparison circuit;

The grid of described the 2nd PMOS transistor (M2) is connected with the grid of a described PMOS transistor (M1) by diode, the drain electrode of a described PMOS transistor (M1) is connected with the drain electrode of described the 3rd PMOS transistor (M3), and the source electrode of a described PMOS transistor (M1) and substrate are connected in described internal power source voltage (V _cC), the grid of a described PMOS transistor (M1) provides described the first bias current (inp1);

Wherein said comparative voltage produces circuit and comprises: the 6th PMOS transistor (M6), the 7th PMOS transistor (M7), the 8th PMOS transistor (M8), the 9th PMOS transistor (M9) and the first electric capacity (C1), a described PMOS transistor (M1) of described the first biasing circuit forms mirror current source with described the 6th PMOS transistor (M6), and described the first bias current (inp1) that the grid of a described PMOS transistor (M1) provides is given the grid of described the 6th PMOS transistor (M6);

The source electrode of described the 6th PMOS transistor (M6) and substrate are connected in described internal power source voltage (V _cC), the source electrode of described the 7th PMOS transistor (M7) and substrate are connected in described internal power source voltage (V _cC), the grid of described the 7th grid of PMOS transistor (M7) and the 15 PMOS transistor (M15) of described band gap comparison circuit is connected, and described the 15 PMOS transistor M15 grid produces self-bias voltage V _bias), the drain electrode of described the 7th PMOS transistor (M7) is connected with the drain electrode of described the 6th PMOS transistor (M6), the drain electrode of described the 7th PMOS transistor (M7) is connected with the source electrode of described the 8th PMOS transistor (M8), the substrate of described the 8th PMOS transistor (M8) is connected in the source electrode of described the 8th PMOS transistor (M8), and the second bias voltage (V is exported in the drain electrode of described the 6th PMOS transistor (M6) _bias2);

The grid short circuit of the transistorized drain electrode of described the 8th PMOS (M8) and described the 8th PMOS transistor (M8), the drain electrode (M8) of described the 8th PMOS pipe is connected in the source electrode of described the 9th PMOS pipe (M9), and the substrate of described the 9th PMOS pipe (M9) is connected in the source electrode of described the 9th PMOS pipe (M9);

The drain electrode of the grid of described the 9th PMOS pipe (M9) and described the 9th PMOS pipe (M9) is by the first electric capacity (C1) ground connection.

3. the under-voltage protecting circuit for Power over Ethernet according to claim 1; it is characterized in that; described resistor voltage divider circuit comprises: the 3rd resistance (R3); the 4th resistance (R4) and the 5th resistance (R5), wherein said the 3rd resistance (R3) one end is connected in described supply voltage (V _dD), and described the 3rd resistance (R3) other end is series at one end of described the 4th resistance (R4), between described the 3rd resistance (R3) and described the 4th resistance (R4), form described the first output voltage (V1), described the first output voltage (V1) is as the input voltage of described voltage selecting circuit;

Described the 5th resistance (R5) one end is series at the other end of described the 4th resistance (R4), and the other end ground connection of described the 5th resistance (R5), between described the 4th resistance (R4) and described the 5th resistance (R5), form described the second output voltage (V2), described the first output voltage (V2) is as the input voltage of described voltage selecting circuit.

4. the under-voltage protecting circuit for Power over Ethernet according to claim 1; it is characterized in that; described voltage selecting circuit comprises: the 4th PMOS transistor (M4), the 5th PMOS transistor (M5) and the first inverter (INV1)

The grid of wherein said the 5th PMOS transistor (M5) is connected in the input of described the first inverter (INV1);

The grid of described the 4th PMOS transistor (M4) is connected in the output of described the first inverter (INV1);

The drain electrode of described the 4th PMOS transistor (M4) is connected with described second output voltage (V2) of described resistor voltage divider circuit;

The drain electrode of described the 5th PMOS transistor (M5) is connected with described first output voltage (V1) of described resistor voltage divider circuit;

The source electrode of described the 5th PMOS transistor (M5) is connected in the source electrode of the 4th PMOS transistor (M4), and the substrate of the substrate of described the 5th PMOS transistor (M5) and the 4th PMOS transistor (M4) is cascaded, the substrate of described the 5th PMOS transistor (M5) is connected in the source electrode of described the 5th PMOS transistor (M5), and the grid of described the 5th source electrode of PMOS transistor (M5) and the 12 PMOS transistor (M12) of described band gap comparison circuit is connected, exported the output voltage (Vin) of described voltage selecting circuit by the source electrode of described the 5th PMOS transistor (M5), described output voltage (Vin) provides input voltage as described band gap comparison circuit.

5. the under-voltage protecting circuit for Power over Ethernet according to claim 1, is characterized in that, described in prevent described supply voltage (V _dD) pulse cause that the protective circuit of operation comprises: ten three PMOS transistor (M13), ten one PMOS transistor (M11) and the ten PMOS transistor (M10) in parallel with described the 12 PMOS transistor (M12) of described band gap comparison circuit

Wherein said the 11 PMOS transistor (M11) and described the tenth PMOS transistor (M10) are all connected in parallel on described internal power source voltage (V _cC) and the source electrode of described the 13 PMOS transistor (M13) between, the source electrode of wherein said the 11 PMOS transistor (M11) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the 11 PMOS transistor (M11) is connected with the source electrode of described the 13 PMOS transistor (M13), described the 11 drain electrode of PMOS transistor (M11) and the source electrode of described the 13 PMOS transistor (M13), the grid of described the 11 PMOS transistor (M11) is connected with the grid of a PMOS transistor (M1) of described the first biasing circuit, and described the 11 PMOS transistor (M11) produces the 4th image current (I of the 4th mirror current source branch road _c4);

The source electrode of described the tenth PMOS transistor (M10) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the tenth PMOS transistor (M10) is connected in the source electrode of described the 13 PMOS transistor (M13), and the drain electrode of described the tenth PMOS transistor (M10) produces the 5th image current (I of the 5th image current branch road _c5);

Described the 13 PMOS transistor (M13) drain electrode and described the 12 PMOS transistor (M12) drain electrode earth, the grid of described the 13 PMOS transistor (M13) accesses the second bias voltage (V _bias2) make comparisons with the input voltage of the grid access of described the 12 PMOS transistor (M12), the source electrode of described the 13 PMOS transistor (M13) is parallel to the source electrode of described the 12 PMOS transistor (M12), the substrate of described the 13 PMOS transistor (M13) is connected in the source electrode of described the 13 PMOS transistor (M13), the substrate of described the 12 PMOS transistor (M12) is connected in the source electrode of described the 12 PMOS transistor (M12), described the second bias voltage (V _bias2) with described input voltage relatively after by the source electrode output voltage of described the 12 PMOS transistor (M12).

6. the under-voltage protecting circuit for Power over Ethernet according to claim 1; it is characterized in that, described band gap comparison circuit comprises: produce the band-gap reference structure of reference voltage, load circuit, second level output circuit, startup clamp circuit and the logical circuit of generation current source branch current.

7. the under-voltage protecting circuit for Power over Ethernet according to claim 6, is characterized in that, described logical circuit comprises Schmidt trigger (SMT) and the second inverter (INV2),

Wherein, the input of described Shi Misi trigger (SMT) is connected with the output of the drain electrode of described the 19 PMOS transistor (M19) of the described second level output circuit of described band gap comparison circuit; the UVLO signal of the described under-voltage protecting circuit of output after described the second inverter (INV2); and described the second inverter (INV2) is connected with described the first inverter (INV1), described UVLO signal feedback is given to the input of described the first inverter (INV1).

8. the under-voltage protecting circuit for Power over Ethernet according to claim 6; it is characterized in that; described band-gap reference structure comprises: the 14 PMOS transistor (M14), the 17 PMOS transistor (M17), the first triode (Q1), the second triode (Q2), the first resistance (R1) and the second resistance (R2)

Wherein, the source electrode of described the 14 PMOS transistor (M14) and substrate are connected in described internal power source voltage (V _cC);

The drain electrode of described the 14 PMOS transistor (M14) is connected in the source electrode of described the 17 PMOS transistor (M17), and the substrate of described the 17 PMOS transistor (M17) is connected in the source electrode of described the 17 PMOS transistor (M17);

The grid of described the 14 PMOS transistor (M14) is connected with the grid of a described PMOS transistor (M1) of described the first biasing circuit, and produces the 3rd image current (I of the 3rd mirror current source branch road _c6);

The base stage of described the second triode (Q2) is connected with the source electrode of the 13 PMOS transistor (M13), and the base stage of described the second triode (Q2) is connected voltage input end as a comparison with the base stage of described the first triode (Q1);

The collector electrode of described the second triode (Q2) is connected with the drain electrode of the 15 PMOS transistor (M15) of described load circuit, produces the second image current (I of the second mirror current source branch road _c2);

The collector electrode of described the first triode (Q1) is connected with the drain electrode of the 16 PMOS transistor (M16) of described load circuit, produces the first mirror image current (I of the first mirror current source branch road _c7);

The emitter of described the second triode (Q2) is connected to the emitter of described the first triode (Q1) through described the second resistance (R2), the source electrode of the 17 PMOS transistor (M17) that the emitter of described the first triode (Q1) connects through described the first resistance (R1), the substrate of the 17 PMOS transistor (M17) is connected in the source electrode of described the 17 PMOS transistor (M17), the grid of the 17 PMOS transistor (M17) and the equal ground connection of drain electrode.

9. the under-voltage protecting circuit for Power over Ethernet according to claim 8, is characterized in that, the load circuit of described generation current source branch current comprises:

The 16 PMOS transistor (M16), the 15 PMOS transistor (M15) and the second electric capacity (C2);

Wherein said the 16 PMOS transistor M16 and described the 15 PMOS transistor M15 form mirror current source, the self-bias voltage V that described the 15 PMOS transistor M15 grid produces _biasbe input to the grid of the 16 PMOS transistor M16, the source electrode of described the 16 PMOS transistor (M16) and substrate are connected in described internal power source voltage (V _cC);

The source electrode of described the 15 PMOS transistor (M15) and substrate are connected in described internal power source voltage (V _cC), the grid of described the 15 PMOS transistor (M15) is connected in the drain electrode of described the 15 PMOS transistor (M15), and the grid of described the 15 PMOS transistor (M15) is connected with the grid that described comparative voltage produces the 7th PMOS transistor (M7) of circuit;

Described the 15 PMOS transistor (M15) forms mirror current source with described the tenth PMOS transistor (M10), the self-bias voltage V that described the 15 PMOS transistor M15 grid produces _biasbe input to the grid of the tenth PMOS transistor M10.

10. the under-voltage protecting circuit for Power over Ethernet according to claim 9; it is characterized in that; described second level output circuit comprises: the 19 PMOS transistor (M19), the 20 PMOS transistor (M20), the 21 PMOS transistor (M21) and the 29 PMOS transistor (M29)

Wherein said the 15 PMOS transistor (M15) forms mirror current source with described the 29 PMOS transistor (M29), and the source electrode of described the 29 PMOS transistor (M29) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the 29 PMOS transistor (M29) is connected with the drain electrode of described the 20 PMOS transistor (M20), the self-bias voltage V that described the 15 PMOS transistor M15 grid produces _biasbe input to the grid of the 29 PMOS transistor M29, produce the 6th image current (I of the 6th image current branch road _c6);

Described the 20 PMOS transistor (M20) forms mirror current source with described the 21 PMOS transistor (M21), and described the 20 PMOS transistor (M20) produces the 7th image current (I _c7), the grid of described the 20 PMOS transistor (M20) is connected with the grid of described the 21 PMOS transistor (M21), the grid of described the 20 PMOS transistor (M20) is connected with the drain electrode of described the 20 PMOS transistor (M20), the source electrode of described the 20 PMOS transistor (M20) and substrate ground connection, the source electrode of described the 21 PMOS transistor (M21) and substrate ground connection, described the 20 PMOS transistor (M20) produces the 8th image current (I _c8);

The grid of described the 19 PMOS transistor (M19) is connected with the collector electrode of described first triode (Q1) of described band-gap reference structure, and the source electrode of described the 19 PMOS transistor (M19) and substrate are connected in described internal power source voltage (V _cC), the drain electrode of described the 19 PMOS transistor (M19) is connected with the drain electrode of described the 21 PMOS transistor (M21), produces the output voltage of second level output circuit.

11. under-voltage protecting circuits for Power over Ethernet according to claim 10, it is characterized in that, described startup clamp circuit comprises: the 18 PMOS transistor (M18), the 22 PMOS transistor (M22), the 23 PMOS transistor (M23), the 24 PMOS transistor (M24), the 25 PMOS transistor (M25), the 26 PMOS transistor (M26), the 27 PMOS transistor (M27), the 28 PMOS transistor (M28), the 3rd electric capacity (C3) and the 5th electric capacity (C5),

The drain electrode of wherein said the 18 PMOS transistor (M18) is connected with the grid of described the 19 PMOS transistor (M19) of described second level output circuit, and the drain electrode of described the 19 PMOS transistor (M19) is parallel to the 5th electric capacity (C5) described in a ground connection; The source electrode of described the 18 PMOS transistor (M18) and substrate are connected in described internal power source voltage (V _cC), being connected of described the 18 grid of PMOS transistor (M18) and the drain electrode of described the 27 PMOS transistor (M27);

The source electrode of described the 22 PMOS transistor (M22) and substrate are connected in described internal power source voltage (V _cC), the grid of the PMOS transistor (M1) that the grid of described the 22 PMOS transistor (M22) is connected with described the first biasing circuit connects, and the drain electrode of described the 22 PMOS transistor (M22) is connected with the source electrode of described the 25 PMOS transistor (M25);

The substrate of described the 25 PMOS transistor (M25) is connected in described internal power source voltage (V _cC), the drain electrode of described the 25 PMOS transistor (M25) is connected with the drain electrode of described the 26 PMOS transistor (M26), the drain electrode of described the 25 PMOS transistor (M25) is connected with the grid of described the 23 PMOS transistor (M23), the grid of described the 25 PMOS transistor (M25) is connected with the grid of described the 26 PMOS transistor (M26), and the grid of described the 26 PMOS transistor (M26) is by described the 3rd electric capacity (C3) ground connection;

The source electrode of described the 26 PMOS transistor (M26) and substrate ground connection;

The drain electrode of described the 23 PMOS transistor (M23) is parallel to the drain electrode of described the 19 PMOS transistor (M19) of described second level output, the substrate ground connection of described the 23 PMOS transistor (M23), the source electrode of described the 23 PMOS transistor (M23) is connected with the drain electrode of described the 24 PMOS transistor (M24);

The source electrode of described the 24 PMOS transistor (M24) and substrate ground connection, the grid of described the 24 PMOS transistor (M24) is connected with the grid of described the 2nd PMOS transistor M2 of described the first biasing circuit;

The source electrode of described the 27 PMOS transistor (M27) and substrate are connected in described internal power source voltage (V _cC), the grid of described the 27 PMOS transistor (M27) is connected with the grid that described comparative voltage produces described the 7th PMOS transistor (M7) of circuit, the drain electrode of described the 27 PMOS transistor (M27) is connected with described the 28 PMOS transistor (M28) drain electrode, and the grid of described the 26 PMOS transistor (M26) is parallel to described the 28 PMOS transistor (M28) drain electrode;

The source electrode of described the 28 PMOS transistor (M28) and substrate ground connection, the grid of described the 28 PMOS transistor (M28) is connected with the grid of a PMOS transistor M2 described in described the first biasing circuit.