CN104113041B - A kind of under-voltage protecting circuit for POE - Google Patents

Abstract

The present invention provides an undervoltage protection circuit for power over Ethernet, the undervoltage protection circuit for power over Ethernet includes: a resistor divider circuit for adjusting the flipping threshold voltage, and generating a first output voltage and a second output voltage Voltage; the voltage selection circuit is connected with the resistor divider circuit, and a voltage value is selected from the first output voltage and the second output voltage; the band gap comparison circuit is connected with the voltage selection circuit, and the voltage value selected by the voltage selection circuit or the The voltage value of the protection circuit that prevents the operation caused by the pulse of the power supply voltage is used as the input voltage to generate the UVLO signal of the undervoltage protection circuit; the feedback control loop set between the resistor voltage divider circuit and the bandgap comparison circuit, the output of the UVLO signal is a high voltage Normally, the UVLO signal passes through the voltage selection circuit to output a higher first output voltage, and the UVLO signal output is at a low level to output a lower second output voltage. In this way, the structure of the bandgap comparator reduces the circuit area and speeds up the response speed of the circuit.

Description

An Undervoltage Protection Circuit for Power over Ethernet

technical field

The invention relates to the field of protection circuits, in particular to an undervoltage protection circuit for Ethernet power supply.

Background technique

In recent years, with the application of VoIP and wireless local area network WLAN more and more widely, the demand for power supply through Ethernet itself is becoming more and more urgent. Power over Ethernet PoE technology can also provide power support while transmitting data. , so it has been rapidly promoted, and PoE technology is more and more applied to network equipment.

It is precisely because of the widespread use of PoE technology that people have higher and higher requirements for its stability, so as to ensure that the PoE power supply can still work normally under the condition of voltage fluctuation. After the power supply equipment PSE completes the detection and classification of the powered device PD, and knows the exact power level of the PD, the PSE will increase the feed voltage and start supplying power to the PD, so that the power supply voltage will rise slowly from zero; when the power supply After the voltage is charged to the turn-on voltage of the chip, the circuit works normally; due to the work of the internal module, the load current of the system becomes larger at this time, and the power supply voltage of the chip will fluctuate, especially the power supply voltage fluctuation in the high-voltage area of the chip will be relatively large. If the power supply voltage is too low, it will cause a lot of power loss. Therefore, in order to ensure that the high-voltage integrated circuit can work stably after the chip is turned on, and to avoid damage to the chip fluctuation system, we generally introduce an undervoltage protection circuit to monitor the chip power supply voltage. .

At present, a relatively common undervoltage protection circuit is shown in Figure 1. The undervoltage protection circuit includes a power voltage divider, a reference voltage source, a comparator and a logic circuit. The chip samples the power supply voltage through the power voltage divider. When the sampling voltage V1 exceeds the turn-on voltage V _{UVLO_R} , UVLO turns to low level, and the chip starts; when the sampling voltage V2 is lower than the power supply voltage V _DD (off), the UVLO signal of the undervoltage protection circuit Flip to high level, the chip is turned off. The undervoltage protection circuit uses an independent reference voltage source and comparator, resulting in long response time, large area occupation and high power consumption.

Contents of the invention

The purpose of the present invention is to provide an undervoltage protection circuit for Ethernet power supply, which solves the problems that the traditional undervoltage circuit uses an independent reference voltage source and comparator, resulting in long response time, large occupied area and high power consumption. .

In order to solve the above technical problems, an embodiment of the present invention provides an undervoltage protection circuit for Power over Ethernet, which includes:

A resistor divider circuit for adjusting the flipping threshold voltage, and generating a first output voltage and a second output voltage;

a voltage selection circuit, connected to the resistor divider circuit, and selects a voltage value from the first output voltage and the second output voltage;

A bandgap comparator circuit, connected to the voltage selection circuit, used to use the voltage value selected by the voltage selection circuit or the voltage value of the protection circuit to prevent the pulse of the power supply voltage from being operated as an input voltage to generate an undervoltage Protection circuit UVLO signal;

The feedback control loop provided between the resistance voltage divider circuit and the bandgap comparison circuit is used to output a higher level of the UVLO signal through the voltage selection circuit when the output of the UVLO signal is at a high level. For the first output voltage, when the output of the UVLO signal is at a low level, a lower second output voltage is output.

Wherein, the undervoltage protection circuit for Power over Ethernet further includes: a bias circuit, wherein the bias circuit includes: a first bias circuit and a comparison voltage generating circuit;

Wherein the first bias circuit comprises: a thirtieth PMOS transistor (M0), a second PMOS transistor (M2), a third PMOS transistor (M3), a first PMOS transistor (M1) and a fourth capacitor (C4),

Wherein the gate of the thirtieth PMOS transistor (M0) is grounded, the source and substrate of the thirtieth PMOS transistor (M0) are connected to the internal power supply voltage (V _CC ), and the thirtieth PMOS transistor (M0) ) is connected to the drain of the second PMOS transistor (M2), and the drain of the second PMOS transistor (M2) is connected to the gate of the second PMOS transistor (M2);

The source and the substrate of the second PMOS transistor (M2) are grounded;

The source and the substrate of the third PMOS transistor (M3) are grounded;

The gate of the third PMOS transistor (M3) is grounded through the fourth capacitor (C4), the gate of the second PMOS transistor (M2) and the gate of the third PMOS transistor (M3) are the The bandgap comparator circuit provides a first bias current (inp1);

The gate of the second PMOS transistor (M2) is connected to the gate of the first PMOS transistor (M1) through a diode, and the drain of the first PMOS transistor (M1) is connected to the gate of the third PMOS transistor (M3 ) is connected to the drain, the source and substrate of the first PMOS transistor (M1) are connected to the internal power supply voltage (V _CC ), and the gate of the first PMOS transistor (M1) provides the first bias current (inp1);

Wherein the comparison voltage generating circuit includes: a sixth PMOS transistor (M6), a seventh PMOS transistor (M7), an eighth PMOS transistor (M8), a ninth PMOS transistor (M9) and a first capacitor (C1), the The first PMOS transistor (M1) and the sixth PMOS transistor (M6) of the first bias circuit form a mirror current source, and the first bias provided by the gate of the first PMOS transistor (M1) current (inp1) to the gate of said sixth PMOS transistor (M6);

The source and substrate of the sixth PMOS transistor (M6) are connected to the internal power supply voltage (V _CC ), and the source and substrate of the seventh PMOS transistor (M7) are connected to the internal power supply voltage ( V _CC ), the gate of the seventh PMOS transistor (M7) is connected to the gate of the fifteenth PMOS transistor (M15) of the bandgap comparison circuit, and the gate of the fifteenth PMOS transistor M15 generates self-bias Set the voltage V _bias , the drain of the seventh PMOS transistor (M7) is connected to the drain of the sixth PMOS transistor (M6), the drain of the seventh PMOS transistor (M7) is connected to the eighth PMOS The source of the transistor (M8) is connected, the substrate of the eighth PMOS transistor (M8) is connected to the source of the eighth PMOS transistor (M8), and the drain of the sixth PMOS transistor (M6) outputs a second bias voltage (V _bias2 );

The drain (M8) of the eighth PMOS transistor is short-circuited to the gate of the eighth PMOS transistor (M8), and the drain (M8) of the eighth PMOS transistor is connected to the ninth PMOS transistor (M9 ), the substrate of the ninth PMOS transistor (M9) is connected to the source electrode of the ninth PMOS transistor (M9);

The gate of the ninth PMOS transistor (M9) and the drain of the ninth PMOS transistor (M9) are grounded through a first capacitor (C1).

Further, the resistor divider circuit includes: a third resistor (R3), a fourth resistor (R4) and a fifth resistor (R5), wherein one end of the third resistor (R3) is connected to the power supply voltage (V _DD ), and the other end of the third resistor (R3) is connected in series with one end of the fourth resistor (R4), the third resistor (R3) and the fourth resistor (R4) form the first an output voltage (V1), the first output voltage (V1) is used as the input voltage of the voltage selection circuit;

One end of the fifth resistor (R5) is connected in series with the other end of the fourth resistor (R4), and the other end of the fifth resistor (R5) is grounded, and the fourth resistor (R4) and the fifth resistor The second output voltage (V2) is formed between the resistors (R5), and the first output voltage (V2) is used as the input voltage of the voltage selection circuit.

Further, the voltage selection circuit includes: a fourth PMOS transistor (M4), a fifth PMOS transistor (M5) and a first inverter (INV1),

wherein the gate of the fifth PMOS transistor (M5) is connected to the input terminal of the first inverter (INV1);

The gate of the fourth PMOS transistor (M4) is connected to the output terminal of the first inverter (INV1);

The drain of the fourth PMOS transistor (M4) is connected to the second output voltage (V2) of the resistor divider circuit;

The drain of the fifth PMOS transistor (M5) is connected to the first output voltage (V1) of the resistor divider circuit;

The source of the fifth PMOS transistor (M5) is connected to the source of the fourth PMOS transistor (M4), and the substrate of the fifth PMOS transistor (M5) is connected in series with the substrate of the fourth PMOS transistor (M4) Together, the substrate of the fifth PMOS transistor (M5) is connected to the source of the fifth PMOS transistor (M5), and the source of the fifth PMOS transistor (M5) is connected to the bandgap comparison circuit The gate of the twelfth PMOS transistor (M12) is connected, and the source of the fifth PMOS transistor (M5) outputs the output voltage (Vin) of the voltage selection circuit, and the output voltage (Vin) is used as the A bandgap comparator circuit provides the input voltage.

Further, the protection circuit for preventing operation caused by the pulse of the power supply voltage (V _DD ) includes: a thirteenth PMOS transistor (M13) connected in parallel with the twelfth PMOS transistor (M12) of the bandgap comparison circuit ), the eleventh PMOS transistor (M11) and the tenth PMOS transistor (M10),

Wherein the eleventh PMOS transistor (M11) and the tenth PMOS transistor (M10) are connected in parallel between the internal power supply voltage (V _CC ) and the source of the thirteenth PMOS transistor (M13), Wherein the source and substrate of the eleventh PMOS transistor (M11) are connected to the internal power supply voltage (V _CC ), the drain of the eleventh PMOS transistor (M11) is connected to the thirteenth PMOS transistor (M13) source is connected, the drain of the eleventh PMOS transistor (M11) is connected to the source of the thirteenth PMOS transistor (M13), the gate of the eleventh PMOS transistor (M11) is connected to The gate of the first PMOS transistor (M1) of the first bias circuit is connected, and the eleventh PMOS transistor (M11) generates a fourth mirror current (I _C4 ) of the fourth mirror current source branch;

The source and substrate of the tenth PMOS transistor (M10) are connected to the internal power supply voltage (V _CC ), and the drain of the tenth PMOS transistor (M10) is connected to the thirteenth PMOS transistor (M13 ), the drain of the tenth PMOS transistor (M10) generates the fifth mirror current (I _C5 ) of the fifth mirror current branch;

The drain of the thirteenth PMOS transistor (M13) is connected to the ground in parallel with the drain of the twelfth PMOS transistor (M12), and the gate of the thirteenth PMOS transistor (M13) is connected to the second bias voltage (V _bias2 ) is compared with the input voltage connected to the gate of the twelfth PMOS transistor (M12), and the source of the thirteenth PMOS transistor (M13) is connected in parallel to the twelfth PMOS transistor (M12) source, the substrate of the thirteenth PMOS transistor (M13) is connected to the source of the thirteenth PMOS transistor (M13), and the substrate of the twelfth PMOS transistor (M12) is connected to the source of the thirteenth PMOS transistor (M12). sources of twelve PMOS transistors (M12), the source of the twelfth PMOS transistors (M12) outputs a voltage after comparing the second bias voltage (V _bias2 ) with the input voltage.

Further, the bandgap comparison circuit includes: a bandgap reference structure for generating a reference voltage, a load circuit for generating current source branch current, a second-stage output circuit, a startup clamp circuit and a logic circuit.

Further, the logic circuit includes a Schmitt trigger (SMT) and a second inverter (INV2),

Wherein, the input end of the Smith trigger (SMT) is connected with the output end of the drain of the nineteenth PMOS transistor (M19) of the second stage output circuit of the bandgap comparator circuit, through the The second inverter (INV2) outputs the UVLO signal of the undervoltage protection circuit, and the second inverter (INV2) is connected to the first inverter (INV1), and the UVLO signal Feedback to the input of the first inverter (INV1).

Further, the bandgap reference structure includes: a fourteenth PMOS transistor (M14), a seventeenth PMOS transistor (M17), a first triode (Q1), a second triode (Q2), a first resistor (R1) and a second resistor (R2),

Wherein, the source and substrate of the fourteenth PMOS transistor (M14) are connected to the internal power supply voltage (V _CC );

The drain of the fourteenth PMOS transistor (M14) is connected to the source of the seventeenth PMOS transistor (M17), and the substrate of the seventeenth PMOS transistor (M17) is connected to the seventeenth PMOS transistor (M17). the source of the transistor (M17);

The gate of the fourteenth PMOS transistor (M14) is connected to the gate of the first PMOS transistor (M1) of the first bias circuit, and generates a third mirror current of the third mirror current source branch ( _IC3 );

The base of the second transistor (Q2) is connected to the source of the thirteenth PMOS transistor (M13), and the base of the second transistor (Q2) is connected to the first transistor (Q1 ) base connection as a comparison voltage input;

The collector of the second triode (Q2) is connected to the drain of the fifteenth PMOS transistor (M15) of the load circuit to generate a second mirror current (I _C2 ) of the second mirror current source branch;

The collector of the first triode (Q1) is connected to the drain of the sixteenth PMOS transistor (M16) of the load circuit to generate the first mirror current (I _C1 ) of the first mirror current source branch;

The emitter of the second triode (Q2) is connected to the emitter of the first triode (Q1) via the second resistor (R2), and the emitter of the first triode (Q1) The source of the seventeenth PMOS transistor (M17) connected via the first resistor (R1), the substrate of the seventeenth PMOS transistor (M17) is connected to the source of the seventeenth PMOS transistor (M17) , both the gate and the drain of the seventeenth PMOS transistor (M17) are grounded.

Further, the load circuit generating the branch current of the current source includes:

A sixteenth PMOS transistor (M16), a fifteenth PMOS transistor (M15) and a second capacitor (C2);

Wherein the sixteenth PMOS transistor M16 and the fifteenth PMOS transistor M15 form a mirror current source, and the self-bias voltage V _bias generated by the gate of the fifteenth PMOS transistor M15 is input to the sixteenth PMOS transistor M16 a gate, a source and a substrate of the sixteenth PMOS transistor (M16) are connected to the internal power supply voltage (V _CC );

The source and substrate of the fifteenth PMOS transistor (M15) are connected to the internal power supply voltage (V _CC ), and the gate of the fifteenth PMOS transistor (M15) is connected to the fifteenth PMOS transistor (M15), the gate of the fifteenth PMOS transistor (M15) is connected to the gate of the seventh PMOS transistor (M7) of the comparison voltage generating circuit;

The fifteenth PMOS transistor (M15) and the tenth PMOS transistor (M10) form a mirror current source, and the self-bias voltage V _bias generated by the gate of the fifteenth PMOS transistor M15 is input to the tenth PMOS transistor M10 the grid.

Further, the second-stage output circuit includes: a nineteenth PMOS transistor (M19), a twentieth PMOS transistor (M20), a twenty-first PMOS transistor (M21) and a twenty-ninth PMOS transistor (M29), Wherein the fifteenth PMOS transistor (M15) and the twenty-ninth PMOS transistor (M29) form a mirror current source, and the source and substrate of the twenty-ninth PMOS transistor (M29) are connected to the internal power supply voltage (V _CC ), the drain of the twenty-ninth PMOS transistor (M29) is connected to the drain of the twenty-ninth PMOS transistor (M20), and the self generated by the gate of the fifteenth PMOS transistor M15 The bias voltage V _bias is input to the gate of the twenty-ninth PMOS transistor M29 to generate the sixth mirror current (I _C6 ) of the sixth mirror current branch;

The 20th PMOS transistor (M20) and the 21st PMOS transistor (M21) form a mirror current source, and the 20th PMOS transistor (M20) generates a seventh mirror current (I _C7 ), and the 20th PMOS transistor (M20) generates a seventh mirror current (I C7 ). The gates of the twenty PMOS transistors (M20) are connected to the gates of the twenty-first PMOS transistors (M21), and the gates of the twenty PMOS transistors (M20) are connected to the gates of the twenty PMOS transistors (M20). ), the source and substrate of the twentieth PMOS transistor (M20) are grounded, the source and substrate of the twenty-first PMOS transistor (M21) are grounded, and the twentieth PMOS transistor (M20) generates an eighth mirror current (I _C8 );

The gate of the nineteenth PMOS transistor (M19) is connected to the collector of the first triode (Q1) of the bandgap reference structure, and the source of the nineteenth PMOS transistor (M19) and The substrate is connected to the internal power supply voltage (V _CC ), the drain of the nineteenth PMOS transistor (M19) is connected to the drain of the twenty-first PMOS transistor (M21), generating a second-stage output circuit output voltage.

Further, the startup clamping circuit includes: an eighteenth PMOS transistor (M18), a twenty-second PMOS transistor (M22), a twenty-third PMOS transistor (M23), a twenty-fourth PMOS transistor (M24), The twenty-fifth PMOS transistor (M25), the twenty-sixth PMOS transistor (M26), the twenty-seventh PMOS transistor (M27), the twenty-eighth PMOS transistor (M28), the third capacitor (C3) and the fifth capacitor (C5),

Wherein the drain of the eighteenth PMOS transistor (M18) is connected to the gate of the nineteenth PMOS transistor (M19) of the second-stage output circuit, and the drain of the nineteenth PMOS transistor (M19) The pole is connected in parallel with a grounded fifth capacitor (C5); the source and substrate of the eighteenth PMOS transistor (M18) are connected to the internal power supply voltage (V _CC ), and the eighteenth PMOS transistor ( the connection of the gate of M18) to the drain of said twenty-seventh PMOS transistor (M27);

The source and substrate of the twenty-second PMOS transistor (M22) are connected to the internal power supply voltage (V _CC ), and the gate of the twenty-second PMOS transistor (M22) is connected to the first bias The gate of the circuit-connected first PMOS transistor (M1) is connected, the drain of the twenty-second PMOS transistor (M22) is connected to the source of the twenty-fifth PMOS transistor (M25);

The substrate of the twenty-fifth PMOS transistor (M25) is connected to the internal power supply voltage (V _CC ), and the drain of the twenty-fifth PMOS transistor (M25) is connected to the twenty-sixth PMOS transistor ( M26), the drain of the twenty-fifth PMOS transistor (M25) is connected to the gate of the twenty-third PMOS transistor (M23), the twenty-fifth PMOS transistor (M25) The gate is connected to the gate of the twenty-sixth PMOS transistor (M26), and the gate of the twenty-sixth PMOS transistor (M26) is grounded through the third capacitor (C3);

The source and the substrate of the twenty-sixth PMOS transistor (M26) are grounded;

The drain of the twenty-third PMOS transistor (M23) is connected in parallel to the drain of the nineteenth PMOS transistor (M19) output by the second stage, and the substrate of the twenty-third PMOS transistor (M23) The bottom is grounded, and the source of the twenty-third PMOS transistor (M23) is connected to the drain of the twenty-fourth PMOS transistor (M24);

The source and the substrate of the twenty-fourth PMOS transistor (M24) are grounded, and the gate of the twenty-fourth PMOS transistor (M24) is connected to the gate of the second PMOS transistor M2 of the first bias circuit. connected to the grid;

The source and substrate of the twenty-seventh PMOS transistor (M27) are connected to the internal power supply voltage (V _CC ), and the gate of the twenty-seventh PMOS transistor (M27) is connected to the comparison voltage generation circuit The gate of the seventh PMOS transistor (M7) is connected, the drain of the twenty-seventh PMOS transistor (M27) is connected to the drain of the twenty-eighth PMOS transistor (M28), and the twenty-eighth PMOS transistor (M28) is connected to the drain. The gates of the six PMOS transistors (M26) are connected in parallel to the drain of the twenty-eighth PMOS transistor (M28);

The source and substrate of the twenty-eighth PMOS transistor (M28) are grounded, and the gate of the twenty-eighth PMOS transistor (M28) is connected to the gate of the first PMOS transistor M2 of the first bias circuit. Pole connected.

The beneficial effects of above-mentioned technical scheme of the present invention are as follows:

In the solution of the present invention, two voltage values are generated by the resistor divider circuit, and a voltage value is selected by the voltage selection circuit as the input voltage of the bandgap comparison circuit, and the pulse of the power supply voltage is prevented from being caused by the voltage value of the protection circuit by comparing with the voltage value of the protection circuit. At the same time, after the UVLO signal of an undervoltage protection circuit is generated by the bandgap comparison circuit, the UVLO signal is returned by the feedback control loop to monitor the high and low levels of the UVLO signal to protect the safety of subsequent module startup. This is achieved through the bandgap comparison circuit. The functions of the bandgap reference circuit and the comparator are optimized, the circuit structure is optimized, the circuit area is reduced, the power consumption is reduced, and the response speed of the circuit is also accelerated. Realize the monitoring of the power supply voltage of the DC chopper DC/DC controller that converts the PoE interface and the fixed DC voltage into a variable DC voltage. At the same time, in order to achieve high conversion efficiency and obtain small changes with input voltage and temperature flip threshold voltage.

Description of drawings

FIG. 1 is a general undervoltage protection circuit diagram of the prior art;

FIG. 2 is a relationship diagram between current I _C1 , current I _C2 and input voltage V _D according to an embodiment of the present invention;

3 is a schematic block diagram of an undervoltage protection circuit according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of an undervoltage protection circuit according to an embodiment of the present invention.

Explanation of reference signs:

1-resistor divider circuit, 2-voltage selection circuit, 3-band gap comparison circuit, 31-band gap reference structure, 32-logic circuit, 4-bias circuit.

detailed description

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

The present invention aims at the problems of using independent reference voltage source and comparator in the traditional undervoltage circuit in the prior art, resulting in long response time, large occupied area and large power consumption, and provides an undervoltage protection for Power over Ethernet The circuit, by making the comparator and the reference voltage source into a bandgap comparison circuit 3 circuit, makes the undervoltage protection circuit have a faster flipping speed, and the power consumption is very low, and through the existence of the protection circuit, the power supply voltage is prevented V _DD pulses cause misoperation.

It should be noted that V _DD in the present invention is an external power supply pin of the chip, and V _DD generates an internal power supply voltage V _CC through an internal low-voltage source generating circuit.

As shown in Figures 2 to 4, the undervoltage protection circuit for Ethernet power supply provided by the embodiment of the present invention includes:

A resistor divider circuit 1 for adjusting the inversion threshold voltage, and generating a first output voltage and a second output voltage;

A voltage selection circuit 2, connected to the resistor divider circuit 1, selects a voltage value from the first output voltage and the second output voltage;

A bandgap comparator circuit 3, connected to the voltage selection circuit 2, used to use the voltage value selected by the voltage selection circuit 2 or the voltage value of the protection circuit that prevents the operation from being caused by the pulse of the power supply voltage as an input voltage to generate 1. Undervoltage protection circuit UVLO signal;

The feedback control circuit arranged between the resistance divider circuit 1 and the bandgap comparison circuit 3 is used to output the UVLO signal through the voltage selection circuit 2 when the output of the UVLO signal is at a high level When the first output voltage is relatively high, when the UVLO signal output is at a low level, the second output voltage is relatively low.

The voltage selection circuit 2 selects the voltage value of the resistor divider circuit 1 or the voltage value of the protection circuit that prevents the operation caused by the pulse of the power supply voltage as the input voltage of the bandgap comparison circuit 3, and after generating the UVLO signal of the undervoltage protection circuit, through The feedback control loop returns the UVLO signal to the voltage selection circuit 2, and then the voltage selection circuit 2 can select a first output voltage with a higher voltage value or output a lower second output voltage as the input of the bandgap comparison circuit 3, and in the bandgap When the UVLO signal of the output undervoltage protection circuit of the gap comparison circuit 3 is at a low level, the basic module inside the chip does not start, which serves the purpose of undervoltage protection; when the UVLO signal of the output undervoltage protection circuit of the band gap comparison circuit 3 is at a high level , the chip starts, and the internal basic module starts. In this way, the comparator and the reference voltage source are combined to form a bandgap comparison circuit 3, the circuit structure is obviously simplified, the area is reduced, and the cost is reduced; and the undervoltage protection circuit flip threshold voltage is adjustable and the temperature drift is small; when When the power supply voltage is undervoltage, no reference voltage is generated, which saves a lot of standby power consumption.

In order to supply power to the bandgap comparison circuit 3, the undervoltage protection circuit for power over Ethernet in the embodiment of the present invention also includes:

A bias circuit 4, wherein the bias circuit 4 includes: a first bias circuit and a comparison voltage generation circuit;

Wherein the first bias circuit includes: a thirtieth PMOS transistor M0, a second PMOS transistor M2, a third PMOS transistor M3, a first PMOS transistor (M1) and a fourth capacitor C4, wherein the thirtieth PMOS transistor The gate of M0 is grounded, the source and substrate of the thirtieth PMOS transistor M0 are connected to the internal power supply voltage V _CC , the drain of the thirtieth PMOS transistor M0 is connected to the drain of the second PMOS transistor M2 , the drain of the second PMOS transistor M2 is connected to the gate of the second PMOS transistor M2; wherein the gate of the thirtieth PMOS transistor M0 is grounded, and the source and substrate are connected to the power supply voltage V _CC , the thirtieth PMOS transistor M0 is in a normally-on state;

The source and the substrate of the second PMOS transistor M2 are grounded;

The source and the substrate of the third PMOS transistor M3 are grounded;

The gate of the third PMOS transistor M3 is grounded through the fourth capacitor C4, and the gates of the second PMOS transistor M2 and the gate M3 of the third PMOS transistor provide a first bias for the bandgap comparison circuit 3. set current inp1;

The gate of the second PMOS transistor M2 is connected to the gate of the first PMOS transistor M1 through a diode, and the drain of the first PMOS transistor M1 is connected to the drain of the third PMOS transistor M3. The source and substrate of the first PMOS transistor M1 are connected to the internal power supply voltage V _CC , and the gate of the first PMOS transistor M1 provides the first bias current inp1;

Wherein the comparison voltage generation circuit includes: a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth PMOS transistor M9 and a first capacitor C1, and the first bias circuit of the first The PMOS transistor M1 and the sixth PMOS transistor M6 form a mirror current source, and the gate of the first PMOS transistor M1 provides the first bias current inp1 to the gate of the sixth PMOS transistor M6;

The source and substrate of the sixth PMOS transistor M6 are connected to the internal power supply voltage V _CC , the source and substrate of the seventh PMOS transistor M7 are connected to the internal power supply voltage V _CC , and the seventh PMOS transistor M7 is connected to the internal power supply voltage V CC . The gate of the PMOS transistor (M7) is connected to the gate of the fifteenth PMOS transistor (M15) of the bandgap comparison circuit 3, and the gate of the fifteenth PMOS transistor M15 generates a self-bias voltage V _bias , the The drain of the seventh PMOS transistor M7 is connected to the drain of the sixth PMOS transistor M6, the drain of the seventh PMOS transistor M7 is connected to the source of the eighth PMOS transistor M8, and the eighth PMOS transistor The substrate of M8 is connected to the source of the eighth PMOS transistor M8, and the drain of the sixth PMOS transistor M6 outputs a second bias voltage V _bias2 ;

The drain M8 of the eighth PMOS transistor is short-circuited to the gate of the eighth PMOS transistor M8, the drain M8 of the eighth PMOS transistor is connected to the source of the ninth PMOS transistor M9, and the eighth PMOS transistor M8 is connected to the source of the ninth PMOS transistor M9. The substrate of the ninth PMOS transistor M9 is connected to the source of the ninth PMOS transistor M9;

The gate of the ninth PMOS transistor M9 and the drain of the ninth PMOS transistor M9 are grounded through the first capacitor C1.

When the above-mentioned chip is powered on, the mirror current source of the sixth PMOS transistor M6 quickly charges the first capacitor C1, when the bandgap comparison circuit 3 starts, the seventh PMOS transistor M7 is turned on, and after the current charging the first capacitor C1 increases, The second bias voltage V _{bias2 charges} more quickly. If the power supply voltage V _DD rises relatively slowly, the voltage of the second bias voltage V _bias2 rises faster than the output voltage Vin, and V _D is mainly controlled by the output voltage Vin, that is, the inversion point is controlled by the output voltage Vin; but when the power supply voltage V _DD generates a pulse, the power supply voltage V _DD rises rapidly, and the output voltage Vin rises faster than the second bias voltage V _bias2 , then at this time, the voltage of V _D is determined by the second bias voltage V _bias2 , when it rises to When a certain value is fixed, the bandgap comparator circuit 3 is reversed, and the same is true for the falling edge, thus preventing the power supply voltage V _DD from being misoperated due to pulses.

In order to sample the power supply voltage V _DD , in the undervoltage protection circuit for Power over Ethernet according to the embodiment of the present invention, the resistor divider circuit 1 includes: a third resistor R3, a fourth resistor R4 and a fifth resistor R5, wherein One end of the third resistor R3 is connected to the power supply voltage V _DD , and the other end of the third resistor R3 is connected in series with one end of the fourth resistor R4, and the connection between the third resistor R3 and the fourth resistor R4 form the first output voltage V1, and the first output voltage V1 is used as the input voltage of the voltage selection circuit 2;

One end of the fifth resistor R5 is connected in series with the other end of the fourth resistor R4, and the other end of the fifth resistor R5 is grounded, the fourth resistor R4 and the fifth resistor R5 form the first Two output voltages V2 , the first output voltage V2 is used as the input voltage of the voltage selection circuit 2 .

By adjusting the voltage dividing resistor of the resistance voltage dividing circuit 1, the threshold voltage of up and down flipping can also be adjusted, and the output signal UVLO of the bandgap comparator circuit 3 returns to the voltage selection circuit 2; when the UVLO signal flips, the voltage selection circuit 2 also flips accordingly. , from the voltage dividing resistor, the output signal Vin also changes accordingly. This signal is not only the input signal of the UVLO circuit, but also the Vin of the divided voltage of the V _DD signal, so the flipping threshold voltage changes accordingly.

In still another embodiment of the present invention, in the undervoltage protection circuit for Power over Ethernet, the voltage selection circuit 2 includes: a fourth PMOS transistor M4, a fifth PMOS transistor M5, and a first inverter INV1,

Wherein the gate of the fifth PMOS transistor M5 is connected to the input terminal of the first inverter INV1;

The gate of the fourth PMOS transistor M4 is connected to the output terminal of the first inverter INV1;

The drain of the fourth PMOS transistor M4 is connected to the second output voltage V2 of the resistor divider circuit 1;

The drain of the fifth PMOS transistor M5 is connected to the first output voltage V1 of the resistor divider circuit 1;

The source of the fifth PMOS transistor M5 is connected to the source of the fourth PMOS transistor M4, and the substrate of the fifth PMOS transistor M5 is connected in series with the substrate of the fourth PMOS transistor M4. The substrate of the transistor M5 is connected to the source of the fifth PMOS transistor M5, and the source of the fifth PMOS transistor M5 is connected to the gate of the twelfth PMOS transistor M12 of the bandgap comparison circuit 3, by The source of the fifth PMOS transistor M5 outputs the output voltage (Vin) of the voltage selection circuit, and the output voltage (Vin) serves as the input voltage for the bandgap comparison circuit 3 .

In order to prevent the operation caused by the pulse of the power supply voltage V _DD , in the undervoltage protection circuit for power over Ethernet in the embodiment of the present invention, the protection circuit for preventing the operation caused by the pulse of the power supply voltage V _DD includes: The thirteenth PMOS transistor M13, the eleventh PMOS transistor (M11) and the tenth PMOS transistor (M10) connected in parallel to the twelfth PMOS transistor M12 of the bandgap comparison circuit 3,

Wherein the eleventh PMOS transistor (M11) and the tenth PMOS transistor (M10) are connected in parallel between the internal power supply voltage (V _CC ) and the source of the thirteenth PMOS transistor (M13), Wherein the source and substrate of the eleventh PMOS transistor (M11) are connected to the internal power supply voltage (V _CC ), the drain of the eleventh PMOS transistor (M11) is connected to the thirteenth PMOS transistor (M13) source is connected, the drain of the eleventh PMOS transistor (M11) is connected to the source of the thirteenth PMOS transistor (M13), the gate of the eleventh PMOS transistor (M11) is connected to The gate of the first PMOS transistor (M1) of the first bias circuit is connected, and the eleventh PMOS transistor (M11) generates a fourth mirror current (I _C4 ) of the fourth mirror current source branch;

The source and substrate of the tenth PMOS transistor (M10) are connected to the internal power supply voltage (V _CC ), and the drain of the tenth PMOS transistor (M10) is connected to the thirteenth PMOS transistor (M13 ), the drain of the tenth PMOS transistor (M10) generates the fifth mirror current (I _C5 ) of the fifth mirror current branch; wherein the tenth PMOS transistor M10 accelerates the power supply voltage to reach the rising threshold voltage The level inversion speed of the bandgap comparison circuit 3 reduces the response time of the comparator, and the bias current provided by the eleventh PMOS transistor M11 is the fourth mirror current I _C4 .

The drain of the thirteenth PMOS transistor M13 is connected to the ground in parallel with the drain of the twelfth PMOS transistor M12, and the gate of the thirteenth PMOS transistor M13 is connected to the second bias voltage V _bias2 and the twelfth PMOS transistor M13. The input voltage connected to the gate of the PMOS transistor M12 is compared, the source of the thirteenth PMOS transistor M13 is connected in parallel to the source of the twelfth PMOS transistor M12, and the substrate of the thirteenth PMOS transistor M13 connected to the source of the thirteenth PMOS transistor M13, the substrate of the twelfth PMOS transistor M12 is connected to the source of the twelfth PMOS transistor M12, the second bias voltage V _bias2 and the After comparing the input voltage, the source of the twelfth PMOS transistor M12 outputs a voltage.

The present invention does not directly input the output of the resistance divider circuit 1 to the bandgap comparator circuit 3, but first inputs it to the twelfth PMOS transistor M12. Since the twelfth PMOS transistor M12 is a source follower, the output of the input signal is raised. Level, the voltage V _D at point D increases with the increase of the power supply voltage V _DD , so because the input voltage is first input to the twelfth PMOS transistor M12, and by the principle of the source follower, V _D =Vin+V _GS12 means that the input voltage has been boosted after passing through M12, so the inversion point of the UVLO circuit is premised, that is, the value of the turn-on voltage V _{UVLO_R} is reduced, and the power supply voltage V _DD is powered on and started quickly.

The thirteenth PMOS transistor M13 prevents misoperation caused by the power supply voltage V _DD pulse by comparing with the input voltage.

Since the present invention combines a reference voltage source and a comparator to form a bandgap comparison circuit 3, in the undervoltage protection circuit for power over Ethernet in the embodiment of the present invention, the bandgap comparison circuit 3 includes: generating a reference voltage The bandgap reference structure 31, the load circuit that generates the current source branch current, the second stage output circuit, the startup clamp circuit and the logic circuit 32.

Wherein the logic circuit 32 includes a Schmitt trigger SMT and a second inverter INV2, wherein, the input terminal of the Schmitt trigger SMT is connected to the output circuit of the second stage of the bandgap comparison circuit 3 The output end of the drain of the nineteenth PMOS transistor M19 is connected to output the UVLO signal of the undervoltage protection circuit through the second inverter INV2, and the second inverter INV2 is connected to the first An inverter INV1 is connected to feed back the UVLO signal to the input terminal of the first inverter INV1.

Wherein the bandgap reference structure 31 includes: a fourteenth PMOS transistor M14, a seventeenth PMOS transistor M17, a first triode Q1, a second triode Q2, a first resistor R1 and a second resistor R2,

Wherein, the source and the substrate of the fourteenth PMOS transistor M14 are connected to the internal power supply voltage V _CC ;

The drain of the fourteenth PMOS transistor M14 is connected to the source of the seventeenth PMOS transistor M17, and the substrate of the seventeenth PMOS transistor M17 is connected to the source of the seventeenth PMOS transistor M17;

The gate of the fourteenth PMOS transistor M14 is connected to the gate of the first PMOS transistor M1 of the first bias circuit, and generates a third mirror current I _C3 of a third mirror current source branch;

The base of the second transistor Q2 is connected to the source of the thirteenth PMOS transistor M13, and the base of the second transistor Q2 is connected to the base of the first transistor Q1 as a comparison voltage input terminal;

The collector of the second transistor Q2 is connected to the drain of the fifteenth PMOS transistor M15 of the load circuit to generate a second mirror current I _C2 of the second mirror current source branch;

The collector of the first triode Q1 is connected to the drain of the sixteenth PMOS transistor M16 of the load circuit to generate a first mirror current I _C1 of the first mirror current source branch;

The emitter of the second transistor Q2 is connected to the emitter of the first transistor Q1 through the second resistor R2, and the emitter of the first transistor Q1 is connected to the emitter of the first transistor Q1 through the first resistor R1 The source of the seventeenth PMOS transistor M17 is connected, the substrate of the seventeenth PMOS transistor M17 is connected to the source of the seventeenth PMOS transistor M17, and the gate and drain of the seventeenth PMOS transistor M17 are both grounded.

The core structure of the bandgap comparison circuit 3 is formed by the fourteenth PMOS transistor M14, the seventeenth PMOS transistor M17, the second triode Q2, the first triode Q1, the second resistor R2 and the first resistor R1 to generate a reference The optimized circuit greatly accelerates the 3-level inversion speed of the bandgap comparator circuit when the power supply voltage reaches the rising threshold, and at the same time reduces the response time of the comparator.

As shown in Figure 2, the relationship between i _c1 , i _c2 and the input voltage V _D. When the circuit is just powered on, the V _DD voltage rises slowly. At the beginning, the V _D voltage is lower than the bandgap comparison circuit 3 flipping threshold voltage V _TH (the value of V _D when I _C1 = I _C2 ), and I _C2 is greater than I _C1 , so A The voltage at point B is higher than the voltage at point B, and the UVLO signal outputs a low level; when the signal V _D gradually increases from low, the current i _c1 and i _c2 both increase, and the slope of the i _c2 curve is smaller than the slope of the i _c1 curve. When V _DD rises to V _{UVLO_R} , that is, when V _D reaches the inversion threshold V _TH of the bandgap reference comparator, i _c1 =i _c2 , the voltage at point A is equal to the voltage at point B, and this is the critical state of inversion; in the critical state of inversion, ΔV _BE =V _BE1 -V _BE2 = _ic2 R2=V _T ln(4), V _BE1 and V _BE2 are the transmitter-base voltages of the first transistor Q1 and the second transistor Q2 respectively, then Solve i _c2 =V _T ln(4)/R2, and set the current of M14 as i _c3 , so at the turning point, the current flowing through point C is 2i _c2 +i _c3 , when it is in the critical state of turning point, there is no I _C1 , I _C2 two currents, at this time I _C1 = I _C2 , plus I _C3 branch current. From this we can know that the voltage at point C is:

Wherein, i _c2 =V _T ln(4)/R2, and i _c3 is the mirror current of the current mirror.

The base voltage of the first triode Q1 is the inversion threshold voltage V _TH , that is,

Wherein, i _c2 =V _T ln(4)/R2, and i _c3 is the mirror current of the current mirror.

Therefore, the inversion threshold voltage of the bandgap comparator circuit 3 is equal to V _TH , in formula (2), i _c3 is a negative temperature coefficient, but 2i _c2 +i _c3 is a positive temperature coefficient, and the first item in (2) is V _BE1 Negative temperature coefficient, the last three items are positive temperature coefficients, so after reasonable adjustment, the flipping threshold voltage independent of temperature and power supply voltage can be obtained.

When V _DD is greater than V _{UVLO_R} , the UVLO signal is inverted and outputs a high level. The reason why the slope of the i _c2 curve is smaller than the slope of the i _c1 curve is that the voltage V _D is delivered to the bases of the first triode Q1 and the second triode Q2, and in the bandgap reference structure 31, the first triode The emitter area ratio of Q1 and the second transistor Q2 is 1:4, then the transconductance relationship of the two transistors is:

4gm1=gm2 (1)

Due to the emitter feedback effect of the first resistor R1 and the second resistor R2, the equivalent transconductance of the first transistor Q1 and the second transistor Q2 is:

Substituting g _m2 in formula (2) into formula (1) and rearranging, we get:

and

Generally choose gm1R2>>1, then Gm1>Gm2. Therefore, when the power supply voltage V _DD of the chip fluctuates, the collector current I _{C1 of the first transistor Q1 changes more than the collector current I C2 of} the second transistor Q2 . Therefore, at the beginning, I _C2 is greater than I _C1 , and M15 and M16 have the same width-to-length ratio, so the voltage drop through M15 is greater than the voltage drop through M16, so the voltage at point B is lower than that at point A.

It is precisely because Gm1>Gm2 that the collector current I _C1 of the first triode Q1 changes greatly compared to the collector current I _C2 of the second triode Q2, so when their bases input the same voltage , the slope of I _C2 is smaller than that of I _C1 .

In another embodiment of the present invention, in the undervoltage protection circuit for Power over Ethernet, the load circuit that generates the branch current of the current source includes:

A sixteenth PMOS transistor (M16), a fifteenth PMOS transistor M15 and a second capacitor C2;

Wherein the sixteenth PMOS transistor M16 and the fifteenth PMOS transistor M15 form a mirror current source, and the self-bias voltage V _bias generated by the gate of the fifteenth PMOS transistor M15 is input to the sixteenth PMOS transistor M16 The gate, the source and the substrate of the sixteenth PMOS transistor M16 are connected to the internal power supply voltage V _CC ;

The source and substrate of the fifteenth PMOS transistor M15 are connected to the internal power supply voltage V _CC , the gate of the fifteenth PMOS transistor M15 is connected to the drain of the fifteenth PMOS transistor M15, so The gate of the fifteenth PMOS transistor M15 is connected to the gate of the seventh PMOS transistor M7 of the comparison voltage generating circuit;

The fifteenth PMOS transistor M15 and the tenth PMOS transistor M10 form a mirror current source, and the self-bias voltage V _bias generated by the gate of the fifteenth PMOS transistor M15 is input to the gate of the tenth PMOS transistor M10 .

As shown in FIG. 4, when the bandgap comparator circuit 3 is activated and the branch of the fifteenth PMOS transistor M15 is turned on, the voltage V _bias generated by its self-bias is input to the gate of the tenth PMOS transistor M10, forming a mirror image relationship. Its mirror current source is like the tenth PMOS transistor M10, and the tenth PMOS transistor M10 is turned on, which accelerates the rise of V _D , and once again accelerates the level flipping speed of the bandgap comparison circuit 3 when the power supply voltage reaches the rising threshold, which accelerates this The inversion of the bandgap comparator circuit 3 greatly reduces the response time of the comparator.

In still another embodiment of the present invention, in the under-voltage protection circuit for Power over Ethernet, the second-stage output circuit includes: a nineteenth PMOS transistor M19, a twentieth PMOS transistor M20, and a twenty-first PMOS transistor M21 and the twenty-ninth PMOS transistor M29, wherein the fifteenth PMOS transistor M15 and the twenty-ninth PMOS transistor M29 form a mirror current source, and the source and substrate of the twenty-ninth PMOS transistor M29 are connected to The internal power supply voltage V _CC , the drain of the twenty-ninth PMOS transistor M29 is connected to the drain of the twenty-ninth PMOS transistor M20, and the self-bias voltage V _bias generated by the gate of the fifteenth PMOS transistor M15 Input to the gate of the twenty-ninth PMOS transistor M29 to generate the sixth mirror current I _C6 of the sixth mirror current branch;

The twentieth PMOS transistor M20 and the twenty-first PMOS transistor M21 form a mirror current source, the twentieth PMOS transistor M20 generates a seventh mirror current I _C7 , and the gate of the twentieth PMOS transistor M20 connected to the gate of the twenty-first PMOS transistor M21, the gate of the twenty-first PMOS transistor M20 is connected to the drain of the twenty-first PMOS transistor M20, and the source of the twenty-first PMOS transistor M20 The pole and the substrate are grounded, the source and the substrate of the twenty-first PMOS transistor M21 are grounded, and the twenty-first PMOS transistor M20 generates an eighth mirror current I _C8 ;

The gate of the nineteenth PMOS transistor M19 is connected to the collector of the first triode Q1 of the bandgap reference structure 31, and the source and substrate of the nineteenth PMOS transistor M19 are connected to the The internal power supply voltage V _CC , the drain of the nineteenth PMOS transistor M19 is connected to the drain of the twenty-first PMOS transistor M21 to generate the output voltage of the second-stage output circuit.

In still another embodiment of the present invention, in the undervoltage protection circuit for Power over Ethernet, the start-up clamping circuit includes: an eighteenth PMOS transistor M18, a twenty-second PMOS transistor M22, and a twenty-third PMOS transistor M23 , the twenty-fourth PMOS transistor M24, the twenty-fifth PMOS transistor M25, the twenty-sixth PMOS transistor M26, the twenty-seventh PMOS transistor M27, the twenty-eighth PMOS transistor M28, the third capacitor C3 and the fifth capacitor C5 ,

Wherein the drain of the eighteenth PMOS transistor M18 is connected to the gate of the nineteenth PMOS transistor M19 of the second-stage output circuit, and the drain of the nineteenth PMOS transistor M19 is connected in parallel to a ground The fifth capacitor C5; the source and substrate of the eighteenth PMOS transistor M18 are connected to the internal power supply voltage V _CC , the gate of the eighteenth PMOS transistor M18 is connected to the twenty-seventh PMOS transistor The drain connection of M27;

The source and substrate of the twenty-second PMOS transistor M22 are connected to the internal power supply voltage V _CC , and the gate of the twenty-second PMOS transistor M22 is connected to the first PMOS transistor of the first bias circuit. The gate of the transistor M1 is connected, and the drain of the twenty-second PMOS transistor M22 is connected to the source of the twenty-fifth PMOS transistor M25;

The substrate of the twenty-fifth PMOS transistor M25 is connected to the internal power supply voltage V _CC , the drain of the twenty-fifth PMOS transistor M25 is connected to the drain of the twenty-sixth PMOS transistor M26, so The drain of the twenty-fifth PMOS transistor M25 is connected to the gate of the twenty-third PMOS transistor M23, and the gate of the twenty-fifth PMOS transistor M25 is connected to the gate of the twenty-sixth PMOS transistor M26. and the gate of the twenty-sixth PMOS transistor M26 is grounded through the third capacitor C3;

The source and the substrate of the twenty-sixth PMOS transistor M26 are grounded;

The drain of the twenty-third PMOS transistor M23 is connected in parallel to the drain of the nineteenth PMOS transistor M19 output from the second stage, the substrate of the twenty-third PMOS transistor M23 is grounded, and the second The source of the twenty-third PMOS transistor M23 is connected to the drain of the twenty-fourth PMOS transistor M24;

The source and the substrate of the twenty-fourth PMOS transistor M24 are grounded, and the gate of the twenty-fourth PMOS transistor M24 is connected to the gate of the second PMOS transistor M2 of the first bias circuit;

The source and substrate of the twenty-seventh PMOS transistor M27 are connected to the internal power supply voltage V _CC , and the gate of the twenty-seventh PMOS transistor M27 is connected to the seventh PMOS of the comparison voltage generating circuit. The gate of the transistor M7 is connected, the drain of the twenty-seventh PMOS transistor M27 is connected to the drain of the twenty-eighth PMOS transistor M28, and the gate of the twenty-sixth PMOS transistor M26 is connected in parallel to the drain of the twenty-sixth PMOS transistor M26. 28 PMOS transistor M28 drain;

The source and substrate of the twenty-eighth PMOS transistor M28 are grounded, and the gate of the twenty-eighth PMOS transistor M28 is connected to the gate of the second PMOS transistor M2 of the first bias circuit.

When the circuit is powered on, the twenty-fourth PMOS transistor M24 and the twenty-eighth PMOS transistor M28 are mirrored and turned on, and the twenty-seventh PMOS transistor M27 is not turned on, so VF is low , so the eighteenth PMOS transistor M18, the twenty-third PMOS transistor M23, and the twenty-fifth PMOS transistor M25 are turned on, forcing the voltage at point A to be at a high level, and the second-stage output voltage at point E to be at a low level. The purpose is to force the output signal UVLO to be low.

The divided voltage output terminal V _D of the resistance voltage divider circuit 1 is connected to the comparison voltage input terminal of the bandgap comparator circuit 3, and the output terminal of the bandgap comparator circuit 3 is input to the input terminal of the logic circuit 32, and after shaping by the logic circuit 32 The output terminal UVLO of the output undervoltage protection circuit; the UVLO signal is fed back to the resistance voltage divider circuit 1. When the bandgap comparison circuit 3 outputs a high level, the resistance voltage divider circuit 1 outputs a higher level through the two-choice switch of the voltage selection circuit 2 High divider voltage. In this way, the PoE interface and the power supply voltage of the DC/DC controller can be monitored, and at the same time, high conversion efficiency and an inversion threshold voltage with little variation with input voltage and temperature can be obtained. The bandgap comparison circuit 3 realizes the functions of the bandgap reference circuit and the comparator, which not only optimizes the circuit structure, but also reduces the circuit area, reduces power consumption, and accelerates the response speed of the circuit.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (10)

1. An undervoltage protection circuit for Power over Ethernet, characterized in that, comprising: A resistor divider circuit for adjusting the flipping threshold voltage, and generating a first output voltage and a second output voltage; a voltage selection circuit, connected to the resistor divider circuit, and selects a voltage value from the first output voltage and the second output voltage; A bandgap comparator circuit, connected to the voltage selection circuit, used to use the voltage value selected by the voltage selection circuit or the voltage value of the protection circuit to prevent the pulse of the power supply voltage from being operated as an input voltage to generate an undervoltage Protection circuit UVLO signal; A bias circuit, wherein the bias circuit includes: a first bias circuit and a comparison voltage generating circuit; Wherein the first bias circuit comprises: a thirtieth PMOS transistor (M0), a second PMOS transistor (M2), a third PMOS transistor (M3), a first PMOS transistor (M1) and a fourth capacitor (C4), Wherein the gate of the thirtieth PMOS transistor (M0) is grounded, the source and substrate of the thirtieth PMOS transistor (M0) are connected to the internal power supply voltage (V _CC ), and the thirtieth PMOS transistor (M0) ) is connected to the drain of the second PMOS transistor (M2), and the drain of the second PMOS transistor (M2) is connected to the gate of the second PMOS transistor (M2); The source and the substrate of the second PMOS transistor (M2) are grounded; The source and the substrate of the third PMOS transistor (M3) are grounded; The gate of the third PMOS transistor (M3) is grounded through the fourth capacitor (C4), the gate of the second PMOS transistor (M2) and the gate of the third PMOS transistor (M3) are the The bandgap comparator circuit provides a first bias current (inp1); The gate of the second PMOS transistor (M2) is connected to the gate of the first PMOS transistor (M1) through a diode, and the drain of the first PMOS transistor (M1) is connected to the gate of the third PMOS transistor (M3 ) is connected to the drain, the source and substrate of the first PMOS transistor (M1) are connected to the internal power supply voltage (V _CC ), and the gate of the first PMOS transistor (M1) provides the first bias current (inp1); Wherein the comparison voltage generating circuit includes: a sixth PMOS transistor (M6), a seventh PMOS transistor (M7), an eighth PMOS transistor (M8), a ninth PMOS transistor (M9) and a first capacitor (C1), the The first PMOS transistor (M1) and the sixth PMOS transistor (M6) of the first bias circuit form a mirror current source, and the first bias provided by the gate of the first PMOS transistor (M1) current (inp1) to the gate of said sixth PMOS transistor (M6); The source and substrate of the sixth PMOS transistor (M6) are connected to the internal power supply voltage (V _CC ), and the source and substrate of the seventh PMOS transistor (M7) are connected to the internal power supply voltage ( V _CC ), the gate of the seventh PMOS transistor (M7) is connected to the gate of the fifteenth PMOS transistor (M15) of the bandgap comparison circuit, and the gate of the fifteenth PMOS transistor M15 generates self-bias voltage V _bias ), the drain of the seventh PMOS transistor (M7) is connected to the drain of the sixth PMOS transistor (M6), and the drain of the seventh PMOS transistor (M7) is connected to the eighth PMOS transistor (M7). The source of the PMOS transistor (M8) is connected, the substrate of the eighth PMOS transistor (M8) is connected to the source of the eighth PMOS transistor (M8), and the drain of the sixth PMOS transistor (M6) outputting a second bias voltage (V _bias2 ); The drain of the eighth PMOS transistor (M8) is short-circuited to the gate of the eighth PMOS transistor (M8), and the drain of the eighth PMOS transistor (M8) is connected to the ninth PMOS transistor (M9) ), the substrate of the ninth PMOS transistor (M9) is connected to the source electrode of the ninth PMOS transistor (M9); The gate of the ninth PMOS transistor (M9) and the drain of the ninth PMOS transistor (M9) are grounded through a first capacitor (C1); The feedback control loop provided between the resistance voltage divider circuit and the bandgap comparison circuit is used to output a higher level of the UVLO signal through the voltage selection circuit when the output of the UVLO signal is at a high level. For the first output voltage, when the output of the UVLO signal is at a low level, a lower second output voltage is output. 2. The undervoltage protection circuit for Power over Ethernet according to claim 1, characterized in that, the resistor divider circuit comprises: a third resistor (R3), a fourth resistor (R4) and a fifth resistor ( R5), wherein one end of the third resistor (R3) is connected to the power supply voltage (V _DD ), and the other end of the third resistor (R3) is connected in series with one end of the fourth resistor (R4), the The first output voltage (V1) is formed between the third resistor (R3) and the fourth resistor (R4), and the first output voltage (V1) is used as the input voltage of the voltage selection circuit; One end of the fifth resistor (R5) is connected in series with the other end of the fourth resistor (R4), and the other end of the fifth resistor (R5) is grounded, and the fourth resistor (R4) and the fifth resistor The second output voltage (V2) is formed between the resistors (R5), and the second output voltage (V2) is used as the output voltage of the voltage selection circuit. 3. The undervoltage protection circuit for Power over Ethernet according to claim 2, characterized in that, the voltage selection circuit comprises: a fourth PMOS transistor (M4), a fifth PMOS transistor (M5) and a first inverter phase device (INV1), wherein the gate of the fifth PMOS transistor (M5) is connected to the input terminal of the first inverter (INV1); The gate of the fourth PMOS transistor (M4) is connected to the output terminal of the first inverter (INV1); The drain of the fourth PMOS transistor (M4) is connected to the second output voltage (V2) of the resistor divider circuit; The drain of the fifth PMOS transistor (M5) is connected to the first output voltage (V1) of the resistor divider circuit; The source of the fifth PMOS transistor (M5) is connected to the source of the fourth PMOS transistor (M4), and the substrate of the fifth PMOS transistor (M5) is connected in series with the substrate of the fourth PMOS transistor (M4) Together, the substrate of the fifth PMOS transistor (M5) is connected to the source of the fifth PMOS transistor (M5), and the source of the fifth PMOS transistor (M5) is connected to the bandgap comparison circuit The gate of the twelfth PMOS transistor (M12) is connected, and the source of the fifth PMOS transistor (M5) outputs the output voltage (Vin) of the voltage selection circuit, and the output voltage (Vin) is used as the A bandgap comparator circuit provides the input voltage. 4. The undervoltage protection circuit for Power over Ethernet according to claim 3, characterized in that, the protection circuit for preventing the operation caused by the pulse of the power supply voltage (V _DD ) comprises: comparing with the bandgap The twelfth PMOS transistor (M12) of the circuit is connected in parallel with the thirteenth PMOS transistor (M13), the eleventh PMOS transistor (M11) and the tenth PMOS transistor (M10), Wherein the eleventh PMOS transistor (M11) and the tenth PMOS transistor (M10) are connected in parallel between the internal power supply voltage (V _CC ) and the source of the thirteenth PMOS transistor (M13), Wherein the source and substrate of the eleventh PMOS transistor (M11) are connected to the internal power supply voltage (V _CC ), the drain of the eleventh PMOS transistor (M11) is connected to the thirteenth PMOS transistor (M13) source is connected, the drain of the eleventh PMOS transistor (M11) is connected to the source of the thirteenth PMOS transistor (M13), the gate of the eleventh PMOS transistor (M11) is connected to The gate of the first PMOS transistor (M1) of the first bias circuit is connected, and the eleventh PMOS transistor (M11) generates a fourth mirror current (I _C4 ) of the fourth mirror current source branch; The source and substrate of the tenth PMOS transistor (M10) are connected to the internal power supply voltage (V _CC ), and the drain of the tenth PMOS transistor (M10) is connected to the thirteenth PMOS transistor (M13 ), the drain of the tenth PMOS transistor (M10) generates the fifth mirror current (I _C5 ) of the fifth mirror current branch; The drain of the thirteenth PMOS transistor (M13) is connected to the ground in parallel with the drain of the twelfth PMOS transistor (M12), and the gate of the thirteenth PMOS transistor (M13) is connected to the second bias voltage (V _bias2 ) is compared with the input voltage connected to the gate of the twelfth PMOS transistor (M12), and the source of the thirteenth PMOS transistor (M13) is connected in parallel to the twelfth PMOS transistor (M12) source, the substrate of the thirteenth PMOS transistor (M13) is connected to the source of the thirteenth PMOS transistor (M13), and the substrate of the twelfth PMOS transistor (M12) is connected to the source of the thirteenth PMOS transistor (M12). sources of twelve PMOS transistors (M12), the source of the twelfth PMOS transistors (M12) outputs a voltage after comparing the second bias voltage (V _bias2 ) with the input voltage. 5. The undervoltage protection circuit for Power over Ethernet according to claim 4, wherein the bandgap comparison circuit comprises: a bandgap reference structure generating a reference voltage, a load circuit generating a current source branch current , Second stage output circuit, start clamping circuit and logic circuit. 6. The undervoltage protection circuit for Power over Ethernet according to claim 5, characterized in that, the logic circuit comprises a Schmitt trigger (SMT) and a second inverter (INV2), Wherein, the input end of the Schmitt trigger (SMT) is connected with the output end of the drain of the nineteenth PMOS transistor (M19) of the second stage output circuit of the bandgap comparison circuit, through the The second inverter (INV2) outputs the UVLO signal of the undervoltage protection circuit, and the second inverter (INV2) is connected to the first inverter (INV1) to feed back the UVLO signal to the input of the first inverter (INV1). 7. The undervoltage protection circuit for Power over Ethernet according to claim 6, characterized in that, the bandgap reference structure comprises: a fourteenth PMOS transistor (M14), a seventeenth PMOS transistor (M17), The first transistor (Q1), the second transistor (Q2), the first resistor (R1) and the second resistor (R2), Wherein, the source and substrate of the fourteenth PMOS transistor (M14) are connected to the internal power supply voltage (V _CC ); The drain of the fourteenth PMOS transistor (M14) is connected to the source of the seventeenth PMOS transistor (M17), and the substrate of the seventeenth PMOS transistor (M17) is connected to the seventeenth PMOS transistor (M17). the source of the transistor (M17); The gate of the fourteenth PMOS transistor (M14) is connected to the gate of the first PMOS transistor (M1) of the first bias circuit, and generates a third mirror current of the third mirror current source branch ( _IC3 ); The base of the second transistor (Q2) is connected to the source of the thirteenth PMOS transistor (M13), and the base of the second transistor (Q2) is connected to the first transistor (Q1 ) base connection as a comparison voltage input; The collector of the second triode (Q2) is connected to the drain of the fifteenth PMOS transistor (M15) of the load circuit to generate a second mirror current (I _C2 ) of the second mirror current source branch; The collector of the first triode (Q1) is connected to the drain of the sixteenth PMOS transistor (M16) of the load circuit to generate the first mirror current (I _C1 ) of the first mirror current source branch; The emitter of the second triode (Q2) is connected to the emitter of the first triode (Q1) via the second resistor (R2), and the emitter of the first triode (Q1) The source of the seventeenth PMOS transistor (M17) connected via the first resistor (R1), the substrate of the seventeenth PMOS transistor (M17) is connected to the source of the seventeenth PMOS transistor (M17) , both the gate and the drain of the seventeenth PMOS transistor (M17) are grounded. 8. The undervoltage protection circuit for Power over Ethernet according to claim 7, characterized in that, the load circuit generating the branch current of the current source comprises: A sixteenth PMOS transistor (M16), a fifteenth PMOS transistor (M15) and a second capacitor (C2); Wherein the sixteenth PMOS transistor (M16) and the fifteenth PMOS transistor (M15) form a mirror current source, and the self-bias voltage V _bias generated by the gate of the fifteenth PMOS transistor (M15) is input to the first the gate of the sixteenth PMOS transistor (M16), the source and substrate of the sixteenth PMOS transistor (M16) are connected to the internal supply voltage (V _CC ); The source and substrate of the fifteenth PMOS transistor (M15) are connected to the internal power supply voltage (V _CC ), and the gate of the fifteenth PMOS transistor (M15) is connected to the fifteenth PMOS transistor (M15), the gate of the fifteenth PMOS transistor (M15) is connected to the gate of the seventh PMOS transistor (M7) of the comparison voltage generating circuit; The fifteenth PMOS transistor (M15) and the tenth PMOS transistor (M10) form a mirror current source, and the self-bias voltage V _bias generated by the gate of the fifteenth PMOS transistor M15 is input to the tenth PMOS transistor ( M10) gate. 9. The undervoltage protection circuit for Power over Ethernet according to claim 8, characterized in that, the second stage output circuit comprises: a nineteenth PMOS transistor (M19), a twentieth PMOS transistor (M20) , the twenty-first PMOS transistor (M21) and the twenty-ninth PMOS transistor (M29), wherein the fifteenth PMOS transistor (M15) and the twenty-ninth PMOS transistor (M29) form a mirror current source, so The source and substrate of the twenty-ninth PMOS transistor (M29) are connected to the internal power supply voltage (V _CC ), the drain of the twenty-ninth PMOS transistor (M29) is connected to the twenty-ninth PMOS transistor The drain of (M20) is connected, and the self-bias voltage V _bias generated by the gate of the fifteenth PMOS transistor M15 is input to the gate of the twenty-ninth PMOS transistor M29 to generate the sixth mirror image of the sixth mirror current branch current (I _C6 ); The 20th PMOS transistor (M20) and the 21st PMOS transistor (M21) form a mirror current source, and the 20th PMOS transistor (M20) generates a seventh mirror current (I _C7 ), and the 20th PMOS transistor (M20) generates a seventh mirror current (I C7 ). The gates of the twenty PMOS transistors (M20) are connected to the gates of the twenty-first PMOS transistors (M21), and the gates of the twenty PMOS transistors (M20) are connected to the gates of the twenty PMOS transistors (M20). ), the source and substrate of the twentieth PMOS transistor (M20) are grounded, the source and substrate of the twenty-first PMOS transistor (M21) are grounded, and the twentieth PMOS transistor (M20) generates an eighth mirror current (I _C8 ); The gate of the nineteenth PMOS transistor (M19) is connected to the collector of the first triode (Q1) of the bandgap reference structure, and the source of the nineteenth PMOS transistor (M19) and The substrate is connected to the internal power supply voltage (V _CC ), the drain of the nineteenth PMOS transistor (M19) is connected to the drain of the twenty-first PMOS transistor (M21), generating a second-stage output circuit output voltage. 10. The undervoltage protection circuit for Power over Ethernet according to claim 9, characterized in that, the startup clamping circuit comprises: an eighteenth PMOS transistor (M18), a twenty-second PMOS transistor (M22) , twenty-third PMOS transistor (M23), twenty-fourth PMOS transistor (M24), twenty-fifth PMOS transistor (M25), twenty-sixth PMOS transistor (M26), twenty-seventh PMOS transistor (M27) , the twenty-eighth PMOS transistor (M28), the third capacitor (C3) and the fifth capacitor (C5), Wherein the drain of the eighteenth PMOS transistor (M18) is connected to the gate of the nineteenth PMOS transistor (M19) of the second-stage output circuit, and the drain of the nineteenth PMOS transistor (M19) The pole is connected in parallel with a grounded fifth capacitor (C5); the source and substrate of the eighteenth PMOS transistor (M18) are connected to the internal power supply voltage (V _CC ), and the eighteenth PMOS transistor ( the connection of the gate of M18) to the drain of said twenty-seventh PMOS transistor (M27); The source and substrate of the twenty-second PMOS transistor (M22) are connected to the internal power supply voltage (V _CC ), and the gate of the twenty-second PMOS transistor (M22) is connected to the first bias The gate of the circuit-connected first PMOS transistor (M1) is connected, the drain of the twenty-second PMOS transistor (M22) is connected to the source of the twenty-fifth PMOS transistor (M25); The substrate of the twenty-fifth PMOS transistor (M25) is connected to the internal power supply voltage (V _CC ), and the drain of the twenty-fifth PMOS transistor (M25) is connected to the twenty-sixth PMOS transistor ( M26), the drain of the twenty-fifth PMOS transistor (M25) is connected to the gate of the twenty-third PMOS transistor (M23), the twenty-fifth PMOS transistor (M25) The gate is connected to the gate of the twenty-sixth PMOS transistor (M26), and the gate of the twenty-sixth PMOS transistor (M26) is grounded through the third capacitor (C3); The source and the substrate of the twenty-sixth PMOS transistor (M26) are grounded; The drain of the twenty-third PMOS transistor (M23) is connected in parallel to the drain of the nineteenth PMOS transistor (M19) output by the second stage, and the substrate of the twenty-third PMOS transistor (M23) The bottom is grounded, and the source of the twenty-third PMOS transistor (M23) is connected to the drain of the twenty-fourth PMOS transistor (M24); The source and substrate of the twenty-fourth PMOS transistor (M24) are grounded, and the gate of the twenty-fourth PMOS transistor (M24) is connected to the second PMOS transistor (M2) of the first bias circuit. ) connected to the grid; The source and substrate of the twenty-seventh PMOS transistor (M27) are connected to the internal power supply voltage (V _CC ), and the gate of the twenty-seventh PMOS transistor (M27) is connected to the comparison voltage generation circuit The gate of the seventh PMOS transistor (M7) is connected, the drain of the twenty-seventh PMOS transistor (M27) is connected to the drain of the twenty-eighth PMOS transistor (M28), and the twenty-eighth PMOS transistor (M28) is connected to the drain. The gates of the six PMOS transistors (M26) are connected in parallel to the drain of the twenty-eighth PMOS transistor (M28); The source and substrate of the twenty-eighth PMOS transistor (M28) are grounded, and the gate of the twenty-eighth PMOS transistor (M28) is connected to the first bias circuit of the first PMOS transistor (M1) connected to the grid.