CN104113041B - A kind of under-voltage protecting circuit for POE - Google Patents
A kind of under-voltage protecting circuit for POE Download PDFInfo
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- CN104113041B CN104113041B CN201410239862.XA CN201410239862A CN104113041B CN 104113041 B CN104113041 B CN 104113041B CN 201410239862 A CN201410239862 A CN 201410239862A CN 104113041 B CN104113041 B CN 104113041B
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Abstract
The present invention provides a kind of under-voltage protecting circuit for POE, and the under-voltage protecting circuit for POE includes：The resistor voltage divider circuit of upset threshold voltage is adjusted, and produces the first output voltage and the second output voltage；Voltage selecting circuit, is connected with resistor voltage divider circuit, selects a magnitude of voltage from the first output voltage and the second output voltage；Band gap comparison circuit, is connected with voltage selecting circuit, is caused by the magnitude of voltage of voltage selecting circuit selection or using the pulse for preventing supply voltage the magnitude of voltage of the protection circuit of operation as input voltage, is produced under-voltage protecting circuit UVLO signals；The feedback control loop being arranged between resistor voltage divider circuit and band gap comparison circuit, when UVLO signal outputs are high level, UVLO signals export the first higher output voltage through voltage selecting circuit, UVLO signal outputs are low level, export the second relatively low output voltage.Band-gap comparator geometries shrink circuit area and the response speed of circuit is accelerated so.
Description
Technical field
The present invention relates to protection circuit field, more particularly to a kind of under-voltage protecting circuit for POE.
Background technology
Application recently as internet voice protocol VoIP and WLAN WLAN is more and more extensive, by with
Too net is more and more urgent to provide the demand of electric power in itself, and POE PoE technologies can also be carried while transmission data
For electric power support, therefore rapid popularization is obtained, PoE technologies are more and more applied to the network equipment.
Just because of widely using for PoE technologies, requirement of the people to its stability also more and more higher, to ensure that PoE is electric
Source can also normal work in the case of voltage pulsation.When power supply unit PSE completes the detection to powered device PD, is classified it
Afterwards, the definite power rank of PD has been known, supplying voltage can be raised, start to power for PD by PSE, so as to realize power supply electricity
Pressure is started from scratch；After supply voltage is charged to the cut-in voltage of chip, normal circuit operation；Due to internal module
Work, now the load current of system become big, chip power voltage can produce fluctuation, particularly chip high voltage area supply voltage
Fluctuation can be larger.If supply voltage is too low to cause very big power attenuation, therefore in order to ensure high voltage integrated circuit in core
Energy steady operation after piece unlatching, and also to avoid the infringement of chip wave propagation system, we are typically led to under-voltage protecting circuit
Chip power voltage is monitored.
At present, more common under-voltage protecting circuit is as shown in figure 1, the under-voltage protecting circuit includes power supply divider, base
Reference voltage source, comparator and logic circuit.Chip is opened when sampled voltage V1 exceedes by power supply divider sampling supply voltage
Voltage VUVLO_R, for low level, chip starts for UVLO upsets；When sampled voltage V2 is less than supply voltage VDD(off), under-voltage protection
Circuit U VLO signal is overturn as high level, chip shut-off.The under-voltage protecting circuit uses independent reference voltage source and comparator,
Cause the response time longer, take larger area and power consumption is big.
The content of the invention
It is an object of the invention to provide a kind of under-voltage protecting circuit for POE, solves traditional under-voltage circuit
Using independent reference voltage source and comparator, cause the response time longer, the problem that area occupied is larger and power consumption is big.
In order to solve above-mentioned technical problem, a kind of under-voltage protection electricity for POE provided in an embodiment of the present invention
Road, wherein, including：
For adjusting the resistor voltage divider circuit of upset threshold voltage, and produce the first output voltage and the second output voltage；
Voltage selecting circuit, is connected with the resistor voltage divider circuit, from first output voltage and second output
Voltage selects a magnitude of voltage；
Band gap comparison circuit, is connected with the voltage selecting circuit, described in the voltage selecting circuit is selected
The pulse for preventing supply voltage is caused the magnitude of voltage of the protection circuit of operation as input voltage by magnitude of voltage, is produced one and is owed
Voltage protection circuit UVLO signals；
The feedback control loop being arranged between the resistor voltage divider circuit and the band gap comparison circuit, for described
When UVLO signal outputs are high level, the UVLO signals export higher described first defeated through the voltage selecting circuit
Go out voltage, when the UVLO signal outputs are low level, export relatively low second output voltage.
Wherein, the described under-voltage protecting circuit for POE also includes：Biasing circuit, wherein the biased electrical
Road includes：First biasing circuit and comparison voltage produce circuit；
Wherein described first biasing circuit includes：30th PMOS transistor (M0), the second PMOS transistor (M2), the 3rd
PMOS transistor (M3), the first PMOS transistor (M1) and the 4th electric capacity (C4),
Wherein described 30th PMOS transistor (M0) grounded-grid, the source electrode of the 30th PMOS transistor (M0) and
Substrate is connected to internal power source voltage (VCC), drain electrode and second PMOS transistor of the 30th PMOS transistor (M0)
(M2) drain electrode connection, the drain electrode of second PMOS transistor (M2) are connected to the grid of second PMOS transistor (M2)
On；
The source electrode and Substrate ground of second PMOS transistor (M2)；
The source electrode and Substrate ground of the 3rd PMOS transistor (M3)；
The grid of the 3rd PMOS transistor (M3) is grounded by the 4th electric capacity (C4), the 2nd PMOS crystal
The grid (M3) of the grid and the 3rd PMOS transistor of pipe (M2) provides the first bias current for the band gap comparison circuit
(inp1)；
The grid of second PMOS transistor (M2) passes through the grid of diode and first PMOS transistor (M1)
Connection, the drain electrode of first PMOS transistor (M1) are connected with the drain electrode of the 3rd PMOS transistor (M3), and described first
The source electrode and substrate of PMOS transistor (M1) is connected to the internal power source voltage (VCC), first PMOS transistor (M1)
Grid provides first bias current (inp1)；
Wherein described comparison voltage produces circuit to be included：6th PMOS transistor (M6), the 7th PMOS transistor (M7),
Eight PMOS transistors (M8), the 9th PMOS transistor (M9) and the first electric capacity (C1), described the first of first biasing circuit
PMOS transistor (M1) forms mirror current source with the 6th PMOS transistor (M6), first PMOS transistor (M1)
Grid of first bias current (inp1) that grid is provided to the 6th PMOS transistor (M6)；
The source electrode and substrate of the 6th PMOS transistor (M6) is connected to the internal power source voltage (VCC), the described 7th
The source electrode and substrate of PMOS transistor (M7) is connected to the internal power source voltage (VCC), the 7th PMOS transistor (M7)
Grid is connected with the grid of the 15th PMOS transistor (M15) of the band gap comparison circuit, the 15th PMOS transistor
M15 grids produce self-bias voltage Vbias, drain electrode and the 6th PMOS transistor of the 7th PMOS transistor (M7)
(M6) drain electrode connection, the drain electrode of the 7th PMOS transistor (M7) are connected with the source electrode of the 8th PMOS transistor (M8)
Connect, the substrate of the 8th PMOS transistor (M8) is connected to the source electrode of the 8th PMOS transistor (M8), and the described 6th
The drain electrode of PMOS transistor (M6) exports the second bias voltage (Vbias2)；
The drain electrode (M8) of the 8th PMOS transistor and the grid short circuit of the 8th PMOS transistor (M8), described
The drain electrode (M8) of eight PMOSs is connected to the source electrode of the 9th PMOS (M9), the substrate connection of the 9th PMOS (M9)
In the source electrode of the 9th PMOS (M9)；
The grid of the 9th PMOS (M9) and the drain electrode of the 9th PMOS (M9) are connect by the first electric capacity (C1)
Ground.
Further, the resistor voltage divider circuit includes：3rd resistor (R3), the 4th resistance (R4) and the 5th resistance
(R5), wherein the 3rd resistor (R3) one end is connected to the supply voltage (VDD), and the 3rd resistor (R3) other end
One end of the 4th resistance (R4) is series at, described between the 3rd resistor (R3) and the 4th resistance (R4), is formed
One output voltage (V1), input voltage of first output voltage (V1) as the voltage selecting circuit；
Described 5th resistance (R5) one end is series at the other end of the 4th resistance (R4), and the 5th resistance (R5)
The other end ground connection, form second output voltage (V2) between the 4th resistance (R4) and the 5th resistance (R5),
Input voltage of first output voltage (V2) as the voltage selecting circuit.
Further, the voltage selecting circuit includes：4th PMOS transistor (M4), the 5th PMOS transistor (M5) and
First phase inverter (INV1),
The grid of wherein described 5th PMOS transistor (M5) is connected to the input of first phase inverter (INV1)；
The grid of the 4th PMOS transistor (M4) is connected to the output end of first phase inverter (INV1)；
Second output voltage (V2) of the drain electrode of the 4th PMOS transistor (M4) and the resistor voltage divider circuit
Connection；
First output voltage (V1) of the drain electrode of the 5th PMOS transistor (M5) and the resistor voltage divider circuit
Connection；
The source electrode of the 5th PMOS transistor (M5) is connected to the source electrode of the 4th PMOS transistor (M4), and the described 5th
The substrate of PMOS transistor (M5) is cascaded with the substrate of the 4th PMOS transistor (M4), the 5th PMOS transistor
(M5) substrate is connected to the source electrode of the 5th PMOS transistor (M5), and the source electrode of the 5th PMOS transistor (M5) with
The grid connection of the 12nd PMOS transistor (M12) of the band gap comparison circuit, by the 5th PMOS transistor (M5)
Source electrode exports the output voltage (Vin) of the voltage selecting circuit, and the output voltage (Vin) is used as the band gap comparison circuit
Input voltage is provided.
Further, it is described to prevent the supply voltage (VDD) pulse cause the protection circuit of operation to include：With it is described
13rd PMOS transistor (M13) of the 12nd PMOS transistor (M12) parallel connection of band gap comparison circuit, the 11st PMOS
Transistor (M11) and the tenth PMOS transistor (M10),
Wherein described 11st PMOS transistor (M11) and the tenth PMOS transistor (M10) are connected in parallel in described
Portion supply voltage (VCC) and the source electrode of the 13rd PMOS transistor (M13) between, wherein the 11st PMOS transistor
(M11) source electrode and substrate is connected to the internal power source voltage (VCC), the drain electrode of the 11st PMOS transistor (M11) with
The source electrode connection of the 13rd PMOS transistor (M13), the drain electrode and the described tenth of the 11st PMOS transistor (M11)
The source electrode of three PMOS transistors (M13), the grid of the 11st PMOS transistor (M11) and the of first biasing circuit
The grid connection of one PMOS transistor (M1), the 11st PMOS transistor (M11) produce the 4th mirror current source branch road
4th image current (IC4)；
The source electrode and substrate of the tenth PMOS transistor (M10) is connected to the internal power source voltage (VCC), described
The drain electrode of ten PMOS transistors (M10) is connected to the source electrode of the 13rd PMOS transistor (M13), the tenth PMOS crystal
The drain electrode of pipe (M10) produces the 5th image current (I of the 5th image current branch roadC5)；
13rd PMOS transistor (M13) drain electrode and the 12nd PMOS transistor (M12) drain electrode earth,
The grid of the 13rd PMOS transistor (M13) accesses the second bias voltage (Vbias2) with the 12nd PMOS transistor
(M12) input voltage that grid is accessed is made comparisons, and the sources connected in parallel of the 13rd PMOS transistor (M13) is in the described tenth
The source electrode of two PMOS transistors (M12), it is brilliant that the substrate of the 13rd PMOS transistor (M13) is connected to the 13rd PMOS
The source electrode of body pipe (M13), the substrate of the 12nd PMOS transistor (M12) are connected to the 12nd PMOS transistor
(M12) source electrode, the second bias voltage (Vbias2) compare with the input voltage after by the 12nd PMOS transistor
(M12) source output voltage.
Further, the band gap comparison circuit includes：Produce band-gap reference structure, the current source of reference voltage
The load circuit of road electric current, second level output circuit, start clamp circuit and logic circuit.
Further, the logic circuit includes Schmidt trigger (SMT) and the second phase inverter (INV2),
Wherein, the input of the Shi Misi triggers (SMT) is exported with the second level of the band gap comparison circuit
The output end connection of the drain electrode of the 19th PMOS transistor (M19) of circuit, it is defeated after the second phase inverter (INV2) described in
Go out the UVLO signals of the under-voltage protecting circuit, and second phase inverter (INV2) is with first phase inverter (INV1) even
Connect, the UVLO signals are fed back to into the input of first phase inverter (INV1).
Further, the band-gap reference structure includes：14th PMOS transistor (M14), the 17th PMOS transistor
(M17), the first triode (Q1), the second triode (Q2), first resistor (R1) and second resistance (R2),
Wherein, the source electrode and substrate of the 14th PMOS transistor (M14) is connected to the internal power source voltage (VCC)；
The drain electrode of the 14th PMOS transistor (M14) is connected to the source electrode of the 17th PMOS transistor (M17),
The substrate of the 17th PMOS transistor (M17) is connected to the source electrode of the 17th PMOS transistor (M17)；
The grid of the 14th PMOS transistor (M14) and first PMOS transistor of first biasing circuit
(M1) grid connection, and produce the 3rd image current (I of the 3rd mirror current source branch roadC3)；
The base stage of second triode (Q2) is connected with the source electrode of the 13rd PMOS transistor (M13), and the described 2nd 3
The base stage of pole pipe (Q2) is connected as comparison voltage input with the base stage of first triode (Q1)；
The drain electrode of the colelctor electrode of second triode (Q2) and the 15th PMOS transistor (M15) of the load circuit
Connection, produces the second image current (I of the second mirror current source branch roadC2)；
The drain electrode of the colelctor electrode of first triode (Q1) and the 16th PMOS transistor (M16) of the load circuit
Connection, produces the first image current (I of the first mirror current source branch roadC1)；
Second resistance (R2) described in the emitter stage Jing of second triode (Q2) is connected to first triode (Q1)
Emitter stage, the 17th PMOS transistor that first resistor (R1) described in the emitter stage Jing of first triode (Q1) connects
(M17) source electrode, the substrate of the 17th PMOS transistor (M17) are connected to the source electrode of the 17th PMOS transistor (M17),
The grid of the 17th PMOS transistor (M17) and drain electrode are grounded.
Further, the load circuit of the current source branch current includes：
16th PMOS transistor (M16), the 15th PMOS transistor (M15) and the second electric capacity (C2)；
Wherein described 16th PMOS transistor M16 forms mirror current source, institute with the 15th PMOS transistor M15
State the self-bias voltage V of the 15th PMOS transistor M15 grid generationbiasThe grid of the 16th PMOS transistor M16 is input to,
The source electrode and substrate of the 16th PMOS transistor (M16) is connected to the internal power source voltage (VCC)；
The source electrode and substrate of the 15th PMOS transistor (M15) is connected to the internal power source voltage (VCC), it is described
The grid of the 15th PMOS transistor (M15) is connected to the drain electrode of the 15th PMOS transistor (M15), and the described 15th
The grid of the 7th PMOS transistor (M7) that the grid of PMOS transistor (M15) produces circuit with the comparison voltage is connected；
15th PMOS transistor (M15) forms mirror current source with the tenth PMOS transistor (M10), described
The self-bias voltage V that 15th PMOS transistor M15 grid is producedbiasIt is input to the grid of the tenth PMOS transistor M10.
Further, the second level output circuit includes：19th PMOS transistor (M19), the 20th PMOS crystal
Pipe (M20), the 21st PMOS transistor (M21) and the 29th PMOS transistor (M29), wherein the 15th PMOS is brilliant
Body pipe (M15) forms mirror current source, the 29th PMOS transistor with the 29th PMOS transistor (M29)
(M29) source electrode and substrate is connected to the internal power source voltage (VCC), the drain electrode of the 29th PMOS transistor (M29)
Drain electrode with the 20th PMOS transistor (M20) is connected, the automatic biasing that the 15th PMOS transistor M15 grid is produced
Voltage VbiasThe grid of the 29th PMOS transistor M29 is input to, the 6th image current of the 6th image current branch road is produced
(IC6)；
20th PMOS transistor (M20) forms mirror current source with the 21st PMOS transistor (M21),
20th PMOS transistor (M20) produces the 7th image current (IC7), the grid of the 20th PMOS transistor (M20)
Be connected with the grid of the 21st PMOS transistor (M21), the grid of the 20th PMOS transistor (M20) with it is described
The drain electrode connection of the 20th PMOS transistor (M20), the source electrode and Substrate ground of the 20th PMOS transistor (M20), institute
The source electrode and Substrate ground of the 21st PMOS transistor (M21) are stated, the 20th PMOS transistor (M20) produces the 8th mirror
Image current (IC8)；
First triode (Q1) of the grid of the 19th PMOS transistor (M19) and the band-gap reference structure
Colelctor electrode connection, the source electrode and substrate of the 19th PMOS transistor (M19) are connected to the internal power source voltage (VCC),
The drain electrode of the 19th PMOS transistor (M19) is connected with the drain electrode of the 21st PMOS transistor (M21), produces the
The output voltage of two grades of output circuits.
Further, the startup clamp circuit includes：18th PMOS transistor (M18), the 22nd PMOS crystal
Pipe (M22), the 23rd PMOS transistor (M23), the 24th PMOS transistor (M24), the 25th PMOS transistor
(M25), the 26th PMOS transistor (M26), the 27th PMOS transistor (M27), the 28th PMOS transistor
(M28), the 3rd electric capacity (C3) and the 5th electric capacity (C5),
The drain electrode and the described 19th of the second level output circuit of wherein described 18th PMOS transistor (M18)
The grid connection of PMOS transistor (M19), the drain electrode of the 19th PMOS transistor (M19) are parallel to a ground connection the described 5th
Electric capacity (C5)；The source electrode and substrate of the 18th PMOS transistor (M18) is connected to the internal power source voltage (VCC), it is described
The grid of the 18th PMOS transistor (M18) and the connection of the drain electrode of the 27th PMOS transistor (M27)；
The source electrode and substrate of the 22nd PMOS transistor (M22) is connected to the internal power source voltage (VCC), institute
State the grid of the first PMOS transistor (M1) that the grid of the 22nd PMOS transistor (M22) is connected with first biasing circuit
Pole connects, and the drain electrode of the 22nd PMOS transistor (M22) is connected with the source electrode of the 25th PMOS transistor (M25)
Connect；
The substrate of the 25th PMOS transistor (M25) is connected to the internal power source voltage (VCC), described second
The drain electrode of 15 PMOS transistors (M25) is connected with the drain electrode of the 26th PMOS transistor (M26), and the described 25th
The drain electrode of PMOS transistor (M25) is connected with the grid of the 23rd PMOS transistor (M23), the 25th PMOS
The grid of transistor (M25) is connected with the grid of the 26th PMOS transistor (M26), and the 26th PMOS is brilliant
The grid of body pipe (M26) is grounded by the 3rd electric capacity (C3)；
The source electrode and Substrate ground of the 26th PMOS transistor (M26)；
The drain electrode of the 23rd PMOS transistor (M23) is parallel to the 19th PMOS of the second level output
The drain electrode of transistor (M19), the Substrate ground of the 23rd PMOS transistor (M23), the 23rd PMOS crystal
The source electrode of pipe (M23) is connected with the drain electrode of the 24th PMOS transistor (M24)；
The source electrode and Substrate ground of the 24th PMOS transistor (M24), the 24th PMOS transistor
(M24) grid is connected with the grid of second PMOS transistor M2 of first biasing circuit；
The source electrode and substrate of the 27th PMOS transistor (M27) is connected to the internal power source voltage (VCC), institute
The grid and the comparison voltage of stating the 27th PMOS transistor (M27) produce the 7th PMOS transistor (M7) of circuit
Grid connection, drain electrode and the 28th PMOS transistor (M28) of the 27th PMOS transistor (M27) drain
Connection, the gate connected in parallel of the 26th PMOS transistor (M26) drain in the 28th PMOS transistor (M28)；
The source electrode and Substrate ground of the 28th PMOS transistor (M28), the 28th PMOS transistor
(M28) grid is connected with the grid of the first PMOS transistor M2 described in first biasing circuit.
The above-mentioned technical proposal of the present invention has the beneficial effect that：
In the solution of the present invention, two magnitudes of voltage are produced by resistor voltage divider circuit, one is selected by voltage selecting circuit
Input voltage of the magnitude of voltage as band gap comparison circuit, prevents the arteries and veins of supply voltage by compared with the magnitude of voltage of protection circuit
Punching causes operation, while after band gap comparison circuit produces a under-voltage protecting circuit UVLO signals, being returned by feedback control loop
Return UVLO signals to monitor the low and high level of UVLO signals, with the security for protecting subsequent module to start, so pass through band gap ratio
The function of band-gap reference circuit and comparator compared with circuit realiration, is optimizing circuit structure, is reducing circuit area, reduces power consumption
While, also speed up the response speed of circuit.Realize that to PoE interfaces and fixed DC voltage conversion be variable direct current
The dc chopper DC/DC controller power source voltages of pressure are monitored, while in order to realize high conversion efficiency and obtain with input
The upset threshold voltage of the equal very little of the change of voltage and temperature.
Description of the drawings
General under-voltage protecting circuit figures of the Fig. 1 for prior art；
Electric current Is of the Fig. 2 for the embodiment of the present inventionC1, electric current IC2With input voltage VDGraph of a relation；
Schematic block diagrams of the Fig. 3 for the under-voltage protecting circuit of the embodiment of the present invention；
Circuit diagrams of the Fig. 4 for the under-voltage protecting circuit of the embodiment of the present invention.
Description of reference numerals：
1- resistor voltage divider circuits, 2- voltage selecting circuits, 3- band gap comparison circuits, 31- band-gap reference structures, 32- logics
Circuit, 4- biasing circuits.
Specific embodiment
To make the technical problem to be solved in the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing and tool
Body embodiment is described in detail.
The present invention uses independent reference voltage source and comparator for traditional under-voltage circuit in prior art, causes response
Time is longer, the problem that area occupied is larger and power consumption is big, there is provided a kind of under-voltage protecting circuit for POE, leads to
Cross and 3 circuit of band gap comparison circuit is made with by comparator and reference voltage source, have under-voltage protecting circuit faster
Reversal rate, and power consumption is very low, and the presence by protection circuit, it is therefore prevented that supply voltage VDDPulse causes maloperation.
It should be noted that the V of the present inventionDDFor chip external power supply pin, VDDProduce through internal low-voltage source generating circuit
Raw internal power source voltage VCC。
As shown in Figures 2 to 4, the under-voltage protecting circuit for POE provided in an embodiment of the present invention, wherein, bag
Include：
For adjusting the resistor voltage divider circuit 1 of upset threshold voltage, and produce the first output voltage and the second output voltage；
Voltage selecting circuit 2, is connected with the resistor voltage divider circuit 1, from first output voltage and described second defeated
Go out voltage and select a magnitude of voltage；
Band gap comparison circuit 3, is connected with the voltage selecting circuit 2, for the institute for selecting the voltage selecting circuit 2
State magnitude of voltage or the pulse for preventing supply voltage causes the magnitude of voltage of the protection circuit of operation used as input voltage, produce one
Under-voltage protecting circuit UVLO signals；
The feedback control circuit being arranged between the resistor voltage divider circuit 1 and the band gap comparison circuit 3, in institute
State UVLO signal outputs for high level when, the UVLO signals export higher described first through the voltage selecting circuit 2
Output voltage, when the UVLO signal outputs are low level, exports relatively low second output voltage.
The voltage selecting circuit 2 selects the magnitude of voltage of resistor voltage divider circuit 1 or selection to prevent the pulse of supply voltage
Cause the magnitude of voltage of protection circuit of operation as the input voltage of band gap comparison circuit 3, produce under-voltage protecting circuit UVLO letters
After number, UVLO signals are returned to by voltage selecting circuit 2 by feedback control loop, then voltage selecting circuit 2 can be selected
The first higher output voltage of magnitude of voltage exports the second relatively low output voltage as the input of band gap comparison circuit 3, and
When the output under-voltage protecting circuit UVLO signals of band gap comparison circuit 3 are low level, chip internal basic module does not start, and rises
To the purpose of under-voltage protection；When the output under-voltage protecting circuit UVLO signals of band gap comparison circuit 3 are high level, chip is opened
Dynamic, internal basic module starts.So comparator is combined with reference voltage source, the band gap comparison circuit 3 of composition, circuit knot
Structure substantially simplifies, and reduces area, reduces cost；It is adjustable and temperature drift is little through under-voltage protecting circuit upset threshold voltage again；
When supply voltage occurs under-voltage, reference voltage is not produced, a large amount of stand-by power consumptions are saved.
In order to power to band gap comparison circuit 3, therefore the under-voltage protection electricity for POE of the embodiment of the present invention
Lu Zhong, also includes：
Biasing circuit 4, wherein the biasing circuit 4 includes：First biasing circuit and comparison voltage produce circuit；
Wherein described first biasing circuit includes：30th PMOS transistor M0, the second PMOS transistor M2, the 3rd PMOS
Transistor M3, the first PMOS transistor (M1) and the 4th electric capacity C4, wherein the 30th PMOS transistor M0 grounded-grid, institute
The source electrode and substrate for stating the 30th PMOS transistor M0 is connected to internal power source voltage VCC, the 30th PMOS transistor M0
Drain electrode is connected with the drain electrode of second PMOS transistor M2, and the drain electrode of second PMOS transistor M2 is connected to described second
On the grid of PMOS transistor M2；The grounded-grid of wherein described 30th PMOS transistor M0, source electrode and substrate are connected to electricity
Source voltage VCC, then the 30th PMOS transistor M0 is in normal open state；
The source electrode and Substrate ground of second PMOS transistor M2；
The source electrode and Substrate ground of the 3rd PMOS transistor M3；
The grid of the 3rd PMOS transistor M3 is grounded by the 4th electric capacity C4, the grid of second PMOS transistor M2
The grid M3 of pole and the 3rd PMOS transistor is that the band gap comparison circuit 3 provides the first bias current inp1；
The grid of second PMOS transistor M2 is connected with the grid of first PMOS transistor M1 by diode,
The drain electrode of first PMOS transistor M1 is connected with the drain electrode of the 3rd PMOS transistor M3, first PMOS transistor
The source electrode and substrate of M1 is connected to the internal power source voltage VCC, the grid offer described first of first PMOS transistor M1
Bias current inp1；
Wherein described comparison voltage produces circuit to be included：6th PMOS transistor M6, the 7th PMOS transistor M7, the 8th
PMOS transistor M8, the 9th PMOS transistor M9 and the first electric capacity C1, a PMOS crystal of first biasing circuit
Pipe M1 and the 6th PMOS transistor M6 form mirror current source, and it is described that the grid of first PMOS transistor M1 is provided
Grids of the first bias current inp1 to the 6th PMOS transistor M6；
The source electrode and substrate of the 6th PMOS transistor M6 is connected to the internal power source voltage VCC, the 7th PMOS
The source electrode and substrate of transistor M7 is connected to the internal power source voltage VCC, the grid of the 7th PMOS transistor (M7) and institute
State the grid connection of the 15th PMOS transistor (M15) of band gap comparison circuit 3, the 15th PMOS transistor M15 grid
Produce self-bias voltage Vbias, the drain electrode of the 7th PMOS transistor M7 and the drain electrode of the 6th PMOS transistor M6 connect
Connect, the drain electrode of the 7th PMOS transistor M7 is connected with the source electrode of the 8th PMOS transistor M8, the 8th PMOS is brilliant
The substrate of body pipe M8 is connected to the source electrode of the 8th PMOS transistor M8, and the drain electrode output of the 6th PMOS transistor M6
Second bias voltage Vbias2；
The drain electrode M8 of the 8th PMOS transistor and the grid short circuit of the 8th PMOS transistor M8, the described 8th
The drain electrode M8 of PMOS is connected to the source electrode of the 9th PMOS M9, and the substrate of the 9th PMOS M9 is connected to described
The source electrode of nine PMOSs M9；
The drain electrode of the grid and the 9th PMOS M9 of the 9th PMOS M9 is grounded by the first electric capacity C1.
It is above-mentioned after electricity on chip, the 6th PMOS transistor M6 mirror current source quickly gives the first electric capacity C1 chargings, works as band
Gap comparison circuit 3 starts, the conducting of the 7th PMOS transistor M7, after increasing to the electric current that the first electric capacity C1 charges, the second biased electrical
Pressure Vbias2More quickly charge.If supply voltage VDDWhat is risen is slow, then the second bias voltage Vbias2Voltage on
, the V faster than output voltage Vin of literDMain to be controlled by output voltage Vin, i.e. upset point is controlled by output voltage Vin；But work as
Supply voltage VDDProduce a pulse, supply voltage VDDRapidly rise, ratio the second bias voltage V that output voltage Vin risesbias2
Hurry up, then now, VDVoltage by the second bias voltage Vbias2Determine, when it rises to certain fixed value, make band gap more electric
Road 3 overturns, and trailing edge is also thus, therefore preventing supply voltage VDDCause maloperation because of pulse.
For the supply voltage V that samplesDD, therefore in the under-voltage protecting circuit for POE of the embodiment of the present invention,
The resistor voltage divider circuit 1 includes：3rd resistor R3, the 4th resistance R4 and the 5th resistance R5, wherein 3rd resistor R3 mono-
End is connected to the supply voltage VDD, and the 3rd resistor R3 other end is series at one end of the 4th resistance R4, it is described
The first output voltage V1 is formed between 3rd resistor R3 and the 4th resistance R4, the first output voltage V1 is used as institute
State the input voltage of voltage selecting circuit 2；
Described 5th resistance R5 one end is series at the other end of the 4th resistance R4, and the 5th resistance R5's is another
End ground connection, forms the second output voltage V2, first output between the 4th resistance R4 and the 5th resistance R5
Input voltages of the voltage V2 as the voltage selecting circuit 2.
Can also be adjusted by the divider resistance of regulation resistor voltage divider circuit 1 and spin upside down threshold voltage, band gap is more electric
Output signal U VLO on road 3 returns to voltage selecting circuit 2 again；When UVLO signals overturn, voltage selecting circuit 2 is also turned over therewith
Turn, from divider resistance, the signal Vin of output also changes therewith, this signal be both the input signal of UVLO circuits, or
VDDThe Vin of the partial pressure of signal, thus overturn threshold voltage change therewith.
In the under-voltage protecting circuit for POE of another embodiment of the present invention, the voltage selecting circuit 2
Including：4th PMOS transistor M4, the 5th PMOS transistor M5 and the first phase inverter INV1,
The grid of wherein described 5th PMOS transistor M5 is connected to the input of the first phase inverter INV1；
The grid of the 4th PMOS transistor M4 is connected to the output end of the first phase inverter INV1；
The drain electrode of the 4th PMOS transistor M4 is connected with the second output voltage V2 of the resistor voltage divider circuit 1
Connect；
The drain electrode of the 5th PMOS transistor M5 is connected with the first output voltage V1 of the resistor voltage divider circuit 1
Connect；
The source electrode of the 5th PMOS transistor M5 is connected to the source electrode of the 4th PMOS transistor M4, and the 5th PMOS
The substrate of transistor M5 is cascaded with the substrate of the 4th PMOS transistor M4, and the substrate of the 5th PMOS transistor M5 connects
It is connected to the source electrode of the 5th PMOS transistor M5, and the source electrode of the 5th PMOS transistor M5 and the band gap comparison circuit
The grid connection of 3 the 12nd PMOS transistor M12, exports the voltage by the source electrode of the 5th PMOS transistor M5 and selects
The output voltage (Vin) of circuit, the output voltage (Vin) provide input voltage as the band gap comparison circuit 3.
In order to prevent the supply voltage VDDPulse cause operation, therefore the embodiment of the present invention for POE
Under-voltage protecting circuit in, it is described to prevent the supply voltage VDDPulse cause the protection circuit of operation to include：With the band
13rd PMOS transistor M13 of the 12nd PMOS transistor M12 parallel connection of gap comparison circuit 3, the 11st PMOS crystal
Pipe (M11) and the tenth PMOS transistor (M10),
Wherein described 11st PMOS transistor (M11) and the tenth PMOS transistor (M10) are connected in parallel in described
Portion supply voltage (VCC) and the source electrode of the 13rd PMOS transistor (M13) between, wherein the 11st PMOS transistor
(M11) source electrode and substrate is connected to the internal power source voltage (VCC), the drain electrode of the 11st PMOS transistor (M11) with
The source electrode connection of the 13rd PMOS transistor (M13), the drain electrode and the described tenth of the 11st PMOS transistor (M11)
The source electrode of three PMOS transistors (M13), the grid of the 11st PMOS transistor (M11) and the of first biasing circuit
The grid connection of one PMOS transistor (M1), the 11st PMOS transistor (M11) produce the 4th mirror current source branch road
4th image current (IC4)；
The source electrode and substrate of the tenth PMOS transistor (M10) is connected to the internal power source voltage (VCC), described
The drain electrode of ten PMOS transistors (M10) is connected to the source electrode of the 13rd PMOS transistor (M13), the tenth PMOS crystal
The drain electrode of pipe (M10) produces the 5th image current (I of the 5th image current branch roadC5)；Wherein described tenth PMOS transistor M10
3 level reversal rate of band gap comparison circuit when supply voltage reaches rising threshold value voltage is accelerated, the response of comparator is reduced
Time, the bias current that the 11st PMOS transistor M11 is provided are the 4th image current IC4。
The 13rd PMOS transistor M13 drain electrode and the 12nd PMOS transistor M12 drain electrode earth, it is described
The grid of the 13rd PMOS transistor M13 accesses the second bias voltage Vbias2With the grid of the 12nd PMOS transistor M12
The input voltage of access is made comparisons, and the sources connected in parallel of the 13rd PMOS transistor M13 is in the 12nd PMOS transistor
The source electrode of M12, the substrate of the 13rd PMOS transistor M13 are connected to the source electrode of the 13rd PMOS transistor M13, institute
The substrate for stating the 12nd PMOS transistor M12 is connected to the source electrode of the 12nd PMOS transistor M12, second biased electrical
Pressure Vbias2After comparing with the input voltage by the 12nd PMOS transistor M12 source output voltage.
The output of resistor voltage divider circuit 1 is not directly inputted to band gap comparison circuit 3 by the present invention, but is first input into the
12 PMOS transistors M12, as the 12nd PMOS transistor M12 is source follower, the level of lifting input signal, D points
Voltage VDWith supply voltage VDDIncrease and increase, so because input voltage be first input into the 12nd PMOS M12, by
The principle of source class follower, VD=Vin+VGS12, illustrate input voltage after M12, boosting, therefore by UVLO circuits
Upset point premise, that is, reduce cut-in voltage VUVLO_RValue, make supply voltage VDDIt is after upper electricity, quick to start.
13rd PMOS M13 prevents supply voltage V by the comparison with input voltageDDPulse causes maloperation.
As reference voltage source and comparator are combined to form 3 circuit of band gap comparison circuit by the present invention, therefore the present invention is real
Apply in the under-voltage protecting circuit for POE of example, the band gap comparison circuit 3 includes：Produce the band gap of reference voltage
Benchmark architecture 31, the load circuit of current source branch current, second level output circuit, startup clamp circuit and logic circuit
32。
Wherein the logic circuit 32 includes Schmidt trigger SMT and the second phase inverter INV2, wherein, the Shi Misi
The 19th PMOS crystal of the input of trigger SMT and the second level output circuit of the band gap comparison circuit 3
The output end connection of the drain electrode of pipe M19, exports the UVLO signals of the under-voltage protecting circuit after the second phase inverter INV2 described in,
And the second phase inverter INV2 is connected with the first phase inverter INV1, the UVLO signals are fed back to into described first anti-phase
The input of device INV1.
Wherein the band-gap reference structure 31 includes：14th PMOS transistor M14, the 17th PMOS transistor M17,
One triode Q1, the second triode Q2, first resistor R1 and second resistance R2,
Wherein, the source electrode and substrate of the 14th PMOS transistor M14 is connected to the internal power source voltage VCC；
The drain electrode of the 14th PMOS transistor M14 is connected to the source electrode of the 17th PMOS transistor M17, described
The substrate of the 17th PMOS transistor M17 is connected to the source electrode of the 17th PMOS transistor M17；
The grid of the 14th PMOS transistor M14 and first PMOS transistor M1 of first biasing circuit
Grid connection, and produce the 3rd mirror current source branch road the 3rd image current IC3；
The base stage of the second triode Q2 is connected with the source electrode of the 13rd PMOS transistor M13, second triode
The base stage of Q2 is connected as comparison voltage input with the base stage of the first triode Q1；
The colelctor electrode of the second triode Q2 is connected with the drain electrode of the 15th PMOS transistor M15 of the load circuit
Connect, produce the second image current I of the second mirror current source branch roadC2；
The colelctor electrode of the first triode Q1 is connected with the drain electrode of the 16th PMOS transistor M16 of the load circuit
Connect, produce the first image current I of the first mirror current source branch roadC1；
Second resistance R2 described in the emitter stage Jing of the second triode Q2 is connected to the transmitting of the first triode Q1
Pole, the source electrode of the 17th PMOS transistor M17 of first resistor R1 connection described in the emitter stage Jing of the first triode Q1, the
The substrate of 17 PMOS transistors M17 is connected to the source electrode of the 17th PMOS transistor M17, the 17th PMOS transistor
The grid of M17 and drain electrode are grounded.
By the 14th PMOS transistor M14, the 17th PMOS transistor M17, the second triode Q2, the first triode
The core texture of Q1, second resistance R2 and first resistor R1 composition band gap comparison circuit 3, produces reference voltage, it is also possible to pass through
3 level reversal rate of band gap comparison circuit when the circuit of optimization has greatly accelerated that supply voltage reaches ascending threshold, while reducing
Response time of comparator.
As shown in Fig. 2 ic1、ic2With input voltage VDRelation.When circuit just goes up electricity, VDDVoltage slowly rises, at the beginning
VDVoltage overturns threshold voltage V less than band gap comparison circuit 3TH(IC1=IC2When VDValue), IC2More than IC1, therefore A point voltages ratio
B point voltages are high, UVLO signal output low levels；As signal VDFrom it is low gradually increase when, electric current ic1、ic2Increase, ic2Curve is oblique
Rate compares ic1The slope of curve is little, works as VDDRise to VUVLO_R, that is, work as VDReach the upset thresholding V of band-gap reference comparatorTHWhen, ic1=
ic2, A point voltages are equal with B point voltages, are now the critical conditions of upset；In the critical condition of upset, Δ VBE=VBE1-
VBE2=ic2R2=VTLn (4), VBE1、VBE2It is the first triode Q1, the emitter-base voltage of the second triode Q2 pipes respectively,
I is solved thenc2=VTLn (4)/R2, sets the electric current of M14 again as ic3, so in upset point, the electric current for flowing through C points is 2ic2+ic3, place
When point critical state is overturn, it is not have IC1、IC2Two-way electric current, now IC1=IC2, along with IC3Branch current.It is possible thereby to
Learn, the voltage of C points is：
Wherein, ic2=VTLn (4)/R2, ic3It is current mirror image current.
The base voltage of the first triode Q1 is exactly to overturn threshold voltage VTH, i.e.,
Wherein, ic2=VTLn (4)/R2, ic3It is current mirror image current.
Then the upset threshold voltage of band gap comparison circuit 3 is equal to VTH, in formula (2), ic3It is negative temperature coefficient, but
2ic2+ic3It is that Section 1 is V in positive temperature coefficient, and (2)BE1Negative temperature coefficient, three is positive temperature coefficient afterwards, therefore is passed through
Rational regulation can be obtained by the upset threshold voltage unrelated with temperature, supply voltage.
Work as VDDMore than VUVLO_R, UVLO signals upset output high level.Wherein ic2The slope of curve compares ic1The slope of curve is little
Reason is voltage VDThe first triode Q1, the base stage of the second triode Q2 are transported to, in band-gap reference structure 31, the one or three is taken
The emitter area ratio of pole pipe Q1 and the second triode Q2 is 1：4, then the mutual conductance relation of two transistors is：
4gm1=gm2 (1)
As the emitter feedback of first resistor R1 and second resistance R2 is acted on, so the first triode Q1 and the second triode
The equivalent transconductance of Q2 is：
By g in (2) formulam2Substituted into and arranged with (1) formula, obtained：
And
Gm1R2 ＞ ＞ 1 are typically chosen, then Gm1 ＞ Gm2.Then, as the supply voltage V of chipDDDuring fluctuation, the one or three pole
The collector current I of pipe Q1C1Relative to the collector current I of the second triode Q2C2Variable quantity is big.Therefore at the beginning, IC2Greatly
In IC1, and M15, M16 breadth length ratio is the same, therefore the pressure drop by M16 is greater than by the pressure drop of M15, therefore B point voltages are less than
A points.
Exactly because Gm1 ＞ Gm2, so the collector current I of the first triode Q1C1Relative to the collection of the second triode Q2
Electrode current IC2Variable quantity is big, therefore when their base stage input identical voltage, IC2Slope ratio IC1Slope it is little.
In the under-voltage protecting circuit for POE of another embodiment of the present invention, the current source branch road
The load circuit of electric current includes：
16th PMOS transistor (M16), the 15th PMOS transistor M15 and the second electric capacity C2；
Wherein described 16th PMOS transistor M16 forms mirror current source, institute with the 15th PMOS transistor M15
State the self-bias voltage V of the 15th PMOS transistor M15 grid generationbiasThe grid of the 16th PMOS transistor M16 is input to,
The source electrode and substrate of the 16th PMOS transistor M16 is connected to the internal power source voltage VCC；
The source electrode and substrate of the 15th PMOS transistor M15 is connected to the internal power source voltage VCC, the described tenth
The grid of five PMOS transistors M15 is connected to the drain electrode of the 15th PMOS transistor M15, the 15th PMOS transistor
The grid of the 7th PMOS transistor M7 that the grid of M15 produces circuit with the comparison voltage is connected；
15th PMOS transistor M15 and the tenth PMOS transistor M10 formation mirror current source, the described tenth
The self-bias voltage V that five PMOS transistor M15 grids are producedbiasIt is input to the grid of the tenth PMOS transistor M10.
As shown in figure 4, when band gap comparison circuit 3 starts, after the conducting of the 15th PMOS transistor M15 branch road, its automatic biasing
The voltage V of generationbiasThe grid of the tenth PMOS transistor M10 is input to, mirror is constituted, its image current source image gives the tenth
PMOS transistor M10, the tenth PMOS transistor M10 conducting, accelerates VDRising, accelerate again supply voltage reach on
When rising threshold value, 3 level reversal rate of band gap comparison circuit, accelerates the upset of this band gap comparison circuit 3, substantially reduces ratio
Compared with the response time of device.
In the under-voltage protecting circuit for POE of another embodiment of the present invention, the second level output circuit
Including：19th PMOS transistor M19, the 20th PMOS transistor M20, the 21st PMOS transistor M21 and the 29th
PMOS transistor M29, wherein the 15th PMOS transistor M15 forms mirror image with the 29th PMOS transistor M29
Current source, the source electrode and substrate of the 29th PMOS transistor M29 are connected to the internal power source voltage VCC, described second
The drain electrode of 19 PMOS transistors M29 is connected with the drain electrode of the 20th PMOS transistor M20, the 15th PMOS transistor
The self-bias voltage V that M15 grids are producedbiasThe grid of the 29th PMOS transistor M29 is input to, the 6th image current is produced
6th image current I of branch roadC6；
20th PMOS transistor M20 forms mirror current source with the 21st PMOS transistor M21, described
20th PMOS transistor M20 produces the 7th image current IC7, the grid and described second of the 20th PMOS transistor M20
The grid connection of 11 PMOS transistors M21, grid and the 20th PMOS crystal of the 20th PMOS transistor M20
The drain electrode connection of pipe M20, the source electrode and Substrate ground of the 20th PMOS transistor M20, the 21st PMOS crystal
The source electrode and Substrate ground of pipe M21, the 20th PMOS transistor M20 produce the 8th image current IC8；
The grid of the 19th PMOS transistor M19 is with the first triode Q1's of the band-gap reference structure 31
Colelctor electrode connects, and the source electrode and substrate of the 19th PMOS transistor M19 are connected to the internal power source voltage VCC, described
The drain electrode of 19 PMOS transistors M19 is connected with the drain electrode of the 21st PMOS transistor M21, produces second level output electricity
The output voltage on road.
In the under-voltage protecting circuit for POE of another embodiment of the present invention, the startup clamp circuit bag
Include：18th PMOS transistor M18, the 22nd PMOS transistor M22, the 23rd PMOS transistor M23, the 24th
PMOS transistor M24, the 25th PMOS transistor M25, the 26th PMOS transistor M26, the 27th PMOS transistor
M27, the 28th PMOS transistor M28, the 3rd electric capacity C3 and the 5th electric capacity C5,
The drain electrode of wherein described 18th PMOS transistor M18 and the 19th PMOS of the second level output circuit
The grid connection of transistor M19, the drain electrode of the 19th PMOS transistor M19 are parallel to a ground connection the 5th electric capacity C5；
The source electrode and substrate of the 18th PMOS transistor M18 is connected to the internal power source voltage VCC, the 18th PMOS is brilliant
The connection of the grid of body pipe M18 and the drain electrode of the 27th PMOS transistor M27；
The source electrode and substrate of the 22nd PMOS transistor M22 is connected to the internal power source voltage VCC, described
The grid connection of the first PMOS transistor M1 that the grid of 22 PMOS transistors M22 is connected with first biasing circuit,
The drain electrode of the 22nd PMOS transistor M22 is connected with the source electrode of the 25th PMOS transistor M25；
The substrate of the 25th PMOS transistor M25 is connected to the internal power source voltage VCC, the described 25th
The drain electrode of PMOS transistor M25 is connected with the drain electrode of the 26th PMOS transistor M26, the 25th PMOS crystal
The drain electrode of pipe M25 is connected with the grid of the 23rd PMOS transistor M23, the 25th PMOS transistor M25
Grid is connected with the grid of the 26th PMOS transistor M26, and the grid of the 26th PMOS transistor M26 leads to
Cross the 3rd electric capacity C3 ground connection；
The source electrode and Substrate ground of the 26th PMOS transistor M26；
The 19th PMOS that the drain electrode of the 23rd PMOS transistor M23 is parallel to the second level output is brilliant
The drain electrode of body pipe M19, the Substrate ground of the 23rd PMOS transistor M23, the 23rd PMOS transistor M23
Source electrode is connected with the drain electrode of the 24th PMOS transistor M24；
The source electrode and Substrate ground of the 24th PMOS transistor M24, the 24th PMOS transistor M24
Grid is connected with the grid of second PMOS transistor M2 of first biasing circuit；
The source electrode and substrate of the 27th PMOS transistor M27 is connected to the internal power source voltage VCC, described
The grid of the 7th PMOS transistor M7 that the grid of 27 PMOS transistors M27 produces circuit with the comparison voltage connects
Connect, the drain electrode of the 27th PMOS transistor M27 is connected with the 28th PMOS transistor M28 drain electrode, described the
The gate connected in parallel of 26 PMOS transistors M26 drains in the 28th PMOS transistor M28；
The source electrode and Substrate ground of the 28th PMOS transistor M28, the 28th PMOS transistor M28
Grid is connected with the grid of the second PMOS transistor M2 described in first biasing circuit.
When circuit just goes up electricity, the 24th PMOS transistor M24, the 28th PMOS is brilliant for the 28th PMOS transistor
Body pipe M28 is mirrored conducting, and the 27th PMOS transistor M27 is not turned on, then VF is low level, therefore the 18th PMOS is brilliant
Body pipe M18, the 23rd PMOS transistor M23, the conducting of the 25th PMOS transistor M25, force A point voltages for high level, E
The second level output voltage of point is low level, and its purpose is exactly to force output signal U VLO to be low level.
Branch pressure voltage output end V of resistor voltage divider circuit 1DIt is connected to the comparison voltage input of band gap comparison circuit 3, band
The defeated input to logic circuit 32 of output end of gap comparison circuit 3, exports under-voltage protection after the shaping of logic circuit 32
Output end UVLO of circuit；UVLO signals feed back to resistor voltage divider circuit 1 again, when band gap comparison circuit 3 exports high level, electricity
Resistance bleeder circuit 1 exports higher branch pressure voltage through the either-or switch of voltage selecting circuit 2.So as to realize to PoE interfaces
It is monitored with DC/DC controller power source voltages, while realizing high conversion efficiency and obtaining the change with input voltage and temperature
The upset threshold voltage of equal very little.Band gap comparison circuit 3 realizes the function of band-gap reference circuit and comparator, not only optimizes
Circuit structure and reduce circuit area, while reducing power consumption, also speeded up the response speed of circuit.
The above is the preferred embodiment of the present invention, it is noted that for those skilled in the art
For, on the premise of without departing from principle of the present invention, some improvements and modifications can also be made, these improvements and modifications
Should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of under-voltage protecting circuit for POE, it is characterised in that include：
For adjusting the resistor voltage divider circuit of upset threshold voltage, and produce the first output voltage and the second output voltage；
Voltage selecting circuit, is connected with the resistor voltage divider circuit, from first output voltage and second output voltage
Select a magnitude of voltage；
Band gap comparison circuit, is connected with the voltage selecting circuit, for the voltage for selecting the voltage selecting circuit
The pulse for preventing supply voltage is caused the magnitude of voltage of the protection circuit of operation as input voltage by value, produces a under-voltage guarantor
Protection circuit UVLO signals；
Biasing circuit, wherein the biasing circuit includes：First biasing circuit and comparison voltage produce circuit；
Wherein described first biasing circuit includes：30th PMOS transistor (M0), the second PMOS transistor (M2), the 3rd PMOS
Transistor (M3), the first PMOS transistor (M1) and the 4th electric capacity (C4),
Wherein described 30th PMOS transistor (M0) grounded-grid, the source electrode and substrate of the 30th PMOS transistor (M0)
It is connected to internal power source voltage (VCC), the drain electrode of the 30th PMOS transistor (M0) and second PMOS transistor (M2)
Drain electrode connection, the drain electrode of second PMOS transistor (M2) is connected on the grid of second PMOS transistor (M2)；
The source electrode and Substrate ground of second PMOS transistor (M2)；
The source electrode and Substrate ground of the 3rd PMOS transistor (M3)；
The grid of the 3rd PMOS transistor (M3) is grounded by the 4th electric capacity (C4), second PMOS transistor
(M2) grid and the grid of the 3rd PMOS transistor (M3) provides the first bias current for the band gap comparison circuit
(inp1)；
The grid of second PMOS transistor (M2) is connected with the grid of first PMOS transistor (M1) by diode,
The drain electrode of first PMOS transistor (M1) is connected with the drain electrode of the 3rd PMOS transistor (M3), and a PMOS is brilliant
The source electrode and substrate of body pipe (M1) is connected to the internal power source voltage (VCC), the grid of first PMOS transistor (M1) is carried
For first bias current (inp1)；
Wherein described comparison voltage produces circuit to be included：6th PMOS transistor (M6), the 7th PMOS transistor (M7), the 8th
PMOS transistor (M8), the 9th PMOS transistor (M9) and the first electric capacity (C1), described the first of first biasing circuit
PMOS transistor (M1) forms mirror current source with the 6th PMOS transistor (M6), first PMOS transistor (M1)
Grid of first bias current (inp1) that grid is provided to the 6th PMOS transistor (M6)；
The source electrode and substrate of the 6th PMOS transistor (M6) is connected to the internal power source voltage (VCC), the 7th PMOS
The source electrode and substrate of transistor (M7) is connected to the internal power source voltage (VCC), the grid of the 7th PMOS transistor (M7)
It is connected with the grid of the 15th PMOS transistor (M15) of the band gap comparison circuit, the 15th PMOS transistor M15 grid
Pole produces self-bias voltage Vbias), drain electrode and the 6th PMOS transistor (M6) of the 7th PMOS transistor (M7)
Drain electrode connection, the drain electrode of the 7th PMOS transistor (M7) is connected with the source electrode of the 8th PMOS transistor (M8), described
The substrate of the 8th PMOS transistor (M8) is connected to the source electrode of the 8th PMOS transistor (M8), and the 6th PMOS crystal
The drain electrode of pipe (M6) exports the second bias voltage (Vbias2)；
The drain electrode of the 8th PMOS transistor (M8) and the grid short circuit of the 8th PMOS transistor (M8), the described 8th
The drain electrode of PMOS (M8) is connected to the source electrode of the 9th PMOS (M9), and the substrate of the 9th PMOS (M9) is connected to
The source electrode of the 9th PMOS (M9)；
The grid of the 9th PMOS (M9) and the drain electrode of the 9th PMOS (M9) are grounded by the first electric capacity (C1)；
The feedback control loop being arranged between the resistor voltage divider circuit and the band gap comparison circuit, in the UVLO
When signal output is high level, the UVLO signals export higher the first output electricity through the voltage selecting circuit
Pressure, when the UVLO signal outputs are low level, exports relatively low second output voltage.
2. the under-voltage protecting circuit for POE according to claim 1, it is characterised in that the electric resistance partial pressure
Circuit includes：3rd resistor (R3), the 4th resistance (R4) and the 5th resistance (R5), wherein the connection of the 3rd resistor (R3) one end
In the supply voltage (VDD), and the 3rd resistor (R3) other end is series at one end of the 4th resistance (R4), it is described
First output voltage (V1), first output voltage are formed between 3rd resistor (R3) and the 4th resistance (R4)
(V1) as the input voltage of the voltage selecting circuit；
Described 5th resistance (R5) one end is series at the other end of the 4th resistance (R4), and the 5th resistance (R5) is another
One end is grounded, and second output voltage (V2) is formed between the 4th resistance (R4) and the 5th resistance (R5), described
Output voltage of second output voltage (V2) as the voltage selecting circuit.
3. the under-voltage protecting circuit for POE according to claim 2, it is characterised in that the voltage is selected
Circuit includes：4th PMOS transistor (M4), the 5th PMOS transistor (M5) and the first phase inverter (INV1),
The grid of wherein described 5th PMOS transistor (M5) is connected to the input of first phase inverter (INV1)；
The grid of the 4th PMOS transistor (M4) is connected to the output end of first phase inverter (INV1)；
The drain electrode of the 4th PMOS transistor (M4) is connected with second output voltage (V2) of the resistor voltage divider circuit；
The drain electrode of the 5th PMOS transistor (M5) is connected with first output voltage (V1) of the resistor voltage divider circuit；
The source electrode of the 5th PMOS transistor (M5) is connected to the source electrode of the 4th PMOS transistor (M4), and the 5th PMOS
The substrate of transistor (M5) is cascaded with the substrate of the 4th PMOS transistor (M4), the 5th PMOS transistor (M5)
Substrate is connected to the source electrode of the 5th PMOS transistor (M5), and the source electrode and the band of the 5th PMOS transistor (M5)
The grid connection of the 12nd PMOS transistor (M12) of gap comparison circuit, the source electrode by the 5th PMOS transistor (M5) are defeated
Go out the output voltage (Vin) of the voltage selecting circuit, the output voltage (Vin) provides defeated as the band gap comparison circuit
Enter voltage.
4. the under-voltage protecting circuit for POE according to claim 3, it is characterised in that described to prevent described
Supply voltage (VDD) pulse cause the protection circuit of operation to include：It is brilliant with the 12nd PMOS of the band gap comparison circuit
Body pipe (M12) the 13rd PMOS transistor (M13) in parallel, the 11st PMOS transistor (M11) and the tenth PMOS transistor
(M10),
Wherein described 11st PMOS transistor (M11) and the tenth PMOS transistor (M10) are connected in parallel on the internal electricity
Source voltage (VCC) and the source electrode of the 13rd PMOS transistor (M13) between, wherein the 11st PMOS transistor (M11)
Source electrode and substrate be connected to the internal power source voltage (VCC), the drain electrode of the 11st PMOS transistor (M11) with it is described
The source electrode connection of the 13rd PMOS transistor (M13), the drain electrode and the described 13rd of the 11st PMOS transistor (M11)
The source electrode of PMOS transistor (M13), the grid of the 11st PMOS transistor (M11) and the first of first biasing circuit
The grid connection of PMOS transistor (M1), the 11st PMOS transistor (M11) produce the of the 4th mirror current source branch road
Four image current (IC4)；
The source electrode and substrate of the tenth PMOS transistor (M10) is connected to the internal power source voltage (VCC), the described tenth
The drain electrode of PMOS transistor (M10) is connected to the source electrode of the 13rd PMOS transistor (M13), the tenth PMOS transistor
(M10) drain electrode produces the 5th image current (I of the 5th image current branch roadC5)；
13rd PMOS transistor (M13) drain electrode and the 12nd PMOS transistor (M12) drain electrode earth, it is described
The grid of the 13rd PMOS transistor (M13) accesses the second bias voltage (Vbias2) with the 12nd PMOS transistor (M12)
The input voltage that accesses of grid make comparisons, the sources connected in parallel of the 13rd PMOS transistor (M13) is in the described 12nd
The source electrode of PMOS transistor (M12), the substrate of the 13rd PMOS transistor (M13) are connected to the 13rd PMOS crystal
The source electrode of pipe (M13), the substrate of the 12nd PMOS transistor (M12) are connected to the 12nd PMOS transistor (M12)
Source electrode, the second bias voltage (Vbias2) compare with the input voltage after by the 12nd PMOS transistor (M12)
Source output voltage.
5. the under-voltage protecting circuit for POE according to claim 4, it is characterised in that the band gap compares
Circuit includes：The band-gap reference structure of generation reference voltage, the load circuit of current source branch current, second level output electricity
Road, startup clamp circuit and logic circuit.
6. the under-voltage protecting circuit for POE according to claim 5, it is characterised in that the logic circuit
Including Schmidt trigger (SMT) and the second phase inverter (INV2),
Wherein, the second level output circuit of the input of the Schmidt trigger (SMT) and the band gap comparison circuit
The 19th PMOS transistor (M19) drain electrode output end connection, export after the second phase inverter (INV2) described in it is described owe
The UVLO signals of voltage protection circuit, and second phase inverter (INV2) is connected with first phase inverter (INV1), will be described
UVLO signals feed back to the input of first phase inverter (INV1).
7. the under-voltage protecting circuit for POE according to claim 6, it is characterised in that the band-gap reference
Structure includes：14th PMOS transistor (M14), the 17th PMOS transistor (M17), the first triode (Q1), the two or three pole
Pipe (Q2), first resistor (R1) and second resistance (R2),
Wherein, the source electrode and substrate of the 14th PMOS transistor (M14) is connected to the internal power source voltage (VCC)；
The drain electrode of the 14th PMOS transistor (M14) is connected to the source electrode of the 17th PMOS transistor (M17), described
The substrate of the 17th PMOS transistor (M17) is connected to the source electrode of the 17th PMOS transistor (M17)；
First PMOS transistor (M1) of the grid of the 14th PMOS transistor (M14) and first biasing circuit
Grid connection, and produce the 3rd mirror current source branch road the 3rd image current (IC3)；
The base stage of second triode (Q2) is connected with the source electrode of the 13rd PMOS transistor (M13), second triode
(Q2) base stage is connected as comparison voltage input with the base stage of first triode (Q1)；
The colelctor electrode of second triode (Q2) is connected with the drain electrode of the 15th PMOS transistor (M15) of the load circuit
Connect, produce the second image current (I of the second mirror current source branch roadC2)；
The colelctor electrode of first triode (Q1) is connected with the drain electrode of the 16th PMOS transistor (M16) of the load circuit
Connect, produce the first image current (I of the first mirror current source branch roadC1)；
Second resistance (R2) described in the emitter stage Jing of second triode (Q2) is connected to sending out for first triode (Q1)
Emitter-base bandgap grading, the 17th PMOS transistor (M17) that first resistor (R1) described in the emitter stage Jing of first triode (Q1) connects
Source electrode, the substrate of the 17th PMOS transistor (M17) is connected to the source electrode of the 17th PMOS transistor (M17), the tenth
The grid of seven PMOS transistors (M17) and drain electrode are grounded.
8. the under-voltage protecting circuit for POE according to claim 7, it is characterised in that the generation electric current
The load circuit of source branch current includes：
16th PMOS transistor (M16), the 15th PMOS transistor (M15) and the second electric capacity (C2)；
Wherein described 16th PMOS transistor (M16) forms mirror current source, institute with the 15th PMOS transistor (M15)
State the self-bias voltage V of the 15th PMOS transistor (M15) grid generationbiasIt is input to the 16th PMOS transistor (M16)
Grid, the source electrode and substrate of the 16th PMOS transistor (M16) are connected to the internal power source voltage (VCC)；
The source electrode and substrate of the 15th PMOS transistor (M15) is connected to the internal power source voltage (VCC), the described tenth
The grid of five PMOS transistors (M15) is connected to the drain electrode of the 15th PMOS transistor (M15), and the 15th PMOS is brilliant
The grid of the 7th PMOS transistor (M7) that the grid of body pipe (M15) produces circuit with the comparison voltage is connected；
15th PMOS transistor (M15) and the tenth PMOS transistor (M10) formation mirror current source, the described tenth
The self-bias voltage V that five PMOS transistor M15 grids are producedbiasIt is input to the grid of the tenth PMOS transistor (M10).
9. the under-voltage protecting circuit for POE according to claim 8, it is characterised in that the second level is defeated
Going out circuit includes：19th PMOS transistor (M19), the 20th PMOS transistor (M20), the 21st PMOS transistor
And the 29th PMOS transistor (M29), (M21) wherein the 15th PMOS transistor (M15) and the described 29th
PMOS transistor (M29) forms mirror current source, and the source electrode and substrate of the 29th PMOS transistor (M29) are connected to institute
State internal power source voltage (VCC), drain electrode and the 20th PMOS transistor of the 29th PMOS transistor (M29)
(M20) drain electrode connection, the self-bias voltage V that the 15th PMOS transistor M15 grid is producedbiasIt is input to the 29th
The grid of PMOS transistor M29, produces the 6th image current (I of the 6th image current branch roadC6)；
20th PMOS transistor (M20) forms mirror current source with the 21st PMOS transistor (M21), described
20th PMOS transistor (M20) produces the 7th image current (IC7), the grid of the 20th PMOS transistor (M20) and institute
State the grid connection of the 21st PMOS transistor (M21), the grid and described second of the 20th PMOS transistor (M20)
The drain electrode connection of ten PMOS transistors (M20), the source electrode and Substrate ground of the 20th PMOS transistor (M20), described the
The source electrode and Substrate ground of 21 PMOS transistors (M21), the 20th PMOS transistor (M20) produce the 8th mirror image electricity
Stream (IC8)；
The collection of the grid of the 19th PMOS transistor (M19) and first triode (Q1) of the band-gap reference structure
Electrode connects, and the source electrode and substrate of the 19th PMOS transistor (M19) are connected to the internal power source voltage (VCC), it is described
The drain electrode of the 19th PMOS transistor (M19) is connected with the drain electrode of the 21st PMOS transistor (M21), produces the second level
The output voltage of output circuit.
10. the under-voltage protecting circuit for POE according to claim 9, it is characterised in that the startup pincers
Position circuit includes：18th PMOS transistor (M18), the 22nd PMOS transistor (M22), the 23rd PMOS transistor
(M23), the 24th PMOS transistor (M24), the 25th PMOS transistor (M25), the 26th PMOS transistor
(M26), the 27th PMOS transistor (M27), the 28th PMOS transistor (M28), the 3rd electric capacity (C3) and the 5th electric capacity
(C5),
The drain electrode of wherein described 18th PMOS transistor (M18) is brilliant with the 19th PMOS of the second level output circuit
The grid connection of body pipe (M19), the drain electrode of the 19th PMOS transistor (M19) are parallel to a ground connection the 5th electric capacity
(C5)；The source electrode and substrate of the 18th PMOS transistor (M18) is connected to the internal power source voltage (VCC), the described tenth
The connection of the grid of eight PMOS transistors (M18) and the drain electrode of the 27th PMOS transistor (M27)；
The source electrode and substrate of the 22nd PMOS transistor (M22) is connected to the internal power source voltage (VCC), described
The grid of the first PMOS transistor (M1) that the grid of 22 PMOS transistors (M22) is connected with first biasing circuit connects
Connect, the drain electrode of the 22nd PMOS transistor (M22) is connected with the source electrode of the 25th PMOS transistor (M25)；
The substrate of the 25th PMOS transistor (M25) is connected to the internal power source voltage (VCC), the described 25th
The drain electrode of PMOS transistor (M25) is connected with the drain electrode of the 26th PMOS transistor (M26), the 25th PMOS
The drain electrode of transistor (M25) is connected with the grid of the 23rd PMOS transistor (M23), the 25th PMOS crystal
The grid of pipe (M25) is connected with the grid of the 26th PMOS transistor (M26), and the 26th PMOS transistor
(M26) grid is grounded by the 3rd electric capacity (C3)；
The source electrode and Substrate ground of the 26th PMOS transistor (M26)；
The drain electrode of the 23rd PMOS transistor (M23) is parallel to the 19th PMOS crystal of the second level output
The drain electrode of pipe (M19), the Substrate ground of the 23rd PMOS transistor (M23), the 23rd PMOS transistor
(M23) source electrode is connected with the drain electrode of the 24th PMOS transistor (M24)；
The source electrode and Substrate ground of the 24th PMOS transistor (M24), the 24th PMOS transistor (M24)
Grid is connected with the grid of second PMOS transistor (M2) of first biasing circuit；
The source electrode and substrate of the 27th PMOS transistor (M27) is connected to the internal power source voltage (VCC), described
The grid of 27 PMOS transistors (M27) produces the grid of the 7th PMOS transistor (M7) of circuit with the comparison voltage
Pole connects, and drain electrode and the 28th PMOS transistor (M28) drain electrode of the 27th PMOS transistor (M27) connect
Connect, the gate connected in parallel of the 26th PMOS transistor (M26) drains in the 28th PMOS transistor (M28)；
The source electrode and Substrate ground of the 28th PMOS transistor (M28), the 28th PMOS transistor (M28)
Grid is connected with the grid of the first PMOS transistor (M1) described in first biasing circuit.
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| CN109617559A (en) * | 2018-12-25 | 2019-04-12 | 成都前锋电子仪器有限责任公司 | A kind of high-precision blind landing ILS signal source |
| CN111446949B (en) * | 2019-01-16 | 2024-03-01 | 中芯国际集成电路制造(上海)有限公司 | Power-on reset circuit and integrated circuit |
| CN110048368B (en) * | 2019-04-29 | 2021-01-29 | 中国电子科技集团公司第五十八研究所 | High-speed high-precision undervoltage protection circuit |
| CN111711172B (en) * | 2020-06-22 | 2021-03-30 | 电子科技大学 | Undervoltage protection circuit with ultralow power consumption |
| CN112649657B (en) * | 2020-11-25 | 2021-10-29 | 西南大学 | Undervoltage indicating system |
| CN113206494B (en) * | 2021-03-19 | 2023-04-28 | 成都市菱奇半导体有限公司 | Input voltage detection circuit and charger |
| CN113783160B (en) * | 2021-11-11 | 2022-04-01 | 浙江大学 | Undervoltage protection circuit and power module |
| CN116093887B (en) * | 2023-02-09 | 2023-07-25 | 北京伽略电子股份有限公司 | Over-temperature protection circuit |
| CN117118410B (en) * | 2023-10-25 | 2024-02-02 | 无锡众享科技有限公司 | Comparator, detection circuit, grading circuit and POE power supply system |
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| CN101958640A (en) * | 2010-10-15 | 2011-01-26 | 苏州大学 | Undervoltage latch circuit with band gap reference structure |
| CN102662518A (en) * | 2012-03-31 | 2012-09-12 | 华映光电股份有限公司 | System and method for controlling signal noise ratio |
| CN102710011A (en) * | 2012-06-14 | 2012-10-03 | 济南镭之源电气有限公司 | Power over Ethernet (POE) device capable of supplying power uninterruptedly |
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| JP4886588B2 (en) * | 2007-05-10 | 2012-02-29 | ルネサスエレクトロニクス株式会社 | Voltage sensor module and voltage monitoring device |
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| CN101958640A (en) * | 2010-10-15 | 2011-01-26 | 苏州大学 | Undervoltage latch circuit with band gap reference structure |
| CN102662518A (en) * | 2012-03-31 | 2012-09-12 | 华映光电股份有限公司 | System and method for controlling signal noise ratio |
| CN102710011A (en) * | 2012-06-14 | 2012-10-03 | 济南镭之源电气有限公司 | Power over Ethernet (POE) device capable of supplying power uninterruptedly |
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Address after: Room 01, 4 / F, building B, Xi'an Tengfei innovation center, No. 38, Gaoxin 6th Road, high tech Zone, Xi'an, Shaanxi 710075 Patentee after: Xi'an Xinhui Photoelectric Technology Co.,Ltd. Address before: 315000 10th floor, Gaoqiao chamber of Commerce building, 388 Huixian Road, Gaoqiao Town, Haishu District, Ningbo City, Zhejiang Province Patentee before: Ningbo Xinhui Technology Co.,Ltd. |
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