CN116093887B - Over-temperature protection circuit - Google Patents
Over-temperature protection circuit Download PDFInfo
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- CN116093887B CN116093887B CN202310085351.6A CN202310085351A CN116093887B CN 116093887 B CN116093887 B CN 116093887B CN 202310085351 A CN202310085351 A CN 202310085351A CN 116093887 B CN116093887 B CN 116093887B
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- 230000005540 biological transmission Effects 0.000 claims abstract description 15
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- 101150110298 INV1 gene Proteins 0.000 claims abstract description 10
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims abstract description 4
- 101150070189 CIN3 gene Proteins 0.000 claims description 9
- 101100286980 Daucus carota INV2 gene Proteins 0.000 claims description 9
- 101100508840 Daucus carota INV3 gene Proteins 0.000 claims description 9
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 108010053481 Antifreeze Proteins Proteins 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
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- 230000010355 oscillation Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H5/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection
- H02H5/04—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature
- H02H5/044—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature using a semiconductor device to sense the temperature
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Abstract
The application discloses excess temperature protection circuit includes: the voltage dividing circuit is used for setting a voltage dividing resistor between the reference voltage and the ground and connecting to the transmission gate based on the voltage dividing resistor; the transmission gate comprises a first NMOS tube N1, a first PMOS tube P1 and a first inverter INV1, wherein: the bias circuit is used for providing bias current for the comparator circuit based on a plurality of groups of PMOS tubes; the comparator circuit comprises a first NPN tube Q1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4 and a second NPN tube Q2, wherein the base electrode of the second NPN tube Q2 is connected with the collector electrode of the second NPN tube Q2 and the grid electrode of the fourth NMOS tube N4, the emitter electrode of the second NPN tube Q2 is grounded in series through a resistor R6 and a capacitor C1, and the emitter electrode of the second NPN tube Q2 is connected to the grid electrode of the second NMOS tube N2. The transmission gate and the comparator circuit have wide temperature hysteresis quantity and high-efficiency conversion rate, and when the power supply voltage changes, the circuit performance is stable.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly to an over-temperature protection circuit.
Background
In practical engineering, many parameters of the transistor are functions of temperature; when the temperature rises, the collector current of the bipolar transistor and the drain current of the MOSFET are obviously changed, and the dissipation power of the tube is increased; the resistance value of the resistor has temperature dependence, and the working state of the whole circuit tends to be unstable. When the temperature is too high, there is a high possibility that the secondary breakdown of the tube and the power consumption are excessive, resulting in the loss of the tube and even the whole chip. In addition, the temperature inside the chip may be increased rapidly under the conditions of large output load current, and the over-temperature protection circuit needs to be designed under the conditions that when the temperature is increased rapidly, the over-temperature protection circuit outputs a control signal to turn off part of the functions of the chip, and the chip is turned on after the temperature is reduced. Meanwhile, a thermal oscillation phenomenon of switching off and on reciprocally may occur near the over-temperature protection threshold point, and the over-temperature protection circuit is required to have a thermal hysteresis function.
The basic design idea of the over-temperature protection circuit is to monitor the temperature change of the chip by utilizing the temperature sensitive characteristics of the BJT and the MOS. Since BJTs have better temperature characteristics than MOS, most over-temperature protection circuits are designed around BJT devices.
Disclosure of Invention
The embodiment of the application provides an over-temperature protection circuit which is used for improving the response capability to a fast transient voltage and improving the conversion rate.
The embodiment of the application provides an over-temperature protection circuit, which comprises:
the voltage dividing circuit is used for setting a voltage dividing resistor between the reference voltage and the ground and connecting to the transmission gate based on the voltage dividing resistor;
the transmission gate comprises a first NMOS tube N1, a first PMOS tube P1 and a first inverter INV1, wherein:
the source electrode of the first NMOS tube N1 is connected with the source electrode of the first PMOS tube P1 and is connected to the first leading-out end of the voltage dividing circuit;
the drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS tube P1 and is connected to the second leading-out end of the voltage dividing circuit;
the grid electrode of the first NMOS tube N1 is connected to the input end of the first inverter INV1, and the output end of the first inverter INV1 is connected to the grid electrode of the first PMOS tube P1;
the bias circuit is used for providing bias current for the comparator circuit based on a plurality of groups of PMOS tubes;
the comparator circuit comprises a first NPN tube Q1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4 and a second NPN tube Q2, wherein:
the base electrode of the first NPN tube Q1 is connected with the drain electrode of the first NMOS tube N1, the emitter electrode is grounded, and the collector electrode is connected with bias current;
the source electrode of the second NMOS tube N2, the third NMOS tube N3 and the fourth NMOS tube N4 are grounded, and the drain electrode of the second NMOS tube is connected with bias current;
the grid electrode of the second NMOS tube N2 is connected with the collector electrode of the first NPN tube Q1;
the grid electrode of the third NMOS tube N3 is connected to the drain electrode of the second NMOS tube N2;
the grid electrode of the fourth NMOS tube N4 is connected to the drain electrode of the third NMOS tube N3;
and the base electrode of the second NPN tube Q2 is connected with the collector electrode of the second NPN tube Q and the grid electrode of the fourth NMOS tube N4, the emitter electrode of the second NPN tube Q is grounded through the series connection of a resistor R6 and a capacitor C1, and the emitter electrode of the second NPN tube Q is connected to the grid electrode of the second NMOS tube N2.
Optionally, the bias circuit includes fourth to thirteenth PMOS transistors P4 to P13, wherein:
the sources of the fourth PMOS tube P4 to the eighth PMOS tube P8 are connected with VDD;
the grid electrode and the drain electrode of the fourth PMOS tube P4 are in short circuit;
the gates of the fifth PMOS transistor P5 to the eighth PMOS transistor P8 are all connected to the gate of the fourth PMOS transistor P4;
the drain electrode of the fourth PMOS tube P4 is connected with the source electrode of the thirteenth PMOS tube P13, and the drain electrode of the fifth PMOS tube P5 is connected with the source electrode of the twelfth PMOS tube P12;
the drain electrode of the sixth PMOS tube P6 is connected with the source electrode of the eleventh PMOS tube P11;
the drain electrode of the seventh PMOS tube P7 is connected with the source electrode of the tenth PMOS tube P10;
the drain electrode of the eighth PMOS tube P8 is connected with the source electrode of the ninth PMOS tube P9;
the grid electrode and the drain electrode of the thirteenth PMOS tube P13 are short-circuited;
the gates of the ninth to twelfth PMOS tubes P9 to P12 are connected to the gate of the thirteenth PMOS tube P13.
Optionally, the system further comprises a second PMOS tube P2 and a third PMOS tube P3;
the grid electrode of the second PMOS tube P2 is connected with a signal end, the drain electrode of the second PMOS tube P2 is connected to the drain electrode of the first NMOS tube N1, and the source electrode of the second PMOS tube P3 is connected to the drain electrode of the third PMOS tube P3;
and the grid electrode of the third PMOS tube P3 is connected to the drain electrode of the fourth PMOS tube P4, and the source electrode of the third PMOS tube P3 is connected to VDD.
Optionally, the circuit further comprises a fourth inverter INV4, wherein the output end of the fourth inverter INV4 is used as the signal end;
an input end of the fourth inverter INV4 serves as a control end.
Optionally, the voltage dividing circuit includes first to fifth resistors R1 to R5, where the first to fifth resistors R1 to R5 are connected in series;
the other end of the first resistor R1 is connected with VREF;
the other end of the fifth resistor R5 is grounded;
the middle of the second resistor R2 and the third resistor R3 is used as a first leading-out end of the voltage dividing circuit;
the middle of the third resistor R3 and the fourth resistor R4 is used as a second leading-out end of the voltage dividing circuit.
Optionally, the circuit further comprises a second inverter INV2 and a third inverter INV3;
the second inverter INV2 is connected in series with the third inverter INV3;
the input end of the third inverter INV3 is connected to the drain electrode of the fourth NMOS transistor N4;
an output terminal of the second inverter INV2 is connected to an input terminal of the first inverter INV 1.
The embodiment of the application also provides electronic equipment, which comprises the over-temperature protection circuit.
The transmission gate and the comparator circuit have wide temperature hysteresis quantity and high-efficiency conversion rate, and when the power supply voltage changes, the circuit performance is stable.
The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
fig. 1 is an example of the overall structure of an over-temperature protection circuit according to an embodiment of the present application;
fig. 2 is a basic circuit configuration example of an over-temperature protection circuit according to an embodiment of the present application;
fig. 3 is a specific circuit configuration example of the over-temperature protection circuit according to the embodiment of the present application;
fig. 4 is a diagram of temperature hysteresis simulation results of an over-temperature protection circuit according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The embodiment of the application provides an over-temperature protection circuit, as shown in fig. 1 and 2, including:
the voltage dividing circuit is mainly used for generating the turn-off of two voltage control main body BJT transistors (first NPN transistor Q1), and in this embodiment, a voltage dividing resistor is disposed between the reference voltage and ground for connecting to the transmission gate based on the voltage dividing resistor.
The transmission gate is configured to selectively transmit the divided voltage to a subsequent circuit, and in this embodiment of the present application, as shown in fig. 2, the transmission gate includes a first NMOS transistor N1, a first PMOS transistor P1, and a first inverter INV1, where:
the source electrode of the first NMOS tube N1 is connected with the source electrode of the first PMOS tube P1 and is connected to the first leading-out end of the voltage dividing circuit.
The drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS tube P1 and is connected to the second leading-out end of the voltage dividing circuit.
The grid electrode of the first NMOS tube N1 is connected to the input end of the first inverter INV1, and the output end of the first inverter INV1 is connected to the grid electrode of the first PMOS tube P1.
And the bias circuit is used for providing bias current for the main circuit and providing bias current for the comparator circuit based on a plurality of groups of PMOS tubes in a specific example.
The comparator circuit is configured to increase the slew rate, and includes a first NPN tube Q1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, and a second NPN tube Q2, where:
and the base electrode of the first NPN pipe Q1 (main body BJT pipe) is connected with the drain electrode of the first NMOS pipe N1, the emitter electrode is grounded, and the collector electrode is connected with bias current.
The source electrode of the second NMOS tube N2, the third NMOS tube N3 and the fourth NMOS tube N4 are grounded, and the drain electrode of the second NMOS tube is connected with bias current;
the grid electrode of the second NMOS tube N2 is connected with the collector electrode of the first NPN tube Q1;
the grid electrode of the third NMOS tube N3 is connected to the drain electrode of the second NMOS tube N2;
the grid electrode of the fourth NMOS tube N4 is connected to the drain electrode of the third NMOS tube N3;
and the base electrode of the second NPN tube Q2 is connected with the collector electrode of the second NPN tube Q and the grid electrode of the fourth NMOS tube N4, the emitter electrode of the second NPN tube Q is grounded through the series connection of a resistor R6 and a capacitor C1, and the emitter electrode of the second NPN tube Q is connected to the grid electrode of the second NMOS tube N2.
The transmission gate and the comparator circuit have wide temperature hysteresis quantity and high-efficiency conversion rate, and when the power supply voltage changes, the circuit performance is stable.
In some embodiments, the bias circuit includes a fourth PMOS transistor P4 to a thirteenth PMOS transistor P13, wherein:
the sources of the fourth PMOS tube P4 to the eighth PMOS tube P8 are connected with VDD;
the grid electrode and the drain electrode of the fourth PMOS tube P4 are in short circuit;
the gates of the fifth PMOS transistor P5 to the eighth PMOS transistor P8 are all connected to the gate of the fourth PMOS transistor P4;
the drain electrode of the fourth PMOS tube P4 is connected with the source electrode of the thirteenth PMOS tube P13, and the drain electrode of the fifth PMOS tube P5 is connected with the source electrode of the twelfth PMOS tube P12;
the drain electrode of the sixth PMOS tube P6 is connected with the source electrode of the eleventh PMOS tube P11;
the drain electrode of the seventh PMOS tube P7 is connected with the source electrode of the tenth PMOS tube P10;
the drain electrode of the eighth PMOS tube P8 is connected with the source electrode of the ninth PMOS tube P9;
the grid electrode and the drain electrode of the thirteenth PMOS tube P13 are short-circuited;
the gates of the ninth to twelfth PMOS tubes P9 to P12 are connected to the gate of the thirteenth PMOS tube P13. The drain electrode of the thirteenth PMOS tube P13 is connected with external current IBN_10U, IBN_10U flows in as 10uA current, flows into the main body BJT tube Q1, the second NMOS tube N2, the third NMOS tube N3 and the fourth NMOS tube N4 through a bias current circuit, and the bias current circuit works by copying the current in proportion through the width-to-length ratio between the tubes.
In a specific application example, as shown in fig. 3, the device further includes a second PMOS transistor P2 and a third PMOS transistor P3;
the grid electrode of the second PMOS tube P2 is connected with a signal end, the drain electrode of the second PMOS tube P2 is connected to the drain electrode of the first NMOS tube N1, and the source electrode of the second PMOS tube P3 is connected to the drain electrode of the third PMOS tube P3;
and the grid electrode of the third PMOS tube P3 is connected to the drain electrode of the fourth PMOS tube P4, and the source electrode of the third PMOS tube P3 is connected to VDD. In some embodiments, the circuit further comprises a fourth inverter INV4, and an output end of the fourth inverter INV4 is used as the signal end; an input end of the fourth inverter INV4 serves as a control end.
In some embodiments, as shown in fig. 2 and 3, the voltage dividing circuit includes first to fifth resistors R1 to R5, wherein the first to fifth resistors R1 to R5 are connected in series;
the other end of the first resistor R1 is connected with VREF;
the other end of the fifth resistor R5 is grounded;
the middle of the second resistor R2 and the third resistor R3 is used as a first leading-out end of the voltage dividing circuit;
the middle of the third resistor R3 and the fourth resistor R4 is used as a second leading-out end of the voltage dividing circuit.
In some embodiments, the second inverter INV2 and the third inverter INV3 are further included;
the second inverter INV2 is connected in series with the third inverter INV3;
the input end of the third inverter INV3 is connected to the drain electrode of the fourth NMOS transistor N4;
an output terminal of the second inverter INV2 is connected to an input terminal of the first inverter INV 1. According to the embodiment of the application, the two inverters are connected in series and used for realizing signal isolation, improving the high impedance characteristic of the pin, enabling the signal not to be affected, and after the two inverters pass through, the signal level is consistent with the original signal. In some embodiments, the over-temperature protection circuit may be implemented using a 0.35um BCD process.
In the operational amplifier design, the conversion rate means the reaction capability of the fast transient voltage, and when the temperature protection hysteresis exists for the over-temperature protection circuit, if the sensitivity of the circuit to voltage change can be improved, the reaction capability of the circuit to the voltage change is enhanced, and the loss of power consumption can be reduced. The reasons for the low slew rate in the prior art are: parasitic capacitance, inter-stage capacitance between operational amplifiers, operational amplifier gain and the like. In this embodiment of the present application, the base and collector of the second NPN tube Q2 are shorted, which is equivalent to a diode, and mainly functions as temperature compensation. When the voltage VX divided by the reference voltage VREF is applied to the VBE of the first NPN transistor Q1, and at low temperature, the voltage cannot turn on the first NPN transistor Q1, so that the second NMOS transistor N2 is turned on, the third NMOS transistor N3 is turned off, the fourth NMOS transistor N4 is turned on, the output low level is fed back to the transmission gate, and the transmission gate is turned off. As the temperature increases, VBE decreases. The first NPN tube Q1 is conducted, the second NMOS tube N2 is cut off, the third NMOS tube N3 is conducted, the fourth NMOS tube N4 is cut off, a high level is output, meanwhile, the transmission gate is turned on, and VY voltage is applied to VBE of the first NPN tube Q1, so that hysteresis of temperature protection is formed; meanwhile, the gain of the two-stage common-source amplifier formed by the N2 and N3 tubes is improved, and the response speed and the comparison precision are improved. As shown in fig. 4, the thermal shutdown and on temperatures of the over-temperature protection circuit according to the verification of the application example are 158 ℃ and 130 ℃, respectively, and the over-temperature protection circuit has higher temperature working capacity and 28 ℃ temperature hysteresis; the conversion rate is higher, and the characteristics of high sensitivity and high precision are achieved; when the power supply voltage changes, the circuit performance is stable.
The embodiment of the application also provides electronic equipment, which comprises the over-temperature protection circuit.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the protection of the claims, which fall within the protection of the present application.
Claims (5)
1. An over-temperature protection circuit, comprising:
the voltage dividing circuit is used for setting a voltage dividing resistor between the reference voltage and the ground and connecting to the transmission gate based on the voltage dividing resistor;
the transmission gate comprises a first NMOS tube N1, a first PMOS tube P1 and a first inverter INV1, wherein:
the source electrode of the first NMOS tube N1 is connected with the source electrode of the first PMOS tube P1 and is connected to the first leading-out end of the voltage dividing circuit;
the drain electrode of the first NMOS tube N1 is connected with the drain electrode of the first PMOS tube P1 and is connected to the second leading-out end of the voltage dividing circuit;
the grid electrode of the first NMOS tube N1 is connected to the input end of the first inverter INV1, and the output end of the first inverter INV1 is connected to the grid electrode of the first PMOS tube P1;
the bias circuit is used for providing bias current for the comparator circuit based on a plurality of groups of PMOS tubes;
the comparator circuit comprises a first NPN tube Q1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4 and a second NPN tube Q2, wherein:
the base electrode of the first NPN tube Q1 is connected with the drain electrode of the first NMOS tube N1, the emitter electrode is grounded, and the collector electrode is connected with bias current;
the source electrode of the second NMOS tube N2, the third NMOS tube N3 and the fourth NMOS tube N4 are grounded, and the drain electrode of the second NMOS tube is connected with bias current;
the grid electrode of the second NMOS tube N2 is connected with the collector electrode of the first NPN tube Q1;
the grid electrode of the third NMOS tube N3 is connected to the drain electrode of the second NMOS tube N2;
the grid electrode of the fourth NMOS tube N4 is connected to the drain electrode of the third NMOS tube N3;
the base electrode of the second NPN tube Q2 is connected with the collector electrode of the second NPN tube Q and the grid electrode of the fourth NMOS tube N4, the emitter electrode of the second NPN tube Q2 is grounded through the series connection of a resistor R6 and a capacitor C1, and the emitter electrode of the second NPN tube Q is connected to the grid electrode of the second NMOS tube N2;
the bias circuit comprises a fourth PMOS tube P4 to a thirteenth PMOS tube P13, wherein:
the sources of the fourth PMOS tube P4 to the eighth PMOS tube P8 are connected with VDD;
the grid electrode and the drain electrode of the fourth PMOS tube P4 are in short circuit;
the gates of the fifth PMOS transistor P5 to the eighth PMOS transistor P8 are all connected to the gate of the fourth PMOS transistor P4;
the drain electrode of the fourth PMOS tube P4 is connected with the source electrode of the thirteenth PMOS tube P13, and the drain electrode of the fifth PMOS tube P5 is connected with the source electrode of the twelfth PMOS tube P12;
the drain electrode of the sixth PMOS tube P6 is connected with the source electrode of the eleventh PMOS tube P11;
the drain electrode of the seventh PMOS tube P7 is connected with the source electrode of the tenth PMOS tube P10;
the drain electrode of the eighth PMOS tube P8 is connected with the source electrode of the ninth PMOS tube P9;
the grid electrode and the drain electrode of the thirteenth PMOS tube P13 are short-circuited;
the gates of the ninth PMOS tube P9 to the twelfth PMOS tube P12 are connected with the gate of the thirteenth PMOS tube P13;
the circuit also comprises a second inverter INV2 and a third inverter INV3;
the second inverter INV2 is connected in series with the third inverter INV3;
the input end of the third inverter INV3 is connected to the drain electrode of the fourth NMOS transistor N4;
an output terminal of the second inverter INV2 is connected to an input terminal of the first inverter INV 1.
2. The over-temperature protection circuit of claim 1, further comprising a second PMOS transistor P2, a third PMOS transistor P3;
the grid electrode of the second PMOS tube P2 is connected with a signal end, the drain electrode of the second PMOS tube P2 is connected to the drain electrode of the first NMOS tube N1, and the source electrode of the second PMOS tube P3 is connected to the drain electrode of the third PMOS tube P3;
and the grid electrode of the third PMOS tube P3 is connected to the drain electrode of the fourth PMOS tube P4, and the source electrode of the third PMOS tube P3 is connected to VDD.
3. The over-temperature protection circuit according to claim 1, further comprising a fourth inverter INV4, an output terminal of the fourth inverter INV4 being the signal terminal;
an input end of the fourth inverter INV4 serves as a control end.
4. The over-temperature protection circuit according to claim 1, wherein the voltage dividing circuit includes first to fifth resistors R1 to R5, wherein the first to fifth resistors R1 to R5 are connected in series;
the other end of the first resistor R1 is connected with VREF;
the other end of the fifth resistor R5 is grounded;
the middle of the second resistor R2 and the third resistor R3 is used as a first leading-out end of the voltage dividing circuit;
the middle of the third resistor R3 and the fourth resistor R4 is used as a second leading-out end of the voltage dividing circuit.
5. An electronic device comprising an overtemperature protection circuit as claimed in any one of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310085351.6A CN116093887B (en) | 2023-02-09 | 2023-02-09 | Over-temperature protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310085351.6A CN116093887B (en) | 2023-02-09 | 2023-02-09 | Over-temperature protection circuit |
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| CN116093887A CN116093887A (en) | 2023-05-09 |
| CN116093887B true CN116093887B (en) | 2023-07-25 |
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| CN202310085351.6A Active CN116093887B (en) | 2023-02-09 | 2023-02-09 | Over-temperature protection circuit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0234024A (en) * | 1988-07-25 | 1990-02-05 | Fujitsu Ltd | Temperature protecting circuit for semiconductor device |
| CN101330208A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protecting circuit |
| CN104113041A (en) * | 2014-05-30 | 2014-10-22 | 西安电子科技大学 | Under-voltage protection circuit for Ethernet power supply |
| CN105487590A (en) * | 2016-02-02 | 2016-04-13 | 厦门新页微电子技术有限公司 | Current feedback type precise over-temperature protection circuit |
-
2023
- 2023-02-09 CN CN202310085351.6A patent/CN116093887B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0234024A (en) * | 1988-07-25 | 1990-02-05 | Fujitsu Ltd | Temperature protecting circuit for semiconductor device |
| CN101330208A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protecting circuit |
| CN104113041A (en) * | 2014-05-30 | 2014-10-22 | 西安电子科技大学 | Under-voltage protection circuit for Ethernet power supply |
| CN105487590A (en) * | 2016-02-02 | 2016-04-13 | 厦门新页微电子技术有限公司 | Current feedback type precise over-temperature protection circuit |
Non-Patent Citations (1)
| Title |
|---|
| 一种高精度阈值可调过温保护电路的设计;张瓷平 等;电子元件与材料;第36卷(第8期);第75-79页 * |
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| CN116093887A (en) | 2023-05-09 |
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