CN112667014A - Band-gap reference circuit applied to ultra-low voltage scene - Google Patents
Band-gap reference circuit applied to ultra-low voltage scene Download PDFInfo
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Abstract
本发明公开了一种应用于超低压电压场景的带隙基准电路，包括：第一启动电路、第二启动电路和核心电路；第一启动电路包括第一MOS管M1、第二MOS管M2、第三MOS管M3和电阻R1；M1的源极、M2的源极以及M3的漏极均接入电源；M1的栅极、M2的栅极和M3的源极彼此连接，并与R1串联后接地；M1的漏极、M2的漏极和M3的栅极均与核心电路连接；第二启动电路包括第四MOS管M4、第五MOS管M5、三极管J1和比较器U1；U1的同相输入端分别与M4的漏极和J1的发射极连接；J1的基极和集电极连接后接地；U1的反相输入端与核心电路连接，输出端与M5的栅极连接；M5的源极接地，漏极与M4的栅极连接；M4的源极接入电源。本发明可以工作在1V甚至更低的工作电压场景下。
The invention discloses a bandgap reference circuit applied to an ultra-low voltage scenario, comprising: a first start-up circuit, a second start-up circuit and a core circuit; the first start-up circuit includes a first MOS transistor M1, a second MOS transistor M2, The third MOS transistor M3 and the resistor R1; the source of M1, the source of M2 and the drain of M3 are all connected to the power supply; the gate of M1, the gate of M2 and the source of M3 are connected to each other and connected in series with R1 Ground; the drain of M1, the drain of M2 and the gate of M3 are all connected to the core circuit; the second start-up circuit includes a fourth MOS transistor M4, a fifth MOS transistor M5, a triode J1 and a comparator U1; the non-inverting input of U1 The terminals are respectively connected to the drain of M4 and the emitter of J1; the base and collector of J1 are connected to the ground; the inverting input terminal of U1 is connected to the core circuit, and the output terminal is connected to the gate of M5; the source of M5 is grounded , the drain is connected to the gate of M4; the source of M4 is connected to the power supply. The present invention can work under a working voltage scenario of 1V or even lower.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a band-gap reference circuit applied to an ultra-low voltage scene.
Background
With the rise of intelligent internet of things, the ultra-low voltage chip is widely applied to various scenes such as internet of things radio frequency, battery management, sensing front end and energy collection. The band-gap reference circuit is used as a general analog technology, and the working principle is as follows: according to the characteristic that the band gap voltage of the silicon material is irrelevant to the temperature, the negative temperature coefficient of the voltage of the base electrode-the emitter electrode of the bipolar transistor and the positive temperature coefficient of the difference value of the base electrode-the emitter electrode voltages of the two bipolar transistors under different current densities are mutually compensated, so that the output voltage reaches very low temperature drift. The prior art bandgap reference circuit generally needs a high voltage, which is higher than a voltage of about 1.5V or more, and generates a reference voltage output of about 1.2V, so that the prior art bandgap reference circuit cannot adapt to a voltage scene of ultra-low voltage of 1.0V or less.
Therefore, how to provide a bandgap reference circuit capable of operating at an operating voltage of 1V or lower is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of this, the invention provides a bandgap reference circuit applied to an ultra-low voltage scenario, which can operate in an operating voltage scenario of 1V or even lower.
In order to achieve the purpose, the invention adopts the following technical scheme:
a bandgap reference circuit for ultra-low voltage scenarios, comprising: the first starting circuit, the second starting circuit and the core circuit are connected in sequence;
the first starting circuit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a resistor R1; the source electrode of the first MOS transistor M1, the source electrode of the second MOS transistor M2 and the drain electrode of the third MOS transistor M3 are all connected with a power supply; the grid electrode of the first MOS transistor M1, the grid electrode of the second MOS transistor M2 and the source electrode of the third MOS transistor M3 are connected with each other, and are connected with the resistor R1 in series and then grounded; the drain electrode of the first MOS transistor M1, the drain electrode of the second MOS transistor M2 and the gate electrode of the third MOS transistor M3 are all connected with the core circuit;
the second starting circuit comprises a fourth MOS tube M4, a fifth MOS tube M5, a triode J1 and a comparator U1; the non-inverting input end of the comparator U1 is respectively connected with the drain electrode of the fourth MOS tube M4 and the emitter electrode of the triode J1; the base electrode and the collector electrode of the triode J1 are grounded after being connected; the inverting input end of the comparator U1 is connected with the core circuit, and the output end of the comparator U1 is connected with the grid electrode of the fifth MOS tube M5; the source electrode of the fifth MOS transistor M5 is grounded, and the drain electrode is connected with the gate electrode of the fourth MOS transistor M4; the source electrode of the fourth MOS tube M4 is connected to the power supply.
Preferably, in the above band gap reference circuit applied to an ultra-low voltage scenario, the core circuit includes a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, an operational amplifier U2, a transistor J2, and a transistor J3; the non-inverting input end of the operational amplifier U2 is respectively connected with the inverting input end of the comparator U1 and the emitter of the triode J2; the base electrode and the collector electrode of the triode J2 are both grounded; the inverting input end of the operational amplifier U2 is respectively connected with the emitter of the triode J3, the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2; the base electrode and the collector electrode of the triode J3 are both grounded; the output end of the operational amplifier U1 is connected to the gate of the third MOS transistor M3, the gate of the fourth MOS transistor M4, the drain of the fifth MOS transistor M5, the gate of the sixth MOS transistor M6, the gate of the seventh MOS transistor M7, and the gate of the eighth MOS transistor M8, respectively; the drain electrode of the sixth MOS transistor M6, the drain electrode of the seventh MOS transistor M7 and the source electrode of the eighth MOS transistor M8 are all connected to the power supply.
Preferably, in the above bandgap reference circuit applied to an ultra-low voltage scenario, the core circuit further includes: a resistor R2, a resistor R3, a resistor R4 and a resistor R5; one end of the resistor R2 is grounded, and the other end of the resistor R2 is respectively connected with the inverting input end of the comparator U1 and the non-inverting input end of the operational amplifier U2; one end of the resistor R3 is connected with an emitter of the triode J2, and the other end of the resistor R3 is respectively connected with an inverting input end of the comparator U1, a non-inverting input end of the operational amplifier U2 and a drain electrode of the eighth MOS transistor M8; one end of the resistor R4 is grounded, and the other end of the resistor R4 is respectively connected with the inverting input end of the operational amplifier U2 and the drain electrode of the first MOS transistor M1; one end of the resistor R5 is grounded, and the other end is connected to the source of the sixth MOS transistor M6.
Preferably, in the above bandgap reference circuit applied to an ultra-low voltage scenario, the third MOS transistor M3 is composed of 4 PMOS transistors connected in parallel.
Preferably, in the above bandgap reference circuit applied to an ultra-low voltage scenario, the fourth MOS transistor M4 is formed by connecting 7 PMOS transistors in parallel.
Preferably, in the above bandgap reference circuit applied to an ultra-low voltage scenario, the sixth MOS transistor M6 is composed of 4 PMOS transistors connected in parallel.
Preferably, in the above bandgap reference circuit applied to an ultra-low voltage scenario, the seventh MOS transistor M7 is composed of 4 PMOS transistors connected in parallel.
Preferably, in the above bandgap reference circuit applied to an ultra-low voltage scenario, the eighth MOS transistor M8 is formed by connecting 6 PMOS transistors in parallel.
Preferably, in the bandgap reference circuit applied to the ultra-low voltage scenario, the transistor J1 is composed of 27 transistors connected in parallel.
Preferably, in the bandgap reference circuit applied to the ultra-low voltage scenario, the transistor J2 is formed by connecting 8 transistors in parallel.
According to the technical scheme, compared with the prior art, the invention discloses the band-gap reference circuit applied to the ultra-low voltage scene, and the band-gap reference circuit has the following beneficial effects:
1. the first starting circuit and the second starting circuit are combined, so that the low-voltage reference can normally work during power-on and power-off and normal work. The circuitry of the first start-up circuit and the second start-up circuit and combinations thereof need to be protected.
2. The working voltage of the core circuit is the sum of the working voltage (0.7) of the triodes J2 and J3 and the Vdsat (0.1) of the PMOS tube, the core circuit can work at about 0.8V, and the voltage requirement of a low-voltage reference is met.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a reference circuit according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention discloses a bandgap reference circuit applied to an ultra-low voltage scenario, including: the first starting circuit, the second starting circuit and the core circuit are connected in sequence;
the first starting circuit comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3 and a resistor R1; the source electrode of the first MOS transistor M1, the source electrode of the second MOS transistor M2 and the drain electrode of the third MOS transistor M3 are all connected with a power supply; the grid electrode of the first MOS transistor M1, the grid electrode of the second MOS transistor M2 and the source electrode of the third MOS transistor M3 are connected with each other, and are connected with the resistor R1 in series and then grounded; the drain electrode of the first MOS transistor M1, the drain electrode of the second MOS transistor M2 and the gate electrode of the third MOS transistor M3 are all connected with the core circuit;
the second starting circuit comprises a fourth MOS tube M4, a fifth MOS tube M5, a triode J1 and a comparator U1; the non-inverting input end of the comparator U1 is respectively connected with the drain electrode of the fourth MOS tube M4 and the emitter electrode of the triode J1; the base electrode and the collector electrode of the triode J1 are grounded after being connected; the inverting input end of the comparator U1 is connected with the core circuit, and the output end of the comparator U1 is connected with the grid electrode of the fifth MOS tube M5; the source electrode of the fifth MOS transistor M5 is grounded, and the drain electrode is connected with the gate electrode of the fourth MOS transistor M4; the source electrode of the fourth MOS tube M4 is connected to the power supply.
The core circuit comprises a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, an operational amplifier U2, a triode J2, a triode J3, a resistor R2, a resistor R3, a resistor R4 and a resistor R5; the non-inverting input end of the operational amplifier U2 is respectively connected with the inverting input end of the comparator U1 and the emitter of the triode J2; the base electrode and the collector electrode of the triode J2 are both grounded; the inverting input end of the operational amplifier U2 is respectively connected with the emitter of the triode J3, the drain of the first MOS transistor M1 and the drain of the second MOS transistor M2; the base electrode and the collector electrode of the triode J3 are both grounded; the output end of the operational amplifier U1 is connected to the gate of the third MOS transistor M3, the gate of the fourth MOS transistor M4, the drain of the fifth MOS transistor M5, the gate of the sixth MOS transistor M6, the gate of the seventh MOS transistor M7, and the gate of the eighth MOS transistor M8, respectively; the drain electrode of the sixth MOS transistor M6, the drain electrode of the seventh MOS transistor M7 and the source electrode of the eighth MOS transistor M8 are all connected to the power supply.
One end of the resistor R2 is grounded, and the other end of the resistor R2 is respectively connected with the inverting input end of the comparator U1 and the non-inverting input end of the operational amplifier U2; one end of the resistor R3 is connected with an emitter of the triode J2, and the other end of the resistor R3 is respectively connected with an inverting input end of the comparator U1, a non-inverting input end of the operational amplifier U2 and a drain electrode of the eighth MOS transistor M8; one end of the resistor R4 is grounded, and the other end of the resistor R4 is respectively connected with the inverting input end of the operational amplifier U2 and the drain electrode of the first MOS transistor M1; one end of the resistor R5 is grounded, and the other end is connected to the source of the sixth MOS transistor M6.
In other embodiments, the third MOS transistor M3 is composed of 4 PMOS transistors connected in parallel. The fourth MOS transistor M4 is formed by connecting 7 PMOS transistors in parallel. The sixth MOS transistor M6 is formed by connecting 4 PMOS transistors in parallel. The seventh MOS transistor M7 is formed by connecting 4 PMOS transistors in parallel. The eighth MOS transistor M8 is formed by connecting 6 PMOS transistors in parallel. The transistor J1 is composed of 27 transistors connected in parallel. The transistor J2 is formed by 8 transistors connected in parallel.
The expression of the reference voltage of the invention is as follows:
in the above formula,. DELTA.VBEIndicating the voltage deviation, V, between transistor J2 and transistor J3BERepresenting the voltage difference, V, between the base and emitter of transistor J1refRepresenting the reference voltage output value.
The implementation of fig. 1 is divided into three parts: the circuit comprises a first starting circuit, a second starting circuit and a core circuit. The first starting circuit is composed of a component resistor R1, a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3 and is mainly responsible for starting a core circuit. The second starting circuit is composed of a fourth MOS transistor M4, a fifth MOS transistor M5, a triode J1 and a comparator U1. Mainly responsible for detecting whether the core circuit is started normally, if soAnd if not, the core circuit is pulled back to a normal working state. The core circuit comprises a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, an operational amplifier U2, a triode J2, a triode J3, a resistor R2, a resistor R3, a resistor R4 and a resistor R5. Mainly responsible for realizing the output electricity V which is not changed with the temperatureref. The working voltage of the core circuit is the sum of the working voltage of the triodes J2 and J3 and Vdsat of the PMOS tube, and the Vdsat represents that the voltage difference between the drain and the source meets the requirement of low voltage in an application scene when M3, M4, M6, M7 and M8 work in a saturation state.
A bandgap reference circuit will typically have 2 or more degeneracy points present: as shown in fig. 1, there are 3 simple points of the bandgap reference circuit, which require a start-up circuit to pull the reference to the desired degeneracy point.
The first degeneracy point is where the respective device currents are all zero and is undesirable. When the circuit is operating at this degenerate point. Normally the first start-up circuit will operate. At this time point E is normally low. M1 and M2 are on. Current was injected to point B through M1. The operational amplifier is operated by sinking current through M2. The operational amplifier makes the D point low, so that M8, M7, M6, M4 and M3 all inject current. Thereby bringing the fiducial into other degenerate points. When the current of M3 increases, the point E rises, and M1 and M2 are cut off. The first startup circuit completes the startup task.
When M8, M7, M6, M4 and M3 have current flowing through MOS transistor, current must flow through R2 and R4, if the voltage at points A and B is not enough to turn on J2 and J3, then the second abnormal degenerate point is entered. At this point, the second start-up circuit starts operating. The current of M4 produces a voltage after flowing through J1, through the electric current of reasonable design M4, the number of triode in J3 makes C point voltage be higher than A point voltage. Thus, the output of the comparator U1 is high, the D point is pulled low continuously through the M5, the currents of the M8, the M7, the M6, the M4 and the M3 are increased continuously, and finally the J2 and the J3 are conducted, the voltage at the C point is lower than the voltage at the A point, the output of the comparator U1 is low, and the M5 is cut off. The benchmark enters a normal operating mode.
If the voltage suddenly drops, the normal voltage is restored later. So that the triode enters a closed state and enters a first degenerated point. In this case, as long as the comparator U1 is active, the circuit can be moved away from the first degeneracy point and operate normally.
In normal operation, it is possible to put the bandgap reference into the BJT off state for some reasons, and by adding the second start-up circuit, the second degeneracy point is also avoided.
The embodiment of the invention respectively sets the combination of the first starting circuit and the second starting circuit and the core circuit through two key settings. The first starting circuit and the second starting circuit are combined, so that the low-voltage reference can normally work during power-on and power-off and normal work. The circuitry of the first start-up circuit and the second start-up circuit and combinations thereof need to be protected.
The working voltage of the core circuit is the sum of the working voltage (0.7) of the triodes J2 and J3 and the Vdsat (0.1) of the PMOS tube, the core circuit can work at about 0.8V, and the voltage requirement of a low-voltage reference is met.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011625656.4A CN112667014B (en) | 2020-12-31 | A bandgap reference circuit for ultra-low voltage scenarios |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011625656.4A CN112667014B (en) | 2020-12-31 | A bandgap reference circuit for ultra-low voltage scenarios |
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| CN112667014A true CN112667014A (en) | 2021-04-16 |
| CN112667014B CN112667014B (en) | 2025-02-21 |
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Cited By (1)
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| CN113110678A (en) * | 2021-04-21 | 2021-07-13 | 湖南融创微电子有限公司 | High-reliability starting circuit based on low power supply voltage bandgap and control method |
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