CN114281148B - Dynamic current bias circuit - Google Patents
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- CN114281148B CN114281148B CN202111450823.0A CN202111450823A CN114281148B CN 114281148 B CN114281148 B CN 114281148B CN 202111450823 A CN202111450823 A CN 202111450823A CN 114281148 B CN114281148 B CN 114281148B
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Abstract
The invention discloses a dynamic current bias circuit, comprising: the device comprises a virtual power supply providing module, a power supply voltage monitoring module and a current mirror module; the virtual power supply providing module is connected with the power supply and used for outputting constant virtual voltage when the power supply voltage is reduced; the power supply voltage monitoring module is respectively connected with the power supply and the virtual power supply providing module and is used for generating a first current in direct proportion to the power supply voltage reduction speed when the power supply voltage is reduced; the current mirror module is connected with the virtual power supply providing module and used for providing a second current which is in direct proportion to the power supply voltage dropping speed for a subsequent circuit based on constant virtual voltage and first current when the power supply voltage drops. The final output bias current of the dynamic current bias circuit is dynamically adjusted and is proportional to the power supply reduction rate, and the problem of insufficient response speed of the biased circuit is solved while the low power consumption of the circuit is maintained.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a dynamic current bias circuit.
Background
In the design of integrated circuits, in order to amplify signal voltages without distortion, amplifiers composed of semiconductor devices such as transistors and MOS transistors must ensure that these devices are in a specific operating state, i.e., their operating points should be set, and the setting of these operating points can be realized by external circuits, which are called bias circuits. Of course, in addition to the amplifier, many circuit structures in the integrated circuit, which are usually called subsequent circuits driven by the bias circuit, need to be provided with an operating point or a stable initial state by the bias circuit, so that the bias circuit is very important in the integrated circuit and has wide application. The bias circuit is divided into different types of current bias circuit and voltage bias circuit according to the type of signal supplied.
In the applications of the internet of things, wearable equipment and the like, low power consumption is an extremely important circuit performance index. However, in the conventional circuit, the power consumption of the current bias circuit is substantially linearly related to the circuit speed, and it is difficult to maintain a low power consumption and a fast response speed.
For example, in some power-on/power-off reset circuits, the current bias circuit needs to respond quickly to power-off of the power supply, but is limited by power consumption requirements, and response speed is difficult to increase.
Therefore, a dynamic current bias circuit is particularly needed to solve the problems of power consumption and circuit response speed in the power-on/power-off reset circuit.
Disclosure of Invention
The invention aims to provide a dynamic current bias circuit for solving the problems of power consumption and circuit response speed in a power-on/power-off reset circuit.
In order to achieve the above object, the present invention provides a dynamic current bias circuit comprising: the device comprises a virtual power supply providing module, a power supply voltage monitoring module and a current mirror module; the virtual power supply providing module is connected with a power supply and used for outputting constant virtual voltage when the power supply voltage is reduced; the power supply voltage monitoring module is respectively connected with the power supply and the virtual power supply providing module and is used for generating a first current in direct proportion to the power supply voltage reduction speed when the power supply voltage is reduced; the current mirror image module is connected with the virtual power supply providing module and used for providing a second current which is in direct proportion to the power supply voltage dropping speed for a subsequent circuit based on the constant virtual voltage and the first current when the power supply voltage drops.
Preferably, the virtual power supply module includes: the power supply circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a first PMOS (P-channel metal oxide semiconductor) tube, a first capacitor and a current source; the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube and the anode of the power supply, the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube and the anode of the power supply, and the source electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube and one end of a first capacitor; the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube and one end of a first capacitor, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube and the anode of a current source, and the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube and the anode of the current source; the negative pole of the current source is connected with the negative pole of the power supply, and the other end of the first capacitor is connected with the negative pole of the power supply.
Preferably, the power supply voltage monitoring module includes: the second capacitor, the first PMOS tube and the current source are connected; one end of the second capacitor is connected with the drain electrode and the grid electrode of the first NMOS tube and the anode of the power supply respectively, and the other end of the second capacitor is connected with the drain electrode and the grid electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube and one end of a first capacitor, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube, the positive electrode of the current source and the other end of the second capacitor, and the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube, the positive electrode of the current source and the other end of the second capacitor.
Preferably, the current mirror module includes: the NMOS transistor comprises a first PMOS transistor, a second NMOS transistor and a third NMOS transistor; the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube, one end of a first capacitor and the source electrode of a second PMOS tube, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube, the anode of a current source, the other end of the second capacitor and the grid electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube, the anode of the current source, the other end of the second capacitor and the grid electrode of the second PMOS tube; the source electrode of the second PMOS tube is connected with the source electrode of the first NMOS tube, one end of a first capacitor and the source electrode of the first PMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first PMOS tube, the positive electrode of a current source and the other end of the second capacitor, and the drain electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube; the drain electrode of the second NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the second PMOS tube, the grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the second PMOS tube, and the source electrode of the second NMOS tube is connected with the negative electrode of the power supply; the grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the second PMOS tube, and the source electrode of the third NMOS tube is connected with the negative electrode of the power supply.
Preferably, the connection between the source of the second PMOS transistor, the source of the first NMOS transistor, one end of the first capacitor, and the source of the first PMOS transistor is a virtual voltage output point.
Preferably, the voltage at the virtual voltage output point is a virtual voltage.
Preferably, when the power supply voltage drops, the current flowing through the second capacitor is the first current proportional to the dropping speed of the power supply voltage.
Preferably, the first current is calculated using the following formula:
I＝C*dVDD/dt
wherein, I is the first current, C is the capacitance of the second capacitor, VDD/dt is the power voltage drop speed, VDD is the power voltage, and t is the drop time.
Preferably, the drain of the third NMOS transistor is used to connect to the subsequent circuit, and provide a second current proportional to the power supply voltage drop speed for the subsequent circuit.
Preferably, the first PMOS transistor and the second PMOS transistor have the same size, and the second NMOS transistor and the third NMOS transistor have the same size.
The invention has the beneficial effects that: the final output bias current of the dynamic current bias circuit is dynamically adjusted and is proportional to the power supply reduction rate, and the problem of insufficient response speed of the biased circuit is solved while the low power consumption of the circuit is maintained.
The apparatus of the present invention has other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts throughout.
Fig. 1 shows a circuit schematic of a dynamic current bias circuit according to the present invention.
Fig. 2 shows the operating waveforms of a dynamic current bias circuit according to the present invention.
Description of reference numerals:
102. a virtual power supply module; 104. a power supply voltage monitoring module; 106. a current mirror module; PM0 and a first PMOS tube; PM1 and a second PMOS tube; NM2, a first NMOS tube; NM0 and a second NMOS tube; NM1, third NMOS tube; c1, a first capacitor; c0 and a second capacitor; ibias, current source; VDD, positive electrode of power supply; GND, negative pole of the power supply; VDD _ Vir, virtual voltage.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below. While the following describes preferred embodiments of the present invention, it should be understood that the present invention may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
A dynamic current bias circuit according to the present invention comprises: the device comprises a virtual power supply providing module, a power supply voltage monitoring module and a current mirror module; the virtual power supply providing module is connected with the power supply and used for outputting constant virtual voltage when the power supply voltage is reduced; the power supply voltage monitoring module is respectively connected with the power supply and the virtual power supply providing module and is used for generating a first current in direct proportion to the power supply voltage reduction speed when the power supply voltage is reduced; the current mirror module is connected with the virtual power supply providing module and used for providing a second current which is in direct proportion to the power supply voltage dropping speed for a subsequent circuit based on constant virtual voltage and first current when the power supply voltage drops.
Specifically, the virtual power supply providing module outputs constant virtual voltage when power supply voltage drops, the power supply voltage monitoring module generates first current in direct proportion to the dropping speed of the power supply voltage, the current mirror module provides second current in direct proportion to the dropping speed of the power supply voltage for a subsequent circuit under the action of the constant virtual voltage and the first current in direct proportion to the dropping speed of the power supply voltage, and the second current is dynamically adjusted according to the amplification factor.
According to the exemplary embodiment, the magnitude of the bias current finally output by the dynamic current bias circuit is dynamically adjusted and is proportional to the power supply reduction rate, and the problem of insufficient response speed of the biased circuit is solved while the low power consumption of the circuit is maintained.
Preferably, the virtual power supply module includes: the power supply circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a first PMOS (P-channel metal oxide semiconductor) tube, a first capacitor and a current source; the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube and the anode of the power supply, the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube and the anode of the power supply, and the source electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube and one end of the first capacitor; the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube and one end of the first capacitor, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube and the anode of the current source, and the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube and the anode of the current source; the negative pole of the current source is connected with the negative pole of the power supply, and the other end of the first capacitor is connected with the negative pole of the power supply.
Specifically, when the power supply voltage works normally, the first capacitor is charged, and when the power supply voltage drops, the first capacitor releases the stored current to form a constant virtual voltage.
Preferably, the power supply voltage monitoring module includes: the second capacitor, the first PMOS tube and the current source; one end of the second capacitor is respectively connected with the drain electrode and the grid electrode of the first NMOS tube and the anode of the power supply, and the other end of the second capacitor is connected with the drain electrode and the grid electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube and one end of the first capacitor, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube, the positive electrode of the current source and the other end of the second capacitor, and the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube, the positive electrode of the current source and the other end of the second capacitor.
Specifically, the power supply voltage monitoring circuit functions to generate a current IC (IC = C0 × vdd/dt) at the second capacitor C0 that is proportional to the rate of decrease of the power supply voltage. The current flowing through the first PMOS transistor at this time is composed of two parts: the smaller constant current source current Ibias, the current IC, which is proportional to the power supply voltage drop rate.
Preferably, the current mirror module includes: the NMOS transistor comprises a first PMOS transistor, a second NMOS transistor and a third NMOS transistor; the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube, one end of the first capacitor and the source electrode of the second PMOS tube, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube, the anode of the current source, the other end of the second capacitor and the grid electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube, the anode of the current source, the other end of the second capacitor and the grid electrode of the second PMOS tube; the source electrode of the second PMOS tube is connected with the source electrode of the first NMOS tube, one end of the first capacitor and the source electrode of the first PMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first PMOS tube, the positive electrode of the current source and the other end of the second capacitor, and the drain electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the drain electrode of the second PMOS tube and the grid electrode of the third NMOS tube; the drain electrode of the second NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the second PMOS tube, the grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the second PMOS tube, and the source electrode of the second NMOS tube is connected with the negative electrode of the power supply; the grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the second PMOS tube, and the source electrode of the third NMOS tube is connected with the negative electrode of the power supply.
Specifically, based on the current mirror image, when the power supply voltage drops, the drain of the first PMOS transistor is connected to the gate, and the source voltage is a constant virtual voltage, so that the first PMOS transistor operates in a saturation region, and the same second PMOS transistor also operates in the saturation region, so that the currents of the first PMOS transistor and the second PMOS transistor are both the sum of the current source and the first current proportional to the power supply voltage dropping speed, and the drain of the third NMOS transistor generates a second current related to the first current proportional to the power supply voltage dropping speed and generated at the second capacitor, where the second current is the sum of the current source and the first current proportional to the power supply voltage dropping speed multiplied by the amplification factor of the third NMOS transistor.
Preferably, the connection between the source electrode of the second PMOS transistor, the source electrode of the first NMOS transistor, one end of the first capacitor, and the source electrode of the first PMOS transistor is a virtual voltage output point.
Preferably, the voltage at the virtual voltage output point is a virtual voltage.
Specifically, the positions of the interconnection of the source electrode of the second PMOS transistor, the source electrode of the first NMOS transistor, one end of the first capacitor, and the source electrode of the first PMOS transistor are virtual voltage output points, the voltage at the points is referred to as virtual voltage, and when the power supply voltage drops, the virtual voltage is kept approximately constant.
Preferably, when the power supply voltage drops, the current flowing through the second capacitor is the first current proportional to the rate of drop of the power supply voltage.
Specifically, the power supply voltage monitoring circuit is operative to generate a current IC (IC = C0 × vdd/dt) at the second capacitor C0 that is proportional to the rate of decrease of the power supply voltage.
Preferably, the first current is calculated using the following formula:
I＝C*dVDD/dt
wherein, I is the first current, C is the capacitance of the second capacitor, VDD/dt is the power voltage drop speed, VDD is the power voltage, and t is the drop time.
Specifically, according to the requirement, a proper capacitance value of the second capacitor is selected to realize dynamic current adjustment.
Preferably, the drain of the third NMOS transistor is used to connect with a subsequent circuit, and provide a second current proportional to the power voltage drop speed for the subsequent circuit.
Specifically, the drain segment of the third NMOS transistor generates a final dynamic current proportional to the power supply droop rate due to the current mirror circuit.
Preferably, the first PMOS transistor and the second PMOS transistor have the same size, and the second NMOS transistor and the third NMOS transistor have the same size.
Specifically, since the first PMOS transistor, the second NMOS transistor, and the third NMOS transistor constitute a current mirror circuit, the first PMOS transistor and the second PMOS transistor have the same size, and the second NMOS transistor and the third NMOS transistor have the same size.
Examples
Fig. 1 shows a circuit schematic of a dynamic current bias circuit according to the present invention. Fig. 2 shows the operating waveforms of a dynamic current bias circuit according to the present invention.
As shown in fig. 1 and 2, the dynamic current bias circuit includes: a virtual power supply providing module 102, a power supply voltage monitoring module 104 and a current mirror module 106; the virtual power supply providing module 102 is connected to a power supply, and is configured to output a constant virtual voltage VDD _ Vir when a power supply voltage decreases; the power supply voltage monitoring module 104 is respectively connected to the power supply and virtual power supply providing module 102, and is configured to generate a first current proportional to a power supply voltage drop speed when the power supply voltage drops; the current mirror module 106 is connected to the virtual power supply providing module 102, and is configured to provide a second current proportional to the power supply voltage falling speed for the subsequent circuit based on the constant virtual voltage and the first current when the power supply voltage falls.
The virtual power supply providing module 102 includes: the first NMOS transistor NM2, the first PMOS transistor PM0, the first capacitor C1 and the current source Ibias; the drain electrode of the first NMOS tube NM2 is connected with the grid electrode of the first NMOS tube NM2 and the positive electrode VDD of the power supply, the grid electrode of the first NMOS tube NM2 is connected with the drain electrode of the first NMOS tube NM2 and the positive electrode VDD of the power supply, and the source electrode of the first NMOS tube NM2 is connected with the source electrode of the first PMOS tube PM0 and one end of the first capacitor C1; the source electrode of the first PMOS pipe PM0 is connected with the source electrode of the first NMOS pipe NM2 and one end of the first capacitor C1, the grid electrode of the first PMOS pipe PM0 is connected with the drain electrode of the first PMOS pipe PM0 and the anode of the current source Ibias, and the drain electrode of the first PMOS pipe PM0 is connected with the grid electrode of the first PMOS pipe PM0 and the anode of the current source Ibias; the negative electrode of the current source Ibias is connected with the negative electrode GND of the power supply, and the other end of the first capacitor C1 is connected with the negative electrode GND of the power supply.
The power supply voltage monitoring module 104 includes: the second capacitor C0, the first PMOS tube PM0 and the current source Ibias; one end of a second capacitor C0 is respectively connected with the drain electrode and the grid electrode of the first NMOS tube NM2 and the positive electrode VDD of the power supply, and the other end of the second capacitor C0 is connected with the drain electrode and the grid electrode of the first PMOS tube PM 0; the source electrode of the first PMOS tube PM0 is connected with the source electrode of the first NMOS tube NM2 and one end of the first capacitor C1, the grid electrode of the first PMOS tube PM0 is connected with the drain electrode of the first PMOS tube PM0, the positive electrode of the current source Ibias and the other end of the second capacitor C0, and the drain electrode of the first PMOS tube PM0 is connected with the grid electrode of the first PMOS tube PM0, the positive electrode of the current source Ibias and the other end of the second capacitor C0.
Wherein the current mirror module 106 includes: the NMOS transistor comprises a first PMOS transistor PM0, a second PMOS transistor PM1, a second NMOS transistor NM0 and a third NMOS transistor NM1; the source electrode of a first PMOS pipe PM0 is connected with the source electrode of a first NMOS pipe NM2 and one end of a first capacitor C1 and the source electrode of a second PMOS pipe PM1, the grid electrode of the first PMOS pipe PM0 is connected with the drain electrode of the first PMOS pipe PM0, the positive electrode of a current source Ibias, the other end of the second capacitor C0 is connected with the grid electrode of the second PMOS pipe PM1, and the drain electrode of the first PMOS pipe PM0 is connected with the grid electrode of the first PMOS pipe PM0, the positive electrode of the current source Ibias, the other end of the second capacitor C0 and the grid electrode of the second PMOS pipe PM 1; the source electrode of the second PMOS tube PM1 is connected with the source electrode of the first NMOS tube NM2, one end of the first capacitor C1 is connected with the source electrode of the first PMOS tube PM0, the grid electrode of the second PMOS tube PM1 is connected with the drain electrode of the first PMOS tube PM0, the grid electrode, the positive electrode of the current source Ibias and the other end of the second capacitor C0, and the drain electrode of the second PMOS tube PM1 is connected with the grid electrode of the second NMOS tube NM0, the drain electrode of the second NMOS tube NM0 and the grid electrode of the third NMOS tube NM1; the drain electrode of the second NMOS tube NM0 is connected with the grid electrode of the second NMOS tube NM0, the grid electrode of the third NMOS tube NM1 and the drain electrode of the second PMOS tube PM1, the grid electrode of the second NMOS tube NM0 is connected with the drain electrode of the second NMOS tube NM0, the grid electrode of the third NMOS tube NM1 and the drain electrode of the second PMOS tube PM1, and the source electrode of the second NMOS tube NM0 is connected with the negative pole GND of the power supply; the grid electrode of the third NMOS tube NM1 is connected with the drain electrode of the second NMOS tube NM0, the grid electrode of the third NMOS tube NM1 and the drain electrode of the second PMOS tube PM1, and the source electrode of the third NMOS tube NM1 is connected with the negative electrode GND of the power supply.
The connection between the source of the second PMOS transistor PM1, the source of the first NMOS transistor NM2, one end of the first capacitor C1, and the source of the first PMOS transistor PM0 is a virtual voltage VDD _ Vir output point.
The voltage of the output point of the virtual voltage VDD _ Vir is the virtual voltage VDD _ Vir.
When the power voltage drops, the current flowing through the second capacitor C0 is a first current proportional to the dropping speed of the power voltage.
Wherein the first current is calculated using the following formula:
I＝C*dVDD/dt
wherein, I is the first current, C is the capacitance of the second capacitor C0, VDD/dt is the power voltage falling speed, VDD is the power voltage, and t is the falling time.
Preferably, the drain of the third NMOS transistor NM1 is configured to be connected to a subsequent circuit, and provide a second current proportional to a power supply voltage drop speed to the subsequent circuit.
The first PMOS tube PM0 and the second PMOS tube PM1 are equal in size, and the second NMOS tube NM0 and the third NMOS tube NM1 are equal in size.
In the embodiment, the size of NM2 is 10um/0.5um, the size of PM0/PM1 is 1um/1um, and the size of NM0/NM1 is 1um/1um; C0/C1 is 0.3pF/8pF respectively; ibias is 10nA.
As shown in FIG. 2, at 10uS, the power voltage starts to drop at a rate of 3v/uS, and the virtual voltage VDD _ Vir is kept relatively constant and changes in a small amount during the power voltage drop. At this time, the current IC0 flowing through the second capacitor C0 rapidly rises from 0nA, and reaches a steady value 730nA at 10.3uS (an ideal value is 0.3pf × 3v/uS =900nA, and an actual value is 730nA due to non-ideal factors such as parasitic capacitance in the circuit). The final output bias current is provided by the drain of NM1 and rapidly rises to 740nA, which is stable, from 10nA when the power supply voltage is constant, and the change ratio is 74 times.
While embodiments of the present invention have been described above, the above description is illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.
Claims (10)
1. A dynamic current bias circuit, comprising: the device comprises a virtual power supply providing module, a power supply voltage monitoring module and a current mirror module;
the virtual power supply providing module is connected with a power supply and used for outputting constant virtual voltage when the power supply voltage is reduced;
the power supply voltage monitoring module is respectively connected with the power supply and the virtual power supply providing module and is used for generating a first current in direct proportion to the power supply voltage reduction speed when the power supply voltage is reduced;
the current mirror image module is connected with the virtual power supply providing module and used for providing a second current which is in direct proportion to the power supply voltage dropping speed for a subsequent circuit based on the constant virtual voltage and the first current when the power supply voltage drops.
2. The dynamic current bias circuit of claim 1, wherein the virtual power supply module comprises: the power supply circuit comprises a first NMOS (N-channel metal oxide semiconductor) tube, a first PMOS (P-channel metal oxide semiconductor) tube, a first capacitor and a current source;
the drain electrode of the first NMOS tube is connected with the grid electrode of the first NMOS tube and the anode of the power supply, the grid electrode of the first NMOS tube is connected with the drain electrode of the first NMOS tube and the anode of the power supply, and the source electrode of the first NMOS tube is connected with the source electrode of the first PMOS tube and one end of a first capacitor;
the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube and one end of a first capacitor, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube and the anode of a current source, and the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube and the anode of the current source;
the negative pole of the current source is connected with the negative pole of the power supply, and the other end of the first capacitor is connected with the negative pole of the power supply.
3. The dynamic current bias circuit of claim 2, wherein the supply voltage monitoring module comprises: the second capacitor, the first PMOS tube and the current source are connected;
one end of the second capacitor is connected with the drain electrode and the grid electrode of the first NMOS tube and the anode of the power supply respectively, and the other end of the second capacitor is connected with the drain electrode and the grid electrode of the first PMOS tube;
the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube and one end of the first capacitor, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube, the positive electrode of the current source and the other end of the second capacitor, and the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube, the positive electrode of the current source and the other end of the second capacitor.
4. The dynamic current bias circuit of claim 3, wherein the current mirror module comprises: the NMOS transistor comprises a first PMOS transistor, a second NMOS transistor and a third NMOS transistor;
the source electrode of the first PMOS tube is connected with the source electrode of the first NMOS tube, one end of a first capacitor and the source electrode of a second PMOS tube, the grid electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube, the anode of a current source, the other end of the second capacitor and the grid electrode of the second PMOS tube, and the drain electrode of the first PMOS tube is connected with the grid electrode of the first PMOS tube, the anode of the current source, the other end of the second capacitor and the grid electrode of the second PMOS tube;
the source electrode of the second PMOS tube is connected with the source electrode of the first NMOS tube, one end of a first capacitor and the source electrode of the first PMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first PMOS tube, the positive electrode of a current source and the other end of the second capacitor, and the drain electrode of the second PMOS tube is connected with the grid electrode of the second NMOS tube, the drain electrode of the second NMOS tube and the grid electrode of the third NMOS tube;
the drain electrode of the second NMOS tube is connected with the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the second PMOS tube, the grid electrode of the second NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the second PMOS tube, and the source electrode of the second NMOS tube is connected with the negative electrode of the power supply;
the grid electrode of the third NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the drain electrode of the second PMOS tube, and the source electrode of the third NMOS tube is connected with the negative electrode of the power supply.
5. The dynamic current bias circuit of claim 4, wherein a connection point of the source of the second PMOS transistor, the source of the first NMOS transistor, one end of the first capacitor and the source of the first PMOS transistor is a virtual voltage output point.
6. The dynamic current bias circuit of claim 5, wherein the voltage at the virtual voltage output point is a virtual voltage.
7. The dynamic current bias circuit of claim 4, wherein the current flowing through the second capacitor is the first current proportional to the rate of supply voltage drop as the supply voltage drops.
8. The dynamic current bias circuit of claim 7, wherein the first current is calculated using the following equation:
I＝C*dVDD/dt
wherein, I is the first current, C is the capacitance of the second capacitor, VDD/dt is the power voltage falling speed, VDD is the power voltage, and t is the falling time.
9. The dynamic current bias circuit of claim 4, wherein the drain of the third NMOS transistor is configured to be coupled to the subsequent circuit to provide a second current proportional to the supply voltage droop speed to the subsequent circuit.
10. The dynamic current bias circuit of claim 4, wherein the first PMOS transistor and the second PMOS transistor are equal in size, and the second NMOS transistor and the third NMOS transistor are equal in size.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN202533829U (en) * | 2012-02-17 | 2012-11-14 | 安凯(广州)微电子技术有限公司 | Non-capacitance low-voltage-differential linear voltage stabilizing system and bias current adjusting circuit thereof |
| CN106330171A (en) * | 2016-08-26 | 2017-01-11 | 成都启臣微电子股份有限公司 | Positive and negative voltage dynamic bias level shifting circuit based on negative voltage detection and band-gap reference |
| CN110545095A (en) * | 2019-07-17 | 2019-12-06 | 南开大学 | Rapid power-down signal detection circuit and power-on reset device for detecting power supply voltage jitter |
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| US20080150614A1 (en) * | 2006-12-20 | 2008-06-26 | Peter Vancorenland | Method and system for dynamic supply voltage biasing of integrated circuit blocks |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202533829U (en) * | 2012-02-17 | 2012-11-14 | 安凯(广州)微电子技术有限公司 | Non-capacitance low-voltage-differential linear voltage stabilizing system and bias current adjusting circuit thereof |
| CN106330171A (en) * | 2016-08-26 | 2017-01-11 | 成都启臣微电子股份有限公司 | Positive and negative voltage dynamic bias level shifting circuit based on negative voltage detection and band-gap reference |
| CN110545095A (en) * | 2019-07-17 | 2019-12-06 | 南开大学 | Rapid power-down signal detection circuit and power-on reset device for detecting power supply voltage jitter |
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