CN102185305B - High Reliability Power Clamp ESD Protection Circuit - Google Patents

Abstract

The invention relates to the technical field of integrated circuit chip ESD (Electronic Static Discharge) protection, in particular to a high-reliability power supply clamping ESD protection circuit. The ESD protection circuit comprises a capacitor-resistor module (1), a clamping transistor open module (2), a clamping transistor (4) which are connected in sequence; the ESD protection circuit also comprises a clamping transistor close module (3) which is respectively connected with the capacitor-resistor module (1) and the clamping transistor (4). According to the invention, through separating a circuit structure used for controlling the open and close of the clamping transistor, the clamping transistor can obtain enough open time under the condition that of the capacitor-resistor module in the ESD protection circuit has very small time constant.

Description

High Reliability Power Clamp ESD Protection Circuit

technical field

The invention relates to the field of integrated circuit chip electrostatic discharge (Electronic Static Discharge, ESD) protection technology, in particular to a high-reliability power clamp ESD protection circuit.

Background technique

In the process of integrated circuit chip manufacturing, packaging, testing, transportation and use, there are many different electrostatic discharge modes. When these electrostatic charges accumulate on the gate of the MOS transistor, due to the small gate capacitance of the MOS transistor , These electrostatic charges will form a large equivalent gate voltage, resulting in the failure of the device or circuit, which is the ESD problem. Along with the scaling down of integrated circuit feature size, the gate oxide layer is made thinner and thinner, which makes ESD protection more difficult and important in nanometer-scale device and circuit design.

An integrated circuit chip is mainly connected with the outside world through input pins, output pins, power pins and ground pins, and the input and output pins usually have corresponding ESD protection circuit modules. The core function module of the chip is generally placed between the power pin and the ground pin. Therefore, a reliable power clamp ESD protection circuit is the key to ensure that the chip function module is not damaged by ESD. Existing power supply clamp ESD protection circuit is usually based on such an idea: use a resistance-capacitance (R-C) filter structure as the ESD detection circuit, when detecting ESD pulse, the filter structure provides a signal to open the clamp transistor, The ESD charge is then released by the clamp transistor.

Figure 1 shows a classic example of the current power supply clamp ESD protection circuit, Mbig in the figure is a clamp transistor. When a fast-rising ESD pulse comes, through the appropriate setting of the R-C time constant, the voltage at the intersection of R and C cannot be pulled up immediately following the power supply pin Vdd, so that the intersection of R and C is in the period before the ESD pulse comes It is at a low level for a certain period of time, and this low level is conducted to the gate of Mbig through a first-stage inverter, so that the gate of Mbig is at a high level, so Mbig is turned on to release the charge accumulated by the ESD pulse. When the R-C time constant has elapsed, the voltage at the intersection of R and C keeps up with the change of Vdd and becomes a high level. This high level is reversed to the gate of Mbig, so Mbig is turned off, ending the ESD protection process. In the case of normal power-on, the voltage of Vdd is pulled up at a relatively slow speed. At this time, the intersection of R and C has been following the voltage change of Vdd, so that Mbig is not turned on, and no extra power is consumed under normal working conditions. power consumption.

Although the circuit shown in Figure 1 is logically correct, the reliability of its ESD protection performance faces enormous challenges as the size of the device shrinks. The continuous reduction of the feature size of integrated circuits will inevitably require the R-C part of the ESD protection module to be as small as possible. Since the gate voltage of Mbig is pulled down after the R-C time constant has passed, the reduction of the R-C time constant will lead to a decrease in the turn-on time of Mbig. shortening, which may lead to incomplete release of ESD charges and damage to internal circuits. On the other hand, for the fast-rising normal power-on voltage, it is hoped that the clamping transistor will not be turned on, that is, the ESD protection circuit will not be triggered by mistake, so the ESD protection circuit with strong anti-false trigger capability also requires the R-C time constant to be made very small , which would also contradict the sufficiently long turn-on time of the clamp transistor.

Contents of the invention

(1) Technical problems to be solved

The technical problem to be solved by the invention is: how to make the clamping transistor have a sufficiently long turn-on time under the condition that the time constant of the capacitance-resistance module in the ESD protection circuit is very small.

(2) Technical solution

In order to solve the above technical problems, the present invention provides a high reliability power supply clamp ESD protection circuit, which is characterized in that it includes: a capacitor-resistor module connected in sequence, a clamp transistor opening module, and a clamp transistor, and also includes: The clamping transistor shutdown module is connected to the capacitor-resistor module and the clamping transistor respectively;

The capacitor-resistor module is used to identify whether the pulse of the power supply pin Vdd of the high-reliability power supply clamp ESD protection circuit is an electrostatic discharge pulse, and if so, send a first response signal to the clamp transistor opening module , sending a second response signal to the clamping transistor shutdown module after the time constant of the capacitor-resistor module has passed;

The clamping transistor enabling module is configured to activate the clamping transistor according to the first response signal;

The clamping transistor turn-off module is configured to turn off the clamping transistor according to the second response signal;

The clamping transistor is used for releasing the electrostatic charge brought by the electrostatic discharge pulse when starting.

Wherein, the capacitor-resistor module includes: a capacitor C1 and a resistor R1 connected in series, the capacitor C1 is connected to the power pin Vdd of the high-reliability power clamp ESD protection circuit, and the resistor R1 is grounded.

Wherein, the clamping transistor is an NMOS transistor Mbig1, the drain of the NMOS transistor Mbig1 is connected to the power supply pin Vdd of the high-reliability power supply clamping ESD protection circuit, and the source of the NMOS transistor Mbig1 is grounded.

Wherein, the clamping transistor opening module includes: PMOS transistors Mp1-1, Mp1-2, Mp2, and NMOS transistor Mn1, the gate of the PMOS transistor Mp1-1 is connected to the intersection of the capacitor C1 and the resistor R1, The source of the PMOS transistor Mp1-1 is connected to the drain and the gate of the PMOS transistor Mp1-2 respectively, and the source of the PMOS transistor Mp1-2 is connected to the high reliability power clamp ESD protection circuit. The power supply pin Vdd is connected, the drain of the PMOS transistor Mp1-1 is respectively connected to the drain of the NMOS transistor Mn1 and the gate of the PMOS transistor Mp2, and the gate of the NMOS transistor Mn1 is connected to the high reliability The power pin Vdd of the permanent power clamp ESD protection circuit is connected, the source of the NMOS transistor Mn1 is grounded, and the source of the PMOS transistor Mp2 is connected to the power pin Vdd of the high reliability power clamp ESD protection circuit. , the drain of the PMOS transistor Mp2 is connected to the gate of the NMOS transistor Mbig1.

Wherein, the clamping transistor turn-off module includes: PMOS transistors Mp3, Mp4, Mp5, NMOS transistors Mn3, Mn2, and capacitors C2, C3, the intersection of the gate of the PMOS transistor Mp4 and the capacitor C1 and resistor R1 connected, the source of the PMOS transistor Mp4 is connected to the power supply pin Vdd of the high-reliability power clamp ESD protection circuit, the drain of the PMOS transistor Mp4 is connected to one end of the capacitor C2, and the other end of the capacitor C2 One end is grounded, the intersection of the PMOS transistor Mp4 and the capacitor C2 is respectively connected to the gate of the PMOS transistor Mp3 and the gate of the NMOS transistor Mn3, and the drain of the PMOS transistor Mp3 is connected to the drain of the NMOS transistor Mn3 pole connection, the source of the PMOS transistor Mp3 is connected to the power supply pin Vdd of the high-reliability power clamp ESD protection circuit, the source of the NMOS transistor Mn3 is grounded, and the drain of the PMOS transistor Mp3 is connected to the NMOS The intersection point of the drain of the transistor Mn3 is connected with the gate of the PMOS transistor Mp5, and the source of the PMOS transistor Mp5 is connected with the power supply pin Vdd of the high-reliability power clamp ESD protection circuit, and the PMOS transistor Mp5 The drain of the capacitor C3 is connected to one end of the capacitor C3, the other end of the capacitor C3 is grounded, the intersection of the PMOS transistor Mp5 and the capacitor C3 is connected to the gate of the NMOS transistor Mn2, and the source of the NMOS transistor Mn2 grounded, and the drain of the NMOS transistor Mn2 is connected to the gate of the NMOS transistor Mbig1.

(3) Beneficial effects

The invention separates the circuit structure for controlling the turn-on and turn-off of the clamp transistor, so that the clamp transistor has a sufficiently long turn-on time when the time constant of the capacitor-resistance module in the ESD protection circuit is small.

Description of drawings

Fig. 1 is the specific circuit structure schematic diagram of traditional power supply clamp ESD protection circuit;

Fig. 2 is a schematic circuit diagram of a high-reliability power clamp ESD protection circuit according to an embodiment of the present invention;

Fig. 3 is the specific circuit structure diagram of the high-reliability power clamp ESD protection circuit shown in Fig. 2;

Fig. 4 is after adding an ESD pulse to the R-C of the power supply clamp ESD protection circuit of the prior art shown in Fig. 1 and adding an ESD pulse, the R-C obtained by Hspice simulation adds the schematic diagram of the voltage change of the output node of the inverter structure;

Figure 5 is a schematic diagram of the voltage change at the output node of the capacitor-resistor module obtained by Hspice simulation after applying an ESD pulse identical to that of Figure 4 to the capacitor-resistor module of the high-reliability power supply clamp ESD protection circuit shown in Figure 2;

6 is a schematic diagram of changes in the gate voltage of Mp1-1 and the gate voltage of Mp2 after the high-reliability power clamp ESD protection circuit shown in FIG. 2 applies an ESD pulse;

FIG. 7 is a schematic diagram of changes in the gate voltage of the clamp transistor after the traditional power supply clamp ESD protection circuit shown in FIG. 1 applies an ESD pulse;

FIG. 8 is a schematic diagram of changes in the gate voltage of the clamp transistor after an ESD pulse is applied by the high-reliability power supply clamp ESD protection circuit shown in FIG. 2 .

Detailed ways

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

The core idea of the present invention is: separate the circuit structure for controlling the opening and closing of the clamping transistor, so that the R and C sizes of the detection circuit part can be set from a small time constant to prevent false triggering, and a large time constant to prevent false triggering. Get out of the paradoxical choice of getting enough clamp transistor turn-on time. In the circuit proposed by the present invention, the C-R structure of the detection circuit basically only plays a decisive role in the opening of the clamping transistor, and the closing of the clamping transistor is controlled by the time delay of the C-R time constant plus the two-stage R-C, like this The control effect of the C-R time constant of the detection circuit on the turn-off of the clamp transistor can be weakened by enlarging the time delay of R-C in the clamp transistor turn-off circuit, thereby making a small space for the C-R time constant.

2 is a schematic circuit diagram of a high-reliability power supply clamp ESD protection circuit according to an embodiment of the present invention, including: a capacitor-resistor module 1, a clamp transistor opening module 2, and a clamp transistor 4 connected in sequence, and Including: a clamping transistor turn-off module 3, which is respectively connected to the capacitor-resistor module 1 and the clamping transistor 4;

The capacitor-resistor module 1 is used to identify whether the pulse of the power pin Vdd of the high-reliability power clamp ESD protection circuit is an electrostatic discharge pulse, and if so, send a first response signal to the clamp transistor to turn on Module 2, after the time constant of the capacitor-resistor module 1 passes, send a second response signal to the clamp transistor shutdown module 3;

The clamping transistor enabling module 2 is configured to activate the clamping transistor 4 according to the first response signal;

The clamping transistor turn-off module 3 is configured to turn off the clamping transistor 4 according to the second response signal;

The clamping transistor 4 is used for releasing the electrostatic charge brought by the electrostatic discharge pulse when starting.

As shown in Figure 3, the capacitor-resistor module 1 includes: a capacitor C1 and a resistor R1 connected in series, the capacitor C1 is connected to the power supply pin Vdd of the high-reliability power clamp ESD protection circuit, and the resistor R1 is grounded.

The clamping transistor 4 is an NMOS transistor Mbig1, the drain of the NMOS transistor Mbig1 is connected to the power supply pin Vdd of the high-reliability power supply clamping ESD protection circuit, and the source of the NMOS transistor Mbig1 is grounded.

The clamping transistor opening module 2 includes: PMOS transistors Mp1-1, Mp1-2, Mp2, and NMOS transistor Mn1, the gate of the PMOS transistor Mp1-1 is connected to the intersection of the capacitor C1 and the resistor R1, so The source of the PMOS transistor Mp1-1 is connected to the drain and the gate of the PMOS transistor Mp1-2 respectively, and the source of the PMOS transistor Mp1-2 is connected to the power supply of the high reliability power clamp ESD protection circuit The pin Vdd is connected, the drain of the PMOS transistor Mp1-1 is respectively connected to the drain of the NMOS transistor Mn1 and the gate of the PMOS transistor Mp2, and the gate of the NMOS transistor Mn1 is connected to the high reliability The power pin Vdd of the power clamp ESD protection circuit is connected, the source of the NMOS transistor Mn1 is grounded, the source of the PMOS transistor Mp2 is connected to the power pin Vdd of the high reliability power clamp ESD protection circuit, The drain of the PMOS transistor Mp2 is connected to the gate of the NMOS transistor Mbig1.

The clamp transistor turn-off module 3 includes: PMOS transistors Mp3, Mp4, Mp5, NMOS transistors Mn3, Mn2, and capacitors C2, C3, the gate of the PMOS transistor Mp4 is connected to the intersection of the capacitor C1 and the resistor R1 , the source of the PMOS transistor Mp4 is connected to the power supply pin Vdd of the high-reliability power clamp ESD protection circuit, the drain of the PMOS transistor Mp4 is connected to one end of the capacitor C2, and the other end of the capacitor C2 Grounded, the intersection of the PMOS transistor Mp4 and the capacitor C2 is respectively connected to the gate of the PMOS transistor Mp3 and the gate of the NMOS transistor Mn3, and the drain of the PMOS transistor Mp3 is connected to the drain of the NMOS transistor Mn3 connected, the source of the PMOS transistor Mp3 is connected to the power supply pin Vdd of the high-reliability power clamp ESD protection circuit, the source of the NMOS transistor Mn3 is grounded, and the drain of the PMOS transistor Mp3 is connected to the NMOS transistor The intersection point of the drain of Mn3 is connected with the gate of the PMOS transistor Mp5, and the source of the PMOS transistor Mp5 is connected with the power supply pin Vdd of the high-reliability power clamp ESD protection circuit, and the PMOS transistor Mp5 The drain is connected to one end of the capacitor C3, the other end of the capacitor C3 is grounded, the intersection of the PMOS transistor Mp5 and the capacitor C3 is connected to the gate of the NMOS transistor Mn2, and the source of the NMOS transistor Mn2 is grounded , the drain of the NMOS transistor Mn2 is connected to the gate of the NMOS transistor Mbig1.

The first improvement of the high-reliability power supply clamp ESD protection circuit of this embodiment compared with the traditional ESD protection circuit is that the capacitor-resistor (C-R) structure is used instead of the R-C plus inverter structure as the ESD pulse detection circuit. Logically, the output voltage curves of the R-C plus inverter structure and the C-R structure under the ESD pulse are basically the same. The difference between the two is that the output voltage of the R-C plus inverter structure under the ESD pulse has a relatively The falling slope is fast, while the output voltage of the C-R structure drops slowly. This is because traditional inverters have a logic threshold voltage. Ideally, the slope of the input-output voltage characteristic curve of an inverter near the logic threshold voltage is infinite. In practical applications, the slope will not be infinite, but it is also a relative The value is very large, and the drop speed of the output voltage of the C-R structure depends on the time constant of the C-R itself. In this way, under the same resistance and capacitance settings, the C-R structure reaches a specific low level later than the R-C plus inverter structure. Use Hspice for simulation. Figure 4 shows the schematic diagram of the voltage change of the output node (that is, the drain of Mp) of the R-C plus inverter structure under a specific ESD pulse. Figure 5 shows the capacitor-resistance module 1 Under the same resistor and capacitor settings as in Figure 4, a schematic diagram of the voltage change at the output node of capacitor-resistor module 1 (that is, the intersection of R1 and C1) when the same ESD pulse as in Figure 4 is applied. Comparing Figure 4 and Figure 5, the two drop It can be seen from the difference in slope that the capacitor-resistor module 1 of this embodiment makes the clamping transistor turn on time longer than that of the traditional ESD protection circuit.

The working principle of the high-reliability power supply clamp ESD protection circuit in this embodiment is: when an ESD pulse with a rise time of nanoseconds or tens of nanoseconds is applied to the power supply pin Vdd, the capacitor C1 and the resistor R1 The voltage at the intersection point will follow the power supply pin Vdd of the high-reliability power clamp ESD protection circuit in this embodiment and reach a high level value (that is, the above-mentioned first response signal), at this time, the PMOS transistor Mp1-1 is turned off, The gate of the PMOS transistor Mp2 is pulled down to a low level by the NMOS transistor Mn1, then the PMOS transistor Mp2 is turned on, and the gate voltage of the clamping transistor Mbig1 is pulled to a high level, the clamping transistor Mbig1 is started, and Mbig1 starts to discharge the electrostatic discharge Electrostatic charges from pulses.

Next, the voltage at the intersection of the capacitor C1 and the resistor R1 will drop with a slope determined by the C-R time constant. Ideally, the voltage at the intersection of the capacitor C1 and the resistor R1 will drop to Vdd-2|Vthp|, After that, Mp1-1 and Mp1-2 will be turned on, and the gate voltage of the PMOS transistor Mp2 will be pulled up, so that Mp2 will be turned off. In the case of ignoring the leakage current, the gate voltage of the clamping transistor Mbig1 will be suspended at the previous Vdd level, so Mbig1 will continue to turn on, wherein, Vthp represents the threshold voltage of the PMOS transistor.

When the voltage at the intersection of the capacitor C1 and the resistor R1 drops to Vdd−|Vthp| (that is, the second response signal), the PMOS transistor Mp4 enters an on state, and the drain voltage of Mp4 is pulled up. Since the PMOS transistor Mp4 and the capacitor C2 form an equivalent R-C delay structure, there is a corresponding R-C time delay in pulling up the drain voltage of Mp4. After this time delay, the drain voltage of Mp4 reaches a higher level, through the inverter composed of Mp3 and Mn3, the gate voltage of Mp5 becomes low level, and then Mp5 is turned on, passing through the inverter composed of Mp5 and capacitor C3 After a determined time delay, the gate voltage of Mn2 is pulled up to a high level, so that Mn2 is turned on, and the gate voltage of the clamping transistor Mbig1 is pulled down to turn it off, ending the action of releasing the ESD pulse.

During the period after Mp2 is turned off and before Mn2 is turned on, ideally, the gate voltage of the clamping transistor Mbig1 is suspended at the moment when Mp2 is turned off. In this embodiment, the high-reliability power supply clamps the power supply pin of the ESD protection circuit. Vdd state, thus avoiding the weakening of the Mbig1 discharge capability due to the voltage drop of the power supply pin Vdd of the high-reliability power supply clamping the ESD protection circuit in this embodiment during the process of Mbig1 releasing the ESD pulse.

It is worth noting that the inverter used in the clamp transistor turn-on module is different from the traditional inverter. This inverter has two functions for prolonging the turn-on time of Mbig: 1. Connect the gate to the power supply The transistor Mn1 of the pin Vdd is used as a current source, and Mn1 will always be in the conduction state, so even if Mp1-1 and Mp1-2 are fully turned on, the gate voltage of Mp2 cannot be completely pulled up to the power supply pin Vdd Equal high level, so Mp2 has a slightly stronger conductivity than that without Mn1 as a current source, so Mn2 needs more time to pull down the level of the gate of Mbig1 to below the threshold voltage of Mbig1, resulting in Mbig1 longer on time. 2. Use the transistor Mp1-2 with the gate and drain short-circuited as the load tube of Mp1-1, so that the turn-on condition of Mp1-1 becomes: the voltage at the intersection of the capacitor C1 and the resistor R1 drops to Vdd-2| Vthp|Later. Compared with the turn-on condition of Vdd-|Vthp| without Mp1-2 as the load tube, the intersection of the capacitor C1 and the resistor R1 naturally takes a longer time to reach a lower level, which also causes Mbig1 to turn on extension of time. Figure 6 shows the simulation results of Hspice. The gate voltage of Mp2 ("V2" in the figure) drops to about 360mV (with Vdd-2|Vthp| Approximately equal) began to pull up obviously, and the pull-up range of the gate voltage of Mp2 was about 665mV, instead of 1V (the amplitude of the ESD pulse applied here was 1V). Of course, in order for the above-mentioned improved inverter to realize the correct logic function, the relative size of the tubes is very important. Here, the size of Mn1 is much smaller than that of Mp1-1 and Mp1-2.

In the case of normal power-on, the power supply pin Vdd is pulled up with a slow slope, so that the charge accumulated in C1 can be released by R1 in time, so the intersection point of the capacitor C1 and the resistor R1 is always at a lower level. The level value makes the gate of Mp2 always in a high level state, so Mp2 is not turned on, so that the gate voltage of Mn2 cannot be pulled up. In this case, Mbig1 will not be triggered, ensuring the correct working logic.

In order to quantify the turn-on time of the clamp transistor, 0.7V is used as the threshold voltage of the clamp transistor. Figure 7 shows the gate voltage of the clamp transistor after an ESD pulse is applied to the traditional power supply clamp ESD protection circuit shown in Figure 1 Change schematic diagram; Figure 8 is a schematic diagram of the gate voltage change of the clamp transistor after the high-reliability power clamp ESD protection circuit shown in Figure 2 applies an ESD pulse; it can be seen that the traditional power clamp ESD shown in Figure 1 The turn-on time of the clamp transistor in the protection circuit is 64.8ns. The turn-on time of the clamp transistor in the high-reliability power supply clamp ESD protection circuit shown in Figure 2 is 608.9ns. Under the same capacitance and resistance and the same ESD pulse Through the high-reliability power supply clamp ESD protection circuit of this embodiment, the clamp transistor turn-on time of 9 times more than that of the traditional ESD protection circuit is obtained, which undoubtedly gives nanoscale circuit design greater control over the R and C time constants. With a small margin, the smaller the R and C time constants, the stronger the immunity of the circuit to the normal charging voltage of fast power-on, which just solves the problem of reliability of ESD protection performance at the nanometer scale mentioned above.

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.

Claims (4)

1. a high reliability power supply clamper esd protection circuit, it is characterized in that, comprise: the electric capacity-resistive module (1), clamp transistor opening module (2) and the clamp transistor (4) that connect successively, also comprise: clamp transistor turn-offs module (3), is connected respectively with described electric capacity-resistive module (1) with clamp transistor (4);

Described electric capacity-resistive module (1), for identifying whether the pulse of the power pin Vdd of described high reliability power supply clamper esd protection circuit is electrostatic discharge pulses, if, send the first response signal to described clamp transistor opening module (2), after the time constant through described electric capacity-resistive module (1), send the second response signal to described clamp transistor and turn-off module (3);

Described clamp transistor opening module (2), for starting described clamp transistor (4) according to described the first response signal;

Described clamp transistor turn-offs module (3), for turn-offing described clamp transistor (4) according to described the second response signal;

Described clamp transistor (4), for when starting, discharges the electrostatic charge that described electrostatic discharge pulses is brought;

Described clamp transistor opening module (2) comprising: PMOS transistor Mp1-1, Mp1-2, Mp2, and nmos pass transistor Mn1, the grid of described PMOS transistor Mp1-1 is connected with the tie point of resistance R 1 with capacitor C 1, the source electrode of described PMOS transistor Mp1-1 is connected respectively with the drain and gate of described PMOS transistor Mp1-2, the source electrode of described PMOS transistor Mp1-2 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp1-1 is connected with the grid of described PMOS transistor Mp2 with the drain electrode of described nmos pass transistor Mn1 respectively, the grid of described nmos pass transistor Mn1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mn1, the source electrode of described PMOS transistor Mp2 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp2 is connected with the grid of nmos pass transistor Mbig1.

2. high reliability power supply clamper esd protection circuit as claimed in claim 1; it is characterized in that; described electric capacity-resistive module (1) comprising: the capacitor C 1 being connected in series and resistance R 1; described capacitor C 1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, described resistance R 1 ground connection.

3. high reliability power supply clamper esd protection circuit as claimed in claim 2; it is characterized in that; described clamp transistor (4) is nmos pass transistor Mbig1; the drain electrode of described nmos pass transistor Mbig1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mbig1.

4. high reliability power supply clamper esd protection circuit as claimed in claim 1, it is characterized in that, described clamp transistor turn-offs module (3) and comprising: PMOS transistor Mp3, Mp4, Mp5, nmos pass transistor Mn3, Mn2, and capacitor C 2, C3, the grid of described PMOS transistor Mp4 is connected with the tie point of resistance R 1 with described capacitor C 1, the source electrode of described PMOS transistor Mp4 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp4 is connected with one end of capacitor C 2, the other end ground connection of described capacitor C 2, described PMOS transistor Mp4 is connected with the grid of described nmos pass transistor Mn3 with the grid of described PMOS transistor Mp3 respectively with the tie point of capacitor C 2, the drain electrode of described PMOS transistor Mp3 is connected with the drain electrode of described nmos pass transistor Mn3, the source electrode of described PMOS transistor Mp3 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mn3, the drain electrode of described PMOS transistor Mp3 is connected with the grid of described PMOS transistor Mp5 with the tie point of the drain electrode of nmos pass transistor Mn3, the source electrode of described PMOS transistor Mp5 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp5 is connected with one end of described capacitor C 3, the other end ground connection of described capacitor C 3, described PMOS transistor Mp5 is connected with the grid of described nmos pass transistor Mn2 with the tie point of capacitor C 3, the source ground of described nmos pass transistor Mn2, the drain electrode of described nmos pass transistor Mn2 is connected with the grid of described nmos pass transistor Mbig1.

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