CN102185305B - High-reliability power supply clamping ESD (Electronic Static Discharge) protection circuit - Google Patents
High-reliability power supply clamping ESD (Electronic Static Discharge) protection circuit Download PDFInfo
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- CN102185305B CN102185305B CN201110129544.4A CN201110129544A CN102185305B CN 102185305 B CN102185305 B CN 102185305B CN 201110129544 A CN201110129544 A CN 201110129544A CN 102185305 B CN102185305 B CN 102185305B
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Abstract
The invention relates to the technical field of integrated circuit chip ESD (Electronic Static Discharge) protection, in particular to a high-reliability power supply clamping ESD protection circuit. The ESD protection circuit comprises a capacitor-resistor module (1), a clamping transistor open module (2), a clamping transistor (4) which are connected in sequence; the ESD protection circuit also comprises a clamping transistor close module (3) which is respectively connected with the capacitor-resistor module (1) and the clamping transistor (4). According to the invention, through separating a circuit structure used for controlling the open and close of the clamping transistor, the clamping transistor can obtain enough open time under the condition that of the capacitor-resistor module in the ESD protection circuit has very small time constant.
Description
Technical field
The present invention relates to integrated circuit (IC) chip static discharge (Electronic Static Discharge, ESD) resist technology field, particularly a kind of high reliability power supply clamper esd protection circuit.
Background technology
Among the process of integrated circuit (IC) chip manufacture, encapsulation, test, transportation and use, exist multiple different static discharge pattern, when these electrostatic charges are accumulated on the grid of MOS transistor, because the gate capacitance of MOS transistor is very little, these electrostatic charges can form very large equivalent grid voltage, cause the inefficacy of device or circuit, this is ESD problem.Be accompanied by the scaled rule of integrated circuit characteristic size, gate oxide is done more and more thinlyyer, has caused like this esd protection problem difficulty all the more and important that becomes among the device of nanoscale and circuit design.
The chip of integrated circuit is mainly associated with the external world by input pin, output pin, power pin and ground pin, and input and output pin has corresponding esd protection circuit module conventionally.The corn module of chip generally can be placed between power pin and ground pin, so a reliable power supply clamper esd protection circuit is to guarantee that chip functions module is not subject to the key of ESD damage.Existing power supply clamper esd protection circuit is normally based on such thinking: with a resistance-capacitance (R-C) filter structure as ESD detection circuit; when detecting esd pulse; filter structure provides a signal and opens clamp transistor, then by clamp transistor, discharges ESD electric charge.
A classical example that Figure 1 shows that current power supply clamper esd protection circuit, the Mbig in figure is clamp transistor.When a zooming esd pulse arrives, by the setting of suitable R-C time constant, the voltage of the intersection point of R and C cannot be followed on power pin Vdd immediately to be drawn, be low level the last period that the intersection point of R and C arrives at esd pulse like this in special time, this low level is transmitted to the grid of Mbig by one-level inverter, the grid that makes Mbig is high level, so Mbig is opened to discharge the electric charge of esd pulse accumulation.When R-C time constant was after the past, the voltage of the intersection point of R and C has been caught up with the variation of Vdd and has been become high level, and this high level is inverted to the grid of Mbig, so Mbig is turned off, finishes esd protection process.In the situation that normally powering on, the voltage of Vdd is with a relatively slow velocity pull-up, and at this moment the intersection point of R and C is followed the change in voltage of Vdd always, and Mbig is not opened, and does not consume extra power supply power consumption in the situation that of normal operation.
Although the circuit shown in Fig. 1 is no problem from seeing in logic, along with dwindling of device size, the reliability of its esd protection performance faces huge challenge.The R-C part of constantly dwindling inevitable requirement esd protection module of integrated circuit characteristic size will be done little as far as possible; because the grid voltage of Mbig is just dragged down in the past in R-C time constant; the reducing of R-C time constant will cause Mbig open-interval to shorten, thereby so likely causes ESD electric charge to discharge the incomplete damage that causes internal circuit.Another one aspect; for zooming normal upper piezoelectric voltage; wish that clamp transistor is not opened; be that esd protection circuit is not by false triggering; the esd protection circuit that so anti-error triggering ability is strong also requires a R-C time constant to do very littlely, and this can contradict with the sufficiently long opening time of clamp transistor equally.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is: how in the situation that in esd protection circuit the time constant of electric capacity-resistive module very little, make clamp transistor have the sufficiently long opening time.
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of high reliability power supply clamper esd protection circuit, it is characterized in that, comprise: the electric capacity-resistive module, clamp transistor opening module and the clamp transistor that connect successively, also comprise: clamp transistor turn-offs module, is connected respectively with described electric capacity-resistive module with clamp transistor;
Described electric capacity-resistive module, for identifying whether the pulse of the power pin Vdd of described high reliability power supply clamper esd protection circuit is electrostatic discharge pulses, if, send the first response signal to described clamp transistor opening module, after the time constant through described electric capacity-resistive module, send the second response signal to described clamp transistor and turn-off module;
Described clamp transistor opening module, for starting described clamp transistor according to described the first response signal;
Described clamp transistor turn-offs module, for turn-offing described clamp transistor according to described the second response signal;
Described clamp transistor, for when starting, discharges the electrostatic charge that described electrostatic discharge pulses is brought.
Wherein, described electric capacity-resistive module comprises: the capacitor C 1 being connected in series and resistance R 1, described capacitor C 1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, described resistance R 1 ground connection.
Wherein, described clamp transistor is nmos pass transistor Mbig1, and the drain electrode of described nmos pass transistor Mbig1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mbig1.
Wherein, described clamp transistor opening module comprises: PMOS transistor Mp1-1, Mp1-2, Mp2, and nmos pass transistor Mn1, the grid of described PMOS transistor Mp1-1 is connected with the intersection point of resistance R 1 with described capacitor C 1, the source electrode of described PMOS transistor Mp1-1 is connected respectively with the drain and gate of described PMOS transistor Mp1-2, the source electrode of described PMOS transistor Mp1-2 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp1-1 is connected with the grid of described PMOS transistor Mp2 with the drain electrode of described nmos pass transistor Mn1 respectively, the grid of described nmos pass transistor Mn1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mn1, the source electrode of described PMOS transistor Mp2 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp2 is connected with the grid of described nmos pass transistor Mbig1.
Wherein, described clamp transistor turn-offs module and comprises: PMOS transistor Mp3, Mp4, Mp5, nmos pass transistor Mn3, Mn2, and capacitor C 2, C3, the grid of described PMOS transistor Mp4 is connected with the intersection point of resistance R 1 with described capacitor C 1, the source electrode of described PMOS transistor Mp4 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp4 is connected with one end of capacitor C 2, the other end ground connection of described capacitor C 2, described PMOS transistor Mp4 is connected with the grid of described nmos pass transistor Mn3 with the grid of described PMOS transistor Mp3 respectively with the intersection point of capacitor C 2, the drain electrode of described PMOS transistor Mp3 is connected with the drain electrode of described nmos pass transistor Mn3, the source electrode of described PMOS transistor Mp3 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mn3, the drain electrode of described PMOS transistor Mp3 is connected with the grid of described PMOS transistor Mp5 with the intersection point of the drain electrode of nmos pass transistor Mn3, the source electrode of described PMOS transistor Mp5 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp5 is connected with one end of described capacitor C 3, the other end ground connection of described capacitor C 3, described PMOS transistor Mp5 is connected with the grid of described nmos pass transistor Mn2 with the intersection point of capacitor C 3, the source ground of described nmos pass transistor Mn2, the drain electrode of described nmos pass transistor Mn2 is connected with the grid of described nmos pass transistor Mbig1.
(3) beneficial effect
The present invention is by controlling circuit structure that clamp transistor opens and turn-off separately, make in the situation that in esd protection circuit the time constant of electric capacity-resistive module very little, clamp transistor has the sufficiently long opening time.
Accompanying drawing explanation
Fig. 1 is the particular circuit configurations schematic diagram of traditional power supply clamper esd protection circuit;
Fig. 2 is according to the circuit theory diagrams of the high reliability power supply clamper esd protection circuit of one embodiment of the present invention;
Fig. 3 is the particular circuit configurations figure of the high reliability power supply clamper esd protection circuit shown in Fig. 2;
Fig. 4 adds after inverter structure applies an esd pulse the R-C of the power supply clamper esd protection circuit of the prior art shown in Fig. 1, and the resulting R-C of Hspice emulation adds the change in voltage schematic diagram of inverter structure output node;
Fig. 5 applies after an esd pulse identical with Fig. 4 the electric capacity-resistive module of the high reliability power supply clamper esd protection circuit shown in Fig. 2, the change in voltage schematic diagram of the resulting electric capacity-resistive module of Hspice emulation output node;
Fig. 6 is that the high reliability power supply clamper esd protection circuit shown in Fig. 2 applies after an esd pulse, and the grid voltage of Mp1-1 and the grid voltage of Mp2 change schematic diagram;
Fig. 7 is that the traditional power supply clamper esd protection circuit shown in Fig. 1 applies after an esd pulse, and the grid voltage of clamp transistor changes schematic diagram;
Fig. 8 is that the high reliability power supply clamper esd protection circuit shown in Fig. 2 applies after an esd pulse, and the grid voltage of clamp transistor changes schematic diagram.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.
Core concept of the present invention is: controlling, clamp transistor is opened and the circuit structure of shutoff separates, like this R, the C of detection circuit part size just arrange can be from doing little time constant in case false triggering, do again large time constant and among the selection of enough such contradiction of clamp transistor opening time, spin off obtaining.In the circuit proposing in the present invention, the C-R structure of detection circuit only plays a decisive role to the unlatching of clamp transistor substantially, the shutoff of clamp transistor adds that by C-R time constant the time delay of two-stage R-C controls, so just can weaken the control action that detection circuit C-R time constant is turn-offed clamp transistor by doing the time delay of R-C in large clamp transistor breaking circuit, thereby do little space to C-R time constant.
Fig. 2 is according to the circuit theory diagrams of the high reliability power supply clamper esd protection circuit of one embodiment of the present invention, comprise: the electric capacity-resistive module 1, clamp transistor opening module 2 and the clamp transistor 4 that connect successively, also comprise: clamp transistor turn-offs module 3, is connected respectively with described electric capacity-resistive module 1 with clamp transistor 4;
Described electric capacity-resistive module 1, for identifying whether the pulse of the power pin Vdd of described high reliability power supply clamper esd protection circuit is electrostatic discharge pulses, if, send the first response signal to described clamp transistor opening module 2, after the time constant through described electric capacity-resistive module 1, send the second response signal to described clamp transistor and turn-off module 3;
Described clamp transistor opening module 2, for starting described clamp transistor 4 according to described the first response signal;
Described clamp transistor turn-offs module 3, for turn-offing described clamp transistor 4 according to described the second response signal;
Described clamp transistor 4, for when starting, discharges the electrostatic charge that described electrostatic discharge pulses is brought.
As shown in Figure 3, described electric capacity-resistive module 1 comprises: the capacitor C 1 being connected in series and resistance R 1, described capacitor C 1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, described resistance R 1 ground connection.
Described clamp transistor 4 is nmos pass transistor Mbig1, and the drain electrode of described nmos pass transistor Mbig1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mbig1.
Described clamp transistor opening module 2 comprises: PMOS transistor Mp1-1, Mp1-2, Mp2, and nmos pass transistor Mn1, the grid of described PMOS transistor Mp1-1 is connected with the intersection point of resistance R 1 with described capacitor C 1, the source electrode of described PMOS transistor Mp1-1 is connected respectively with the drain and gate of described PMOS transistor Mp1-2, the source electrode of described PMOS transistor Mp1-2 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp1-1 is connected with the grid of described PMOS transistor Mp2 with the drain electrode of described nmos pass transistor Mn1 respectively, the grid of described nmos pass transistor Mn1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mn1, the source electrode of described PMOS transistor Mp2 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp2 is connected with the grid of described nmos pass transistor Mbig1.
Described clamp transistor turn-offs module 3 and comprises: PMOS transistor Mp3, Mp4, Mp5, nmos pass transistor Mn3, Mn2, and capacitor C 2, C3, the grid of described PMOS transistor Mp4 is connected with the intersection point of resistance R 1 with described capacitor C 1, the source electrode of described PMOS transistor Mp4 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp4 is connected with one end of capacitor C 2, the other end ground connection of described capacitor C 2, described PMOS transistor Mp4 is connected with the grid of described nmos pass transistor Mn3 with the grid of described PMOS transistor Mp3 respectively with the intersection point of capacitor C 2, the drain electrode of described PMOS transistor Mp3 is connected with the drain electrode of described nmos pass transistor Mn3, the source electrode of described PMOS transistor Mp3 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mn3, the drain electrode of described PMOS transistor Mp3 is connected with the grid of described PMOS transistor Mp5 with the intersection point of the drain electrode of nmos pass transistor Mn3, the source electrode of described PMOS transistor Mp5 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp5 is connected with one end of described capacitor C 3, the other end ground connection of described capacitor C 3, described PMOS transistor Mp5 is connected with the grid of described nmos pass transistor Mn2 with the intersection point of capacitor C 3, the source ground of described nmos pass transistor Mn2, the drain electrode of described nmos pass transistor Mn2 is connected with the grid of described nmos pass transistor Mbig1.
The high reliability power supply clamper esd protection circuit of present embodiment uses electric capacity-resistance (C-R) structure to replace R-C to add inverter structure as the detection circuit of esd pulse with respect to first improvements of traditional E SD protective circuit exactly.From in logic, it is substantially the same that R-C adds the voltage curve variation tendency that inverter structure exports under esd pulse with C-R structure, the difference of the two is that R-C adds the voltage that inverter structure exports under esd pulse and has a descending slope faster, and the voltage of C-R structure output declines comparatively slow.This is because traditional inverter all exists a logic threshold voltage, ideally, near logic threshold voltage, the input-output voltage response slope of inverter is infinitely great, in practical application, slope can not be infinitely great, but be also a relative very large value, the decline speed of C-R structure output voltage depends on the time constant of C-R self.Like this under identical resistance, capacitance size arrange, C-R structure just adds than R-C that inverter structure is more late reaches a specific low level.With Hspice, carry out emulation, Figure 4 shows that R-C adds the change in voltage schematic diagram that inverter structure R-C under a specific esd pulse adds inverter structure output node (being the drain electrode of Mp), Fig. 5 is the resistance that electric capacity-resistive module 1 is identical with Fig. 4 size, electric capacity arranges down, the change in voltage schematic diagram of electric capacity-resistive module 1 output node while applying the esd pulse identical with Fig. 4 (R1 and C1 intersection point), comparison diagram 4 and Fig. 5, the difference of the two descending slope is known, electric capacity-the resistive module 1 of present embodiment makes the clamp transistor opening time longer than traditional E SD protective circuit.
The operation principle of the high reliability power supply clamper esd protection circuit of present embodiment is: when the esd pulse that is nanosecond or tens of nanosecond orders when a rise time is added to power pin Vdd, the power pin Vdd that the voltage of the intersection point of described capacitor C 1 and resistance R 1 can be followed high reliability power supply clamper esd protection circuit in present embodiment comparatively fast reaches a high value (being above-mentioned the first response signal), at this moment PMOS transistor Mp1-1 turn-offs, the grid of PMOS transistor Mp2 is pulled down to low level by nmos pass transistor Mn1, then PMOS transistor Mp2 opens, the grid voltage of clamp transistor Mbig1 is moved to high level, clamp transistor Mbig1 starts, Mbig1 starts to discharge the electrostatic charge that described electrostatic discharge pulses is brought.
Next the voltage of the intersection point of described capacitor C 1 and resistance R 1 can decline with a slope being determined by C-R time constant, under ideal situation, the voltage drop of the intersection point of described capacitor C 1 and resistance R 1 is to Vdd-2|Vthp|, afterwards, Mp1-1 and Mp1-2 will open, drawing on the grid voltage of PMOS transistor Mp2, Mp2 is turn-offed, in the situation that ignoring leakage current, now the gate voltage of clamp transistor Mbig1 can be suspended in previous Vdd level, therefore Mbig1 can continue to open, wherein, Vthp represents the transistorized threshold voltage of PMOS.
At the voltage drop of the intersection point of described capacitor C 1 and resistance R 1, during to Vdd-|Vthp| (being above-mentioned the second response signal), PMOS transistor Mp4 enters opening, and the drain voltage of Mp4 is drawn high.Because PMOS transistor Mp4 and capacitor C 2 have formed an equivalent R-C delay structure, thus the drain voltage of Mp4 on draw and have a corresponding R-C time delay.After this time delay, the drain voltage of Mp4 reaches a higher level, the inverter consisting of Mp3 and Mn3, makes the grid voltage of Mp5 become low level, then Mp5 conducting, through the time delay being determined by Mp5 and capacitor C 3, the grid voltage of Mn2 by draw as high level, Mn2 conducting like this, drags down the grid voltage of clamp transistor Mbig1, it is turn-offed, finish to discharge the action of esd pulse.
Before opening with Mn2 after Mp2 turn-offs during this period of time in; in the ideal case; the grid voltage of clamp transistor Mbig1 is suspended in the state that Mp2 turn-offs the power pin Vdd of high reliability power supply clamper esd protection circuit in present embodiment constantly, has so just avoided the phenomenon weakening due to Mbig1 relieving capacity that in Mbig1 release esd pulse process, the power pin Vdd voltage drop of high reliability power supply clamper esd protection circuit causes in present embodiment.
Be worth explanation a bit: the inverter that use clamp transistor opening module the inside and conventional inverter be difference to some extent, this inverter has the effect of two aspects for the opening time that extends Mbig: one, the transistor Mn1 that meets power pin Vdd with grid makes a current source, Mn1 can be always in conducting state, even if Mp1-1 and Mp1-2 open completely like this, also the grid voltage of Mp2 cannot be moved to the high level equating with power pin Vdd on completely, so Mp2 is just than not having Mn1 to do there is slightly strong conductive capability in the situation of current source, so Mn2 needs the more time level of the grid of Mbig1 could be pulled down to below the threshold voltage of Mbig1, cause the longer opening time of Mbig1.Two, the load pipe of making Mp1-1 with the transistor Mp1-2 of grid and drain electrode short circuit, becomes the unlocking condition of Mp1-1: the voltage drop of the intersection point of described capacitor C 1 and resistance R 1 is after Vdd-2|Vthp|.Compare in make the unlocking condition of Vdd-|Vthp| under load pipe without Mp1-2, the intersection point of described capacitor C 1 and resistance R 1 needs a longer time reach a lower level naturally, so also cause Mbig1 open-interval to extend.Fig. 6 is the simulation result of Hspice, the grid voltage of Mp2 (" V2 " in figure) is that the grid voltage (" V1 " in figure) at Mp1-1 drops to about 360mV (with Vdd-2|Vthp| approximately equal) and just starts on obvious to draw, on the grid voltage of Mp2, tentering degree is 665mV left and right simultaneously, rather than 1V (amplitude of the esd pulse that applies is 1V here).Certainly, want the above-mentioned inverter having improved and realize correct logic function, the relative size of pipe is very important, and the size of Mn1 arranges little much than the size of Mp1-1 and Mp1-2 here.
In situation about normally powering on, power pin Vdd with a slower slope by draw, the electric charge of C1 accumulation can be discharged timely by R1 like this, so the intersection point of described capacitor C 1 and resistance R 1, always in a lower level value, makes the grid of Mp2 all the time in high level state, so not conducting of Mp2, make Mn2 grid voltage cannot on draw, in this case, Mbig1 can not be triggered, and has guaranteed correct work-based logic.
For the ease of quantizing the opening time of clamp transistor, using 0.7V as the threshold voltage of clamp transistor, Fig. 7 is that the traditional power supply clamper esd protection circuit shown in Fig. 1 applies after an esd pulse, the grid voltage of clamp transistor changes schematic diagram, Fig. 8 is that the high reliability power supply clamper esd protection circuit shown in Fig. 2 applies after an esd pulse, and the grid voltage of clamp transistor changes schematic diagram, can find out in the traditional power supply clamper esd protection circuit shown in Fig. 1 that the clamp transistor opening time is 64.8ns, in high reliability power supply clamper esd protection circuit shown in Fig. 2, the circuit clamp transistor opening time is 608.9ns, under onesize electric capacity and resistance and same esd pulse, high reliability power supply clamper esd protection circuit by present embodiment has obtained 9 times of clamp transistor opening times more than traditional E SD protective circuit, this given undoubtedly the design of nanoscale circuit larger R, C time constant is done little nargin, R, C time constant is done littlely, circuit for fast powering-up to charge normal voltage immunocompetence just stronger, this has just in time solved the problem of esd protection performance reliability under above-mentioned nanoscale.
Above execution mode is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (4)
1. a high reliability power supply clamper esd protection circuit, it is characterized in that, comprise: the electric capacity-resistive module (1), clamp transistor opening module (2) and the clamp transistor (4) that connect successively, also comprise: clamp transistor turn-offs module (3), is connected respectively with described electric capacity-resistive module (1) with clamp transistor (4);
Described electric capacity-resistive module (1), for identifying whether the pulse of the power pin Vdd of described high reliability power supply clamper esd protection circuit is electrostatic discharge pulses, if, send the first response signal to described clamp transistor opening module (2), after the time constant through described electric capacity-resistive module (1), send the second response signal to described clamp transistor and turn-off module (3);
Described clamp transistor opening module (2), for starting described clamp transistor (4) according to described the first response signal;
Described clamp transistor turn-offs module (3), for turn-offing described clamp transistor (4) according to described the second response signal;
Described clamp transistor (4), for when starting, discharges the electrostatic charge that described electrostatic discharge pulses is brought;
Described clamp transistor opening module (2) comprising: PMOS transistor Mp1-1, Mp1-2, Mp2, and nmos pass transistor Mn1, the grid of described PMOS transistor Mp1-1 is connected with the tie point of resistance R 1 with capacitor C 1, the source electrode of described PMOS transistor Mp1-1 is connected respectively with the drain and gate of described PMOS transistor Mp1-2, the source electrode of described PMOS transistor Mp1-2 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp1-1 is connected with the grid of described PMOS transistor Mp2 with the drain electrode of described nmos pass transistor Mn1 respectively, the grid of described nmos pass transistor Mn1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mn1, the source electrode of described PMOS transistor Mp2 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp2 is connected with the grid of nmos pass transistor Mbig1.
2. high reliability power supply clamper esd protection circuit as claimed in claim 1; it is characterized in that; described electric capacity-resistive module (1) comprising: the capacitor C 1 being connected in series and resistance R 1; described capacitor C 1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, described resistance R 1 ground connection.
3. high reliability power supply clamper esd protection circuit as claimed in claim 2; it is characterized in that; described clamp transistor (4) is nmos pass transistor Mbig1; the drain electrode of described nmos pass transistor Mbig1 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mbig1.
4. high reliability power supply clamper esd protection circuit as claimed in claim 1, it is characterized in that, described clamp transistor turn-offs module (3) and comprising: PMOS transistor Mp3, Mp4, Mp5, nmos pass transistor Mn3, Mn2, and capacitor C 2, C3, the grid of described PMOS transistor Mp4 is connected with the tie point of resistance R 1 with described capacitor C 1, the source electrode of described PMOS transistor Mp4 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp4 is connected with one end of capacitor C 2, the other end ground connection of described capacitor C 2, described PMOS transistor Mp4 is connected with the grid of described nmos pass transistor Mn3 with the grid of described PMOS transistor Mp3 respectively with the tie point of capacitor C 2, the drain electrode of described PMOS transistor Mp3 is connected with the drain electrode of described nmos pass transistor Mn3, the source electrode of described PMOS transistor Mp3 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the source ground of described nmos pass transistor Mn3, the drain electrode of described PMOS transistor Mp3 is connected with the grid of described PMOS transistor Mp5 with the tie point of the drain electrode of nmos pass transistor Mn3, the source electrode of described PMOS transistor Mp5 is connected with the power pin Vdd of described high reliability power supply clamper esd protection circuit, the drain electrode of described PMOS transistor Mp5 is connected with one end of described capacitor C 3, the other end ground connection of described capacitor C 3, described PMOS transistor Mp5 is connected with the grid of described nmos pass transistor Mn2 with the tie point of capacitor C 3, the source ground of described nmos pass transistor Mn2, the drain electrode of described nmos pass transistor Mn2 is connected with the grid of described nmos pass transistor Mbig1.
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| CN103001205A (en) * | 2012-11-02 | 2013-03-27 | 长沙景嘉微电子股份有限公司 | Electrostatic protection circuit applied to power supply pin |
| CN103001200B (en) * | 2012-12-14 | 2015-04-22 | 北京大学 | Multiple RC triggered power supply clamp electro-static discharge (ESD) protective circuit |
| CN103078305B (en) * | 2013-01-09 | 2015-02-04 | 北京大学 | Anti-false-triggering power supply clamp ESD (Electro-Static Discharge) protection circuit |
| CN105680433B (en) * | 2016-03-24 | 2018-01-26 | 北京大学 | A kind of ESD power clamps protection circuit |
| CN109752612B (en) * | 2018-12-29 | 2021-03-16 | 西安紫光国芯半导体有限公司 | Simulation circuit and method of chip ESD protection circuit |
| CN110912098B (en) * | 2019-11-25 | 2021-08-24 | 南京尔芯电子有限公司 | Circuit for preventing electrostatic discharge ESD protection from causing leakage current under power-off |
| CN112104044B (en) * | 2020-09-22 | 2021-12-24 | 中国科学院微电子研究所 | Off-chip high-voltage isolation circuit applied to quick charging interface |
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| US5978192A (en) * | 1997-11-05 | 1999-11-02 | Harris Corporation | Schmitt trigger-configured ESD protection circuit |
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| US7102864B2 (en) * | 2004-06-14 | 2006-09-05 | King Billion Electronics Co., Ltd. | Latch-up-free ESD protection circuit using SCR |
| WO2009023099A2 (en) * | 2007-08-10 | 2009-02-19 | Skyworks Solutions, Inc. | Power clamp for on-chip esd protection |
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2011
- 2011-05-18 CN CN201110129544.4A patent/CN102185305B/en active Active
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| US5978192A (en) * | 1997-11-05 | 1999-11-02 | Harris Corporation | Schmitt trigger-configured ESD protection circuit |
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| CN102185305A (en) | 2011-09-14 |
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