CN103107528B - Power clamping electrostatic discharge protection circuit - Google Patents
Power clamping electrostatic discharge protection circuit Download PDFInfo
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- CN103107528B CN103107528B CN201210576053.9A CN201210576053A CN103107528B CN 103107528 B CN103107528 B CN 103107528B CN 201210576053 A CN201210576053 A CN 201210576053A CN 103107528 B CN103107528 B CN 103107528B
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Abstract
The invention provides a power clamping electrostatic discharge protection circuit which comprises a power pin, a grounding pin, a decision circuit (310), a time-delay circuit (320), a trigger circuit (330) and a clamping circuit (340), wherein the decision circuit (310) is used for sensing of an electrostatic discharge voltage, the time-delay circuit (320) is used for recording and storing a sensed electrostatic discharge voltage signal so as to provide time delay, the trigger circuit (330) is used for converting the electrostatic discharge voltage signal stored by the time-delay circuit (320) to an electrostatic discharge trigger signal, and the clamping circuit (340) is used for bleeding electrostatic current after the electrostatic discharge trigger signal is received. The decision circuit and the time-delay circuit are separated, the probability of clamping circuit false triggering caused by rapid electrifying is avoided, and meanwhile, a longer starting time for the clamping circuit can be obtained when electrostatic discharge impact occurs, and the reliability of electrostatic discharge protection is improved.
Description
Technical field
The present invention relates to integrated circuit (IC) chip static discharge (Electronic Static Discharge, ESD) resist technology field, the power supply clamper esd protection circuit that particularly a kind of identifying unit and delay unit separate.
Background technology
Along with constantly dwindling of integrated circuit technology characteristic size, the antistatic relieving capacity of chip has become the key factor that ensures internal circuit reliably working.Electrostatic leakage phenomenon refer to when two with not iso-electric object near or when contact, between the two, there is the transient process that electrostatic charge shifts.Under advanced integrated circuit technology level, the gate oxide of device is very thin, and its equivalent gate oxide electric capacity is very little, in the time that electrostatic charge is accumulated on gate oxide, can form very large equivalent grid voltage, causes the inefficacy of device or circuit.For integrated circuit (IC) chip, electrostatic impact has different patterns, and correspondence also has different protective circuits.Power pin to ground pin or I/O pin to the conflicting model of I/O pin under, the electrostatic charge inner function circuit module of can flowing through, causes the damage of internal circuit.Power supply clamper esd protection circuit is mainly for above-mentioned two kinds of conflicting models, is impacting temporarily, provides an effective electrostatic charge to discharge path to chip, ensures the damage that chip internal functional circuit is not hit.
The design of existing power supply clamper esd protection circuit need to meet following condition: impact temporarily at ESD, provide a useful signal by electric capacity-resistance or the resistance-capacitance module of protective circuit, open clamp transistor with discharge electrostatic charges.Charging normal voltage temporarily, clamp transistor requires not to be opened.
Power supply fast powering-up faces the challenge power supply clamper esd protection circuit: in order to prevent the false triggering of clamper ESD circuit, need the time constant of electric capacity-resistance or resistance-capacitance module as far as possible little; But too little time constant can not ensure that clamp transistor has enough opening times under ESD impacts.
Figure 1 shows that a kind of power supply clamper esd protection circuit of prior art; its operation principle is as follows: in the time that an esd pulse is applied to power pin VDD; on the voltage of Node B, draw the voltage levvl into VDD pin; through two-stage inverter; the grid voltage of clamp transistor 1 is pulled to the voltage levvl of power pin VDD; then clamp transistor 1 starts, and starts to discharge ESD and impacts the electrostatic charge accumulating.By the time after the time constant past being coupled by resistance R 1 and capacitor C 1, the voltage of Node B becomes logic low, and through two-stage inverter, the grid voltage of clamp transistor 1 is pulled down to the voltage levvl of ground pin, finishes esd protection process.
When the charging voltage normally powering on is applied to power pin VDD, the voltage of Node B can maintain the voltage levvl of ground pin, through two-stage inverter, clamp transistor 1 grid voltage, all the time in low level state, has ensured that clamp transistor 1 is not triggered in the time normally powering on.
The problem of prior art is as shown in Figure 1: capacitor C 1 and resistance R 1 have been born the task of judgement and time delay simultaneously.For example, in order to obtain enough ESD open time delays (500ns), must there be enough large capacitor C 1 and resistance R 1, but, so for example, when power supply generation fast powering-up (100ns rise time), through resistance R 1, the charging of capacitor C 1 will not caught up with to variation, now, will cause the false triggering of clamp transistor 1.
Summary of the invention
For addressing the above problem; the invention provides a kind of power supply clamper ESD protection circuit; this protective circuit is separated decision circuitry and delay circuit; the clamp circuit false triggering of having avoided fast powering-up to cause; simultaneously; in the time that static discharge impacts, can make described clamp circuit obtain the longer opening time, improve the reliability of electrostatic discharge (ESD) protection.
For realizing above object, the present invention is achieved by the following technical programs:
A kind of power supply clamper ESD protection circuit, includes power pin, ground pin, decision circuit, delay circuit, circuits for triggering and clamp circuit; Wherein:
Power pin, for connecting power supply, so that supply voltage to be provided;
Ground pin, for providing low level;
Decision circuit, it is connected between described power pin and ground pin, for responding to the voltage signal of static discharge;
Delay circuit, its input is connected with the output of described decision circuit, records and retains, so that time delay to be provided for the static discharge voltage signal that described decision circuit is sensed;
Circuits for triggering, its input is connected with the output of described delay circuit, is converted to electrostatic discharge triggering signal for the static discharge voltage signal that described delay circuit is retained;
Clamp circuit, it is connected between described power pin and ground pin, and its input is connected with the output of described circuits for triggering, for receiving after described electrostatic discharge triggering signal, static electricity discharge electric current.
Preferably, described decision circuit is diode-capacitive reactance-impedance circuit, and it further comprises:
Diode, its anodic bonding is in described power pin, and its negative electrode is connected with one end of the first capacitive reactive element, and forms the first tie point;
The other end of described the first capacitive reactive element is connected with first impedor one end, and forms the second tie point; The described first impedor other end is connected in described ground pin;
The output that described the second tie point is this decision circuit, it provides static discharge voltage signal for described delay circuit.
Preferably, described the first capacitive reactive element is electric capacity, and described the first impedance component is resistor.
Preferably, described delay circuit further comprises:
The second impedance component, its first end points is connected to described power pin;
The second capacitive reactive element, its first end points is connected to described power pin;
The first N-type MOS transistor, its grid is connected to the output of described decision circuit, and its drain electrode is connected to described second impedor the second end points, and its source electrode is connected to described ground pin;
The second N-type MOS transistor, its grid and drain electrode are connected to the second end points of described the second capacitive reactive element, and its source electrode is connected to described second impedor the second end points;
The one P type MOS transistor, its grid and drain electrode are connected to the second end points of described the second capacitive reactive element, and its source electrode is connected to described second impedor the second end points;
The 2nd P type MOS transistor, its grid is connected to the second end points of described the second capacitive reactive element, and its drain electrode is connected to described ground pin, and its source electrode is connected to described second impedor the second end points;
The output that described second impedor the second end points is this delay circuit, it provides static discharge voltage signal for described circuits for triggering.
Preferably, described the second impedance component is resistor, and described the second capacitive reactive element is electric capacity.
Preferably, described circuits for triggering further comprise:
The 3rd P type MOS transistor, its grid is connected to the output of described delay circuit, and its source electrode is connected to described power pin;
The 3rd N-type MOS transistor, its grid is connected to the output of described delay circuit, and its source electrode is connected to described ground pin, and its drain electrode is connected to the drain electrode of described the 3rd P type MOS transistor;
The drain electrode of described the 3rd N-type MOS transistor is the output of these circuits for triggering, and it provides described static discharge trigger voltage signal for described clamp circuit.
Preferably, described clamp circuit is N raceway groove clamp transistor, and its grid is connected to the output of described circuits for triggering, and its source electrode is connected to described ground pin, and its drain electrode is connected to described power pin.
The present invention is by providing a kind of power supply clamper ESD protection circuit; this protective circuit is separated decision circuitry and delay circuit; the clamp circuit false triggering of having avoided fast powering-up to cause; simultaneously; in the time that static discharge impacts, can make described clamp circuit obtain the longer opening time, improve the reliability of electrostatic discharge (ESD) protection.
Brief description of the drawings
Fig. 1 is power supply clamper ESD protection circuit figure of the prior art;
Fig. 2 is the theory diagram of power supply clamper ESD protection circuit in one embodiment of the invention;
Fig. 3 is the power supply clamper ESD protection circuit figure of one embodiment of the invention;
Fig. 4 (a) and (b) are respectively the simulation result of power supply clamper ESD protection circuit under esd pulse effect in Fig. 1, Fig. 3;
Fig. 5 (a) and (b) are respectively the simulation result of power supply clamper ESD protection circuit in power supply fast powering-up situation in Fig. 1, Fig. 3.
Embodiment
Under regard to a kind of power supply clamper ESD protection circuit proposed by the invention, in conjunction with the accompanying drawings and embodiments describe in detail.
As shown in Figures 2 and 3, the invention provides a kind of power supply clamper ESD protection circuit, include power pin VDD, ground pin VSS, decision circuit 310, delay circuit 320, circuits for triggering 330 and clamp circuit 340; Wherein:
Power pin VDD, for connecting power supply, so that supply voltage to be provided;
Ground pin VSS, for providing low level;
Decision circuit 310, it is connected between described power pin VDD and ground pin VSS, for responding to the voltage of static discharge;
Delay circuit 320, its input is connected with the output of described decision circuit 310, records and retains, so that time delay to be provided for the static discharge voltage signal that described decision circuit 310 is sensed;
Circuits for triggering 330, its input is connected with the output of described delay circuit 320, is converted to electrostatic discharge triggering signal for the static discharge voltage signal that described delay circuit 320 is retained;
Clamp circuit 340, it is connected between described power pin VDD and ground pin VSS, and its input is connected with the output of described circuits for triggering 330, for receiving after described electrostatic discharge triggering signal, static electricity discharge electric current.
Preferably, as shown in Figure 3, described decision circuit 310 is diode-capacitive reactance-impedance circuit, and it further comprises:
Diode 311, its anodic bonding is in described power pin VDD, and its negative electrode is connected with one end of the first capacitive reactive element, and forms the first tie point A, and described diode 311 is connected between described power pin VDD and described the first tie point A;
The other end of described the first capacitive reactive element is connected with first impedor one end, and forms the second tie point B; Be that described the first capacitive reactive element is connected between described the first tie point A and the second tie point B; The described first impedor other end is connected in described ground pin VSS;
Described the second tie point B is the output of this decision circuit 310, and it provides static discharge voltage signal for described delay circuit 320.
Preferably, described the first capacitive reactive element is electric capacity 312, and described the first impedance component is resistor 313.
Preferably, described delay circuit 320 further comprises:
The second impedance component, its first end points is connected to described power pin VDD;
The second capacitive reactive element, its first end points is connected to described power pin VDD;
The first N-type MOS transistor 323, its grid is connected to the output of described decision circuit 310, and its drain electrode is connected to described second impedor the second end points, and its source electrode is connected to described ground pin VSS;
The second N-type MOS transistor 324, its grid and drain electrode are connected to the second end points of described the second capacitive reactive element, and its source electrode is connected to described second impedor the second end points;
The one P type MOS transistor 325, its grid and drain electrode are connected to the second end points of described the second capacitive reactive element, and its source electrode is connected to described second impedor the second end points;
The 2nd P type MOS transistor 326, its grid is connected to the second end points of described the second capacitive reactive element, and its drain electrode is connected to described ground pin VSS, and its source electrode is connected to described second impedor the second end points;
The output that described second impedor the second end points is this delay circuit 320, it provides static discharge voltage signal for described circuits for triggering 330.
Preferably, described the second impedance component is resistor 321, and described the second capacitive reactive element is electric capacity 322.
Preferably, described circuits for triggering 330 further comprise:
The 3rd P type MOS transistor 331, its grid is connected to the output of described delay circuit 320, and its source electrode is connected to described power pin VDD;
The 3rd N-type MOS transistor 332, its grid is connected to the output of described delay circuit 320, and its source electrode is connected to described ground pin VSS, and its drain electrode is connected to the drain electrode of described the 3rd P type MOS transistor 331;
The drain electrode of described the 3rd N-type MOS transistor 332 is the output of these circuits for triggering 330, and it provides described static discharge trigger voltage signal for described clamp circuit 340.
Preferably, described clamp circuit 340 is N raceway groove clamp transistor 341, and its grid is connected to the output of described circuits for triggering 330, and its source electrode is connected to described ground pin VSS, and its drain electrode is connected to described power pin VDD.
Described clamp circuit 340 is further used for receiving after described electrostatic discharge triggering signal, and the low impedance path between a power supply and ground is provided, with static electricity discharge electric current, and protection internal circuit; It should be noted that, N raceway groove clamp transistor 341 herein can be replaced by other clamps, for example: controllable silicon SCR etc.
Following content is that the operation principle of described power supply clamper ESD protection circuit is described in detail, operation principle when it is included in ESD and impacts lower and power supply fast powering-up:
When ESD impact type occurs, while occurring suddenly that a power vd D arrives the high-voltage pulse of ground VSS, on the voltage of described the second tie point B, move high potential to, the first N-type MOS transistor 323 conductings, and tie point C is pulled down to 0 current potential, described tie point C is the second end points of resistor 321 and the source electrode tie point of the second N-type MOS transistor 324; By the second N-type MOS transistor 324, tie point E is pulled down to compared with electronegative potential again, the grid that described tie point E is described the second N-type MOS transistor 324 and drain electrode and described electric capacity 322 double-pointed tie points, described tie point C is that 0 current potential and tie point D are high potential, N raceway groove clamp transistor 341 is opened, and tie point D is herein the tie point of the grid of described N raceway groove clamp transistor 341 and the drain electrode of described the 3rd N-type MOS transistor 332; After short time, described the second tie point B becomes 0 current potential, and described the first N-type MOS transistor 323 is turn-offed, and by resistor 321, to tie point C charging, described tie point C becomes after high level, and tie point D becomes electronegative potential, and described N raceway groove clamp transistor 341 turn-offs.Wherein, a P type MOS transistor 325 and the 2nd P type MOS transistor 326 form current mirror, the equivalent capacity while effectively increasing tie point C charging, thus increase turn off delay time.
On the other hand, when fast powering-up (establishing the rise time is 100ns), the time constant very little (about 20ns) being coupled due to resistor 313 and electric capacity 312, and diode 311 bears a part of pressure drop (being about its conducting voltage), thereby the voltage that ensures tie point B not can by move high potential to, now the first N-type MOS transistor 323 is turn-offed; Meanwhile, power pin VDD, by resistor in parallel 321 and electric capacity 322, will move high level on tie point C, and now described tie point D is 0 current potential, and described N raceway groove clamp transistor 341 turn-offs.
, will utilize circuit simulation tools HSPICE respectively the power supply clamper ESD protection circuit in Fig. 1 and Fig. 3 to be carried out to emulation below, this emulation be based on standard CMOS 130nm technology library.
First the ESD performance of two circuit is carried out to emulation, Fig. 4 (a) and (b) are respectively two kinds of esd protection circuits simulation results under esd pulse effect in Fig. 1, Fig. 2; With peak value be 2V, square wave that the rise time is 5ns simulation ESD voltage; Can find out, in the time that the time constant of delay circuit is all taken as 500ns, in the embodiment of the present invention, esd protection circuit still can obtain larger time delay.
The situation of the reply fast powering-up to two circuit is carried out emulation again, and Fig. 5 (a) and (b) are respectively two kinds of esd protection circuits simulation results in power supply fast powering-up situation in Fig. 1, Fig. 3; If supply voltage peak value 1.2V, rise time 100ns; Can find out, as ESD circuit in the prior art of Fig. 1 obviously can cause false triggering, and esd protection circuit in the embodiment of the present invention can ensure to turn-off preferably, avoids false triggering.
The present invention is by providing a kind of power supply clamper ESD protection circuit; this protective circuit is separated decision circuitry and delay circuit; the clamp circuit false triggering of having avoided fast powering-up to cause; simultaneously; in the time that static discharge impacts, can make described clamp circuit obtain the longer opening time, improve the reliability of electrostatic discharge (ESD) protection.
Above execution mode is only for illustrating the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; without departing from the spirit and scope of the present invention; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (6)
1. a power supply clamper ESD protection circuit, it is characterized in that, include power pin, ground pin, decision circuit (310), delay circuit (320), circuits for triggering (330) and clamp circuit (340); Wherein:
Power pin, for connecting power supply, so that supply voltage to be provided;
Ground pin, for providing low level;
Decision circuit (310), it is connected between described power pin and ground pin, for responding to the voltage signal of static discharge;
Delay circuit (320), its input is connected with the output of described decision circuit (310), records and retains, so that time delay to be provided for the static discharge voltage signal that described decision circuit (310) is sensed;
Circuits for triggering (330), its input is connected with the output of described delay circuit (320), is converted to electrostatic discharge triggering signal for the static discharge voltage signal that described delay circuit (320) is retained;
Clamp circuit (340), it is connected between described power pin and ground pin, and its input is connected with the output of described circuits for triggering (330), for receiving after described electrostatic discharge triggering signal, static electricity discharge electric current;
Wherein, delay circuit (320) further comprises:
The second impedance component, its first end points is connected to described power pin;
The second capacitive reactive element, its first end points is connected to described power pin;
The first N-type MOS transistor (323), its grid is connected to the output of described decision circuit (310), and its drain electrode is connected to described second impedor the second end points, and its source electrode is connected to described ground pin;
The second N-type MOS transistor (324), its grid and drain electrode are connected to the second end points of described the second capacitive reactive element, and its source electrode is connected to described second impedor the second end points;
The one P type MOS transistor (325), its grid and drain electrode are connected to the second end points of described the second capacitive reactive element, and its source electrode is connected to described second impedor the second end points;
The 2nd P type MOS transistor (326), its grid is connected to the second end points of described the second capacitive reactive element, and its drain electrode is connected to described ground pin, and its source electrode is connected to described second impedor the second end points;
The output that described second impedor the second end points is this delay circuit (320), it provides static discharge voltage signal for described circuits for triggering (330).
2. power supply clamper ESD protection circuit as claimed in claim 1, is characterized in that, described decision circuit (310) is diode-capacitive reactance-impedance circuit, and it further comprises:
Diode (311), its anodic bonding is in described power pin, and its negative electrode is connected with one end of the first capacitive reactive element, and forms the first tie point;
The other end of described the first capacitive reactive element is connected with first impedor one end, and forms the second tie point; The described first impedor other end is connected in described ground pin;
Described the second tie point is the output of this decision circuit (310), and it provides static discharge voltage signal for described delay circuit (320).
3. power supply clamper ESD protection circuit as claimed in claim 2, is characterized in that, described the first capacitive reactive element is electric capacity (312), and described the first impedance component is resistor (313).
4. power supply clamper ESD protection circuit as claimed in claim 1, is characterized in that, described the second impedance component is resistor (321), and described the second capacitive reactive element is electric capacity (322).
5. power supply clamper ESD protection circuit as claimed in claim 1, is characterized in that, described circuits for triggering (330) further comprise:
The 3rd P type MOS transistor (331), its grid is connected to the output of described delay circuit (320), and its source electrode is connected to described power pin;
The 3rd N-type MOS transistor (332), its grid is connected to the output of described delay circuit (320), and its source electrode is connected to described ground pin, and its drain electrode is connected to the drain electrode of described the 3rd P type MOS transistor (331);
The drain electrode of described the 3rd N-type MOS transistor (332) is the output of these circuits for triggering (330), and it provides described electrostatic discharge triggering signal for described clamp circuit (340).
6. power supply clamper ESD protection circuit as claimed in claim 1; it is characterized in that; described clamp circuit (340) is N raceway groove clamp transistor (341); its grid is connected to the output of described circuits for triggering (330); its source electrode is connected to described ground pin, and its drain electrode is connected to described power pin.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210576053.9A CN103107528B (en) | 2012-12-26 | 2012-12-26 | Power clamping electrostatic discharge protection circuit |
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| CN201210576053.9A CN103107528B (en) | 2012-12-26 | 2012-12-26 | Power clamping electrostatic discharge protection circuit |
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| CN103107528A CN103107528A (en) | 2013-05-15 |
| CN103107528B true CN103107528B (en) | 2014-12-10 |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015002510A (en) * | 2013-06-18 | 2015-01-05 | 株式会社東芝 | Electrostatic protection circuit |
| CN104362605B (en) * | 2014-11-06 | 2017-05-24 | 北京大学 | Transient trigger static electricity discharge protection circuit |
| CN104332976B (en) * | 2014-11-20 | 2017-05-17 | 辽宁大学 | High voltage compatible with electrostatic discharge power supply clamp circuit of integrated circuit |
| CN105470938B (en) * | 2016-01-25 | 2018-04-06 | 珠海全志科技股份有限公司 | A kind of power clamp circuit for extending the electrostatic leakage time |
| CN105680433B (en) * | 2016-03-24 | 2018-01-26 | 北京大学 | A kind of ESD power clamps protection circuit |
| US10734806B2 (en) * | 2016-07-21 | 2020-08-04 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
| CN106533419B (en) * | 2016-10-12 | 2022-11-01 | 格科微电子（上海）有限公司 | ESD protection circuit and clock path of MIPI interface |
| US10886729B2 (en) * | 2017-06-01 | 2021-01-05 | Richwave Technology Corp. | Electrostatic discharge protection device for high supply voltage operations |
| CN107732888A (en) * | 2017-10-19 | 2018-02-23 | 丹阳恒芯电子有限公司 | A kind of high performance ESD protection circuit in Internet of Things |
| CN110120659B (en) * | 2018-02-06 | 2021-05-18 | 联发科技股份有限公司 | Electrostatic discharge protection device |
| CN110518561B (en) * | 2019-07-26 | 2020-10-16 | 北京大学 | Power clamp ESD protection circuit and integrated circuit structure |
| CN113224737B (en) * | 2020-01-21 | 2022-08-26 | 华为技术有限公司 | Charging port protection device and terminal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102170118A (en) * | 2011-04-28 | 2011-08-31 | 北京大学 | Power supply clamping position ESD (electronic static discharge) protecting circuit |
| CN102222891A (en) * | 2011-06-20 | 2011-10-19 | 北京大学 | Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror |
| CN102801146A (en) * | 2012-08-24 | 2012-11-28 | 北京大学 | Power clamp ESD (Electronic Static Discharge) protective circuit |
Family Cites Families (1)
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| US8553381B2 (en) * | 2011-05-27 | 2013-10-08 | Hamilton Sundstrand Corporation | Gradually reducing resistive clamp |
-
2012
- 2012-12-26 CN CN201210576053.9A patent/CN103107528B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102170118A (en) * | 2011-04-28 | 2011-08-31 | 北京大学 | Power supply clamping position ESD (electronic static discharge) protecting circuit |
| CN102222891A (en) * | 2011-06-20 | 2011-10-19 | 北京大学 | Power clamping ESD (electro-static discharge) protection circuit utilizing current mirror |
| CN102801146A (en) * | 2012-08-24 | 2012-11-28 | 北京大学 | Power clamp ESD (Electronic Static Discharge) protective circuit |
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