CN103107528B - Power clamping electrostatic discharge protection circuit - Google Patents

Abstract

The invention provides a power supply clamp electrostatic discharge protection circuit, including a power supply pin, a ground pin, and a determination circuit (310) for inducing electrostatic discharge voltage; used for inducing the determination circuit (310) An electrostatic discharge voltage signal is recorded and retained to provide a delay circuit (320); a trigger circuit (330) for converting the electrostatic discharge voltage signal retained by the delay circuit (320) into an electrostatic discharge trigger signal; and A clamping circuit (340) used to discharge the electrostatic current after receiving the electrostatic discharge trigger signal; the present invention separates the judgment circuit from the delay circuit, avoiding false triggering of the clamping circuit that may be caused by fast power-on, At the same time, the clamping circuit can obtain a longer turn-on time when the electrostatic discharge impacts, thereby improving the reliability of electrostatic discharge protection.

Description

A power clamp electrostatic discharge protection circuit

technical field

The invention relates to the field of integrated circuit chip electrostatic discharge (Electronic Static Discharge, ESD) protection technology, in particular to a power clamp ESD protection circuit with a separate determination unit and delay unit.

Background technique

With the continuous shrinking of the feature size of the integrated circuit process, the anti-static discharge capability of the chip has become a key factor to ensure the reliable operation of the internal circuit. The electrostatic discharge phenomenon refers to the transient process of electrostatic charge transfer between two objects with unequal potentials approaching or touching. At the advanced level of integrated circuit technology, the gate oxide layer of the device is very thin, and its equivalent gate oxide layer capacitance is very small. When electrostatic charges accumulate on the gate oxide layer, a large equivalent gate voltage will be formed, resulting in failure of a device or circuit. For integrated circuit chips, there are different modes of electrostatic shock, and correspondingly different protection circuits. In the impact mode of the power pin to the ground pin or the input/output pin to the input/output pin, the electrostatic charge will flow through the internal functional circuit module, causing damage to the internal circuit. The power clamp ESD protection circuit is mainly aimed at the above two impact modes. When the impact comes, it provides an effective electrostatic charge discharge path for the chip to ensure that the internal functional circuits of the chip are not damaged by the impact.

The design of the existing power supply clamp ESD protection circuit needs to meet the following conditions: when the ESD strikes, the capacitor-resistor or resistor-capacitor module of the protection circuit gives an effective signal to turn on the clamp transistor to discharge the electrostatic charge. When the normal charging voltage comes, the clamping transistor is not required to be turned on.

The fast power-up of the power supply makes the power clamp ESD protection circuit face challenges: in order to prevent false triggering of the clamp ESD circuit, the time constant of the capacitor-resistor or resistor-capacitor module needs to be as small as possible; however, too small a time constant cannot guarantee The clamp transistor has enough turn-on time under ESD strike.

Figure 1 shows a power supply clamp ESD protection circuit of the prior art, and its working principle is as follows: when an ESD pulse is applied to the power supply pin VDD, the voltage of node B is pulled up to the voltage level of the VDD pin, and after In a two-stage inverter, the gate voltage of the clamping transistor 1 is pulled up to the voltage level of the power supply pin VDD, and then the clamping transistor 1 starts to discharge the electrostatic charge accumulated in the ESD impact. After the time constant coupled by resistor R1 and capacitor C1 has elapsed, the voltage of node B becomes a logic low level, and after two stages of inverters, the gate voltage of clamp transistor 1 is pulled down to the voltage level of the ground pin, ending ESD protection process.

When the charging voltage of normal power-on is applied to the power pin VDD, the voltage of node B will be maintained at the voltage level of the ground pin. After passing through the two-stage inverter, the gate voltage of the clamping transistor 1 is always in a low-level state, ensuring Clamp transistor 1 is not triggered during normal power-up.

The problem with the prior art shown in FIG. 1 is that the capacitor C1 and the resistor R1 undertake the tasks of determination and delay at the same time. In order to obtain a sufficient ESD turn-on delay (for example, 500ns), there must be a large enough capacitor C1 and resistor R1. However, when the power supply is powered on quickly (for example, 100ns rise time), the charging of capacitor C1 through resistor R1 is will not be able to keep up with the changes, and at this time, false triggering of the clamping transistor 1 will be caused.

Contents of the invention

In order to solve the above problems, the present invention provides a power supply clamp electrostatic discharge protection circuit, which separates the judgment circuit from the delay circuit, avoiding the false triggering of the clamp circuit that may be caused by fast power-on, and at the same time, the electrostatic discharge shock This can enable the clamping circuit to obtain a longer turn-on time and improve the reliability of electrostatic discharge protection.

To achieve the above object, the present invention is achieved through the following technical solutions:

A power clamp electrostatic discharge protection circuit, including a power pin, a ground pin, a judgment circuit, a delay circuit, a trigger circuit and a clamp circuit; wherein:

The power supply pin is used to connect the power supply to provide the power supply voltage;

Ground pin, used to provide low level;

A determination circuit, which is connected between the power supply pin and the ground pin, and is used to induce the voltage signal of electrostatic discharge;

A delay circuit, the input end of which is connected to the output end of the determination circuit, is used to record and retain the electrostatic discharge voltage signal sensed by the determination circuit, so as to provide a delay;

A trigger circuit, the input end of which is connected to the output end of the delay circuit, is used to convert the electrostatic discharge voltage signal retained by the delay circuit into an electrostatic discharge trigger signal;

A clamp circuit, which is connected between the power supply pin and the ground pin, and its input end is connected to the output end of the trigger circuit, and is used to discharge the electrostatic current after receiving the electrostatic discharge trigger signal .

Preferably, the determination circuit is a diode-capacitive reactance-impedance circuit, which further includes:

a diode whose anode is connected to the power supply pin, and whose cathode is connected to one end of the first capacitive reactance element to form a first connection point;

The other end of the first capacitive element is connected to one end of the first impedance element to form a second connection point; the other end of the first impedance element is connected to the ground pin;

The second connection point is the output terminal of the determination circuit, which provides the electrostatic discharge voltage signal for the delay circuit.

Preferably, the first capacitive reactance element is a capacitor, and the first impedance element is a resistor.

Preferably, the delay circuit further includes:

a second impedance element, the first terminal of which is connected to the power supply pin;

a second capacitive reactance element, the first terminal of which is connected to the power supply pin;

A first N-type MOS transistor, the gate of which is connected to the output terminal of the determination circuit, the drain of which is connected to the second terminal of the second impedance element, and the source of which is connected to the ground pin;

a second N-type MOS transistor, the gate and drain of which are connected to the second terminal of the second capacitive element, and the source of which is connected to the second terminal of the second impedance element;

a first P-type MOS transistor, the gate and drain of which are connected to the second terminal of the second capacitive element, and the source of which is connected to the second terminal of the second impedance element;

A second P-type MOS transistor, the gate of which is connected to the second terminal of the second capacitive element, the drain of which is connected to the ground pin, and the source of which is connected to the second terminal of the second impedance element ;

The second terminal of the second impedance element is the output terminal of the delay circuit, which provides an electrostatic discharge voltage signal for the trigger circuit.

Preferably, the second impedance element is a resistor, and the second capacitive reactance element is a capacitor.

Preferably, the trigger circuit further includes:

A third P-type MOS transistor, the gate of which is connected to the output terminal of the delay circuit, and the source of which is connected to the power supply pin;

A third N-type MOS transistor, the gate of which is connected to the output terminal of the delay circuit, the source of which is connected to the ground pin, and the drain of which is connected to the drain of the third P-type MOS transistor;

The drain of the third N-type MOS transistor is the output terminal of the trigger circuit, which provides the electrostatic discharge trigger voltage signal for the clamping circuit.

Preferably, the clamping circuit is an N-channel clamping transistor, its gate is connected to the output terminal of the trigger circuit, its source is connected to the ground pin, and its drain is connected to the power supply pin .

The present invention provides a power supply clamp electrostatic discharge protection circuit, which separates the judgment circuit from the delay circuit, avoids false triggering of the clamp circuit that may be caused by fast power-on, and at the same time, can make all The above clamp circuit obtains a longer turn-on time and improves the reliability of electrostatic discharge protection.

Description of drawings

FIG. 1 is a circuit diagram of a power clamp electrostatic discharge protection circuit in the prior art;

Fig. 2 is a functional block diagram of a power supply clamp electrostatic discharge protection circuit in an embodiment of the present invention;

3 is a circuit diagram of a power clamp electrostatic discharge protection circuit according to an embodiment of the present invention;

Figure 4 (a) and (b) are the simulation results of the power clamp electrostatic discharge protection circuit in Figure 1 and Figure 3 under the action of ESD pulses;

Figure 5(a) and (b) are the simulation results of the power clamp electrostatic discharge protection circuit in Figure 1 and Figure 3 under the condition of fast power-on.

Detailed ways

A power supply clamp electrostatic discharge protection circuit proposed by the present invention will be described in detail below with reference to the drawings and embodiments.

As shown in Figure 2 and Figure 3, the present invention provides a power supply clamp electrostatic discharge protection circuit, including a power supply pin VDD, a ground pin VSS, a determination circuit 310, a delay circuit 320, a trigger circuit 330 and a clamping circuit 340; of which:

The power supply pin VDD is used to connect to a power supply to provide a power supply voltage;

The ground pin VSS is used to provide low level;

A determination circuit 310, which is connected between the power supply pin VDD and the ground pin VSS, and is used to sense the voltage of electrostatic discharge;

Delay circuit 320, its input end is connected with the output end of described judging circuit 310, is used for recording and retaining the electrostatic discharge voltage signal sensed by described judging circuit 310, to provide time delay;

A trigger circuit 330, whose input terminal is connected to the output terminal of the delay circuit 320, is used to convert the electrostatic discharge voltage signal retained by the delay circuit 320 into an electrostatic discharge trigger signal;

The clamping circuit 340 is connected between the power supply pin VDD and the grounding pin VSS, and its input terminal is connected to the output terminal of the trigger circuit 330, for receiving the electrostatic discharge trigger signal, Discharge static electricity.

Preferably, as shown in Figure 3, the determination circuit 310 is a diode-capacitive reactance-impedance circuit, which further includes:

Diode 311, its anode is connected to the power supply pin VDD, its cathode is connected to one end of the first capacitive reactance element, and forms a first connection point A, that is, the diode 311 is connected to the power supply pin VDD and the Between the first connection point A;

The other end of the first capacitive reactance element is connected to one end of the first impedance element to form a second connection point B; that is, the first capacitive reactance element is connected to the first connection point A and the second connection point B between; the other end of the first impedance element is connected to the ground pin VSS;

The second connection point B is the output end of the determination circuit 310 , which provides an electrostatic discharge voltage signal for the delay circuit 320 .

Preferably, the first capacitive reactance element is a capacitor 312 , and the first impedance element is a resistor 313 .

Preferably, the delay circuit 320 further includes:

a second impedance element, the first terminal of which is connected to the power supply pin VDD;

a second capacitive reactance element, the first terminal of which is connected to the power supply pin VDD;

The first N-type MOS transistor 323, its gate is connected to the output terminal of the determination circuit 310, its drain is connected to the second terminal of the second impedance element, and its source is connected to the ground pin VSS;

A second N-type MOS transistor 324, the gate and drain of which are connected to the second terminal of the second capacitive element, and the source of which is connected to the second terminal of the second impedance element;

The first P-type MOS transistor 325, its gate and drain are connected to the second terminal of the second capacitive element, and its source is connected to the second terminal of the second impedance element;

The second P-type MOS transistor 326 has its gate connected to the second terminal of the second capacitive element, its drain connected to the ground pin VSS, and its source connected to the first terminal of the second impedance element. Two endpoints;

The second terminal of the second impedance element is the output terminal of the delay circuit 320 , which provides the trigger circuit 330 with an electrostatic discharge voltage signal.

Preferably, the second impedance element is a resistor 321 , and the second capacitive reactance element is a capacitor 322 .

Preferably, the trigger circuit 330 further includes:

The third P-type MOS transistor 331, its gate is connected to the output terminal of the delay circuit 320, and its source is connected to the power supply pin VDD;

The third N-type MOS transistor 332, its gate is connected to the output terminal of the delay circuit 320, its source is connected to the ground pin VSS, and its drain is connected to the third P-type MOS transistor 331 Drain;

The drain of the third N-type MOS transistor 332 is the output terminal of the trigger circuit 330 , which provides the electrostatic discharge trigger voltage signal for the clamping circuit 340 .

Preferably, the clamping circuit 340 is an N-channel clamping transistor 341, its gate is connected to the output terminal of the trigger circuit 330, its source is connected to the ground pin VSS, and its drain is connected to the The above-mentioned power supply pin VDD.

The clamping circuit 340 is further used to provide a low-impedance channel between the power supply and the ground after receiving the electrostatic discharge trigger signal to discharge the electrostatic current and protect the internal circuit; it should be noted that the The N-channel clamping transistor 341 can be replaced by other clamping devices, for example: SCR and the like.

The following content is a detailed description of the working principle of the power supply clamp electrostatic discharge protection circuit, including the working principle under ESD impact and when the power supply is powered on quickly:

When an ESD impact occurs, that is, when a high-voltage pulse from the power supply VDD to the ground VSS suddenly appears, the voltage of the second connection point B is pulled up to a higher potential, the first N-type MOS transistor 323 is turned on, and the connection point C is pulled down to 0 potential, and the connection point C is the second end point of the resistor 321 and the source connection point of the second N-type MOS transistor 324; then the connection point E is pulled down to a lower level by the second N-type MOS transistor 324 potential, the connection point E is the connection point between the gate and drain of the second N-type MOS transistor 324 and the second terminal of the capacitor 322, the connection point C is 0 potential and the connection point D is a high potential , then the N-channel clamp transistor 341 is turned on, and the connection point D here is the connection point between the gate of the N-channel clamp transistor 341 and the drain of the third N-type MOS transistor 332; after a short time The second connection point B becomes 0 potential, the first N-type MOS transistor 323 is turned off, and the connection point C is charged through the resistor 321. After the connection point C becomes high level, the connection point D becomes is low, the N-channel clamp transistor 341 is turned off. Wherein, the first P-type MOS transistor 325 and the second P-type MOS transistor 326 form a current mirror, which effectively increases the equivalent capacitance when the connection point C is charged, thereby increasing the turn-off delay.

On the other hand, when the power is turned on quickly (assuming that the rise time is 100ns), the time constant of the coupling between the resistor 313 and the capacitor 312 is very small (about 20ns), and the diode 311 bears a part of the voltage drop (about its turn-on voltage) , so as to ensure that the voltage at the connection point B will not be pulled up to a higher potential, and at this time the first N-type MOS transistor 323 is turned off; at the same time, the power supply pin VDD connects the connection point C to pull up to high level, at this time the connection point D is at 0 potential, and the N-channel clamping transistor 341 is turned off.

Next, the circuit simulation tool HSPICE will be used to simulate the power supply clamp electrostatic discharge protection circuit in Figure 1 and Figure 3 respectively. This simulation is based on the standard CMOS130nm process library.

First, simulate the ESD performance of the two circuits. Figure 4 (a) and (b) are the simulation results of the two ESD protection circuits in Figure 1 and Figure 2 under the action of ESD pulses; the peak value is 2V, and the rise time is A square wave of 5 ns simulates the ESD voltage; it can be seen that when the time constants of the delay circuits are all taken as 500 ns, the ESD protection circuit in the embodiment of the present invention can still obtain a greater delay.

Then simulate the situation of the two circuits in response to fast power-on. Figure 5 (a) and (b) are the simulation results of the two ESD protection circuits in Figure 1 and Figure 3 under the condition of fast power-on; The peak voltage is 1.2V, and the rise time is 100ns; it can be seen that the ESD circuit in the prior art shown in Figure 1 will obviously cause false triggering, but the ESD protection circuit in the embodiment of the present invention can ensure better shutdown and avoid false triggering .

The present invention provides a power supply clamp electrostatic discharge protection circuit, which separates the judgment circuit from the delay circuit, avoids false triggering of the clamp circuit that may be caused by fast power-on, and at the same time, can make all The above clamp circuit obtains a longer turn-on time and improves the reliability of electrostatic discharge protection.

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.

Claims (6)

1. A power clamp electrostatic discharge protection circuit is characterized in that it includes a power pin, a ground pin, a determination circuit (310), a delay circuit (320), a trigger circuit (330) and a clamp circuit (340) );in: The power supply pin is used to connect the power supply to provide the power supply voltage; Ground pin, used to provide low level; A determination circuit (310), which is connected between the power supply pin and the ground pin, and is used to induce a voltage signal of electrostatic discharge; A delay circuit (320), whose input terminal is connected to the output terminal of the determination circuit (310), is used to record and retain the electrostatic discharge voltage signal induced by the determination circuit (310), so as to provide a delay; A trigger circuit (330), whose input terminal is connected to the output terminal of the delay circuit (320), is used to convert the electrostatic discharge voltage signal retained by the delay circuit (320) into an electrostatic discharge trigger signal; A clamping circuit (340), which is connected between the power pin and the ground pin, and whose input end is connected to the output end of the trigger circuit (330), is used to receive the electrostatic discharge trigger signal After that, discharge the electrostatic current; Wherein, the delay circuit (320) further includes: a second impedance element, the first terminal of which is connected to the power supply pin; a second capacitive reactance element, the first terminal of which is connected to the power supply pin; The first N-type MOS transistor (323), its gate is connected to the output terminal of the determination circuit (310), its drain is connected to the second terminal of the second impedance element, and its source is connected to the ground Pin; A second N-type MOS transistor (324), whose gate and drain are connected to the second terminal of the second capacitive element, and whose source is connected to the second terminal of the second impedance element; A first P-type MOS transistor (325), the gate and drain of which are connected to the second terminal of the second capacitive reactance element, and the source of which is connected to the second terminal of the second impedance element; The second P-type MOS transistor (326), its gate is connected to the second terminal of the second capacitive reactance element, its drain is connected to the ground pin, and its source is connected to the second impedance element second endpoint; The second terminal of the second impedance element is the output terminal of the delay circuit (320), which provides an electrostatic discharge voltage signal for the trigger circuit (330). 2. power supply clamp electrostatic discharge protection circuit as claimed in claim 1, is characterized in that, described judgment circuit (310) is diode-capacitance-impedance circuit, and it further comprises: a diode (311), the anode of which is connected to the power supply pin, and the cathode of which is connected to one end of the first capacitive reactance element to form a first connection point; The other end of the first capacitive element is connected to one end of the first impedance element to form a second connection point; the other end of the first impedance element is connected to the ground pin; The second connection point is an output terminal of the determination circuit (310), which provides an electrostatic discharge voltage signal for the delay circuit (320). 3. The power supply clamp electrostatic discharge protection circuit according to claim 2, characterized in that, the first capacitive reactance element is a capacitor (312), and the first impedance element is a resistor (313). 4. The power supply clamp electrostatic discharge protection circuit according to claim 1, characterized in that, the second impedance element is a resistor (321), and the second capacitive reactance element is a capacitor (322). 5. The power supply clamp electrostatic discharge protection circuit according to claim 1, characterized in that, the trigger circuit (330) further comprises: A third P-type MOS transistor (331), the gate of which is connected to the output terminal of the delay circuit (320), and the source of which is connected to the power supply pin; The third N-type MOS transistor (332), its gate is connected to the output terminal of the delay circuit (320), its source is connected to the ground pin, and its drain is connected to the third P-type MOS the drain of the transistor (331); The drain of the third N-type MOS transistor (332) is the output terminal of the trigger circuit (330), which provides the electrostatic discharge trigger signal for the clamping circuit (340). 6. power clamp electrostatic discharge protection circuit as claimed in claim 1 is characterized in that, described clamping circuit (340) is N channel clamping transistor (341), and its gate is connected to described trigger circuit ( 330), its source is connected to the ground pin, and its drain is connected to the power supply pin.