CN102801146A - Power clamp ESD (Electronic Static Discharge) protective circuit - Google Patents
Power clamp ESD (Electronic Static Discharge) protective circuit Download PDFInfo
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Abstract
The invention relates to the technical field of electronic static discharge of semiconductor integrated chips and discloses a power clamp ESD (Electronic Static Discharge) protective circuit comprising a power pin, an earth pin, a capacitance-resistance detecting circuit, a bias circuit, a trigger circuit and a clamp circuit. Through the arrangement of the bias circuit, the voltage difference at the two ends of a capacitor-impeder component in the capacitance-resistance detecting circuit is reduced, and the leakage current of the power clamp ESD protective circuit is effectively inhibited.
Description
Technical field
The present invention relates to static discharge (Electronic Static Discharge, ESD) resist technology field, particularly a kind of power supply clamper esd protection circuit of semiconductor integrated chip.
Background technology
In processes such as the manufacturing of IC chip, encapsulation, test, transportation, electrostatic discharge event in various degree all can appear.When integrated circuit discharges, can produce the equivalent high pressure of hundreds if not thousands of volts, the gate oxide that this can puncture input stage in the integrated circuit sustains damage integrated circuit.Scaled along with transistor size in the integrated circuit particularly, the gate oxide thickness of input stage is more and more thinner, is more prone to receive the influence of exterior static electric charge and damages.
For the protection integrated circuit does not receive electrostatic damage, input and output interface (Pin) generally has corresponding esd protection circuit.But core circuit is directly connected between power vd D and the ground VSS, if do not have the protection of power supply clamp circuit, the destruction that is easy to receive esd pulse.Traditional power supply and the esd clamp position circuit between the ground adopt electric capacity-resistance (C-R) coupled modes to realize that Fig. 1 shows its basic structure.
Esd protection circuit among Fig. 1 comprises an electric capacity-resistance (C-R) circuit, circuits for triggering and a clamp circuit.Wherein, electric capacity-resistance (C-R) circuit comprises resistance R 1 and electric capacity Mcap, is used to respond to ESD voltage, and drives circuits for triggering; Circuits for triggering comprise first inverter and second inverter; First inverter comprises P type Metal-oxide-semicondutor (PMOS) transistor Mp1 and N type Metal-oxide-semicondutor (NMOS) transistor Mn1, and its output is used to drive second inverter; Second inverter comprises PMOS transistor Mp2 and nmos pass transistor Mn2, and its output is used to drive the grid of clamp circuit; Clamp circuit is made up of a large-sized N-raceway groove clamp transistor Mbig, is used for when sensing esd pulse, providing power supply to arrive the current drain passage on ground.
When the circuit operate as normal, resistance R 1 is pulled down to low level VSS with node A, and the grid through first inverter and a low level VSS driving N-raceway groove clamp transistor Mbig of second inverter generation makes its shutoff.When esd pulse was applied on the VDD, it was high level that electric capacity Mcap keeps node A, kept a period of time simultaneously, and this time is by the R-C time constant decision of resistance R 1 and electric capacity Mcap.The high level input of node A produces a low level output in Node B under the effect of first inverter, drive second inverter; Then produce a high level output at node C; The grid of driving N-raceway groove clamp transistor Mbig is opened it to high level, and the low impedance path from VDD to VSS is provided; With the electrostatic charge of releasing, play the effect of protection internal circuit.
Though the conventional power source clamp circuit of this C-R structure was once brought into play important function aspect esd protection; But along with semiconductor technology gets into the nano-scale rank; The gate oxide thickness of semiconductor device is attenuate day by day, makes that the gate oxide electric leakage problem of this circuit is more and more serious.In addition, be to reduce circuit area and cost, Metal-oxide-semicondutor (MOS) electric capacity that adopts nano-scale technology to realize usually in the esd protection circuit replaces traditional capacitor, and this causes the increase of leaking electricity more easily.
Be example with the esd protection circuit among Fig. 1 still, under the nano-scale process conditions, the electric leakage of this circuit mainly comes from the thin gate oxide of mos capacitance Mcap.Gate oxide is thin more, and the leakage current of mos capacitance is just big more, thereby on resistance R 1, produces bigger pressure drop; Make the level of normal condition lower node A be higher than VSS; Then make nmos pass transistor Mn1 conducting, Node B is pulled down to a level that is lower than VDD, make PMOS transistor Mp2 conducting; Node C is pulled to a level that is higher than VSS, makes the conducting of N-raceway groove clamp transistor Mbig subthreshold value.For guaranteeing that circuit has enough electrostatic leakage abilities, N-raceway groove clamp transistor Mbig often adopts the transistor of oversize to realize, so its subthreshold value electric leakage is also very big.Like this, because the electric leakage of mos capacitance Mcap has caused more electric leakage factor.
Too much leakage current has increased the error probability of esd protection circuit.For example, excessive leakage current might cause the false triggering of esd protection circuit, and then under normal circumstances opens clamp circuit, causes the electric leakage problem that circuit working is not normal and initiation is more serious.Simultaneously, for some portable use, low electric leakage also is very important.
In a word, when not having esd event to take place, must try every possible means to suppress the leakage current of esd protection circuit, in order to avoid produce the consequences such as false triggering of esd clamp position circuit.
Summary of the invention
The technical problem that (one) will solve
The technical problem that the present invention will solve is: the leakage current that how to suppress esd protection circuit.
(2) technical scheme
For solving the problems of the technologies described above, technical scheme of the present invention provides a kind of power supply clamper esd protection circuit, comprising:
Power pin is used to provide supply voltage VDD;
Ground pin is used to provide ground level VSS;
Electric capacity-resistance circuit is used to respond to the static discharge esd pulse, and said electric capacity-resistance circuit comprises: impedance component is connected between said ground pin and the node A; Capacitive reactive element is connected between node A and the Node B;
Biasing circuit is connected between said Node B and the power pin, is used to said Node B bias voltage is provided;
Circuits for triggering are connected between said power pin, ground pin and electric capacity-resistance circuit three, are used for producing according to the level of said node A and Node B the triggering signal of static discharge; Wherein, said triggering signal is through output node D output; And,
Clamp circuit is connected between said power pin, ground pin and the circuits for triggering three, and being used for provides the low impedance path between a power supply and the ground after receiving said static discharge ESD triggering signal, with the electrostatic charge of releasing.
Preferably, the capacitive reactive element in said electric capacity-resistance circuit realizes that through PMOS electric capacity grid is connected to said node A, is the bottom crown of capacitive reactive element, and source electrode, drain electrode and substrate all are connected to said Node B, are the top crown of capacitive reactive element.
Preferably, said circuits for triggering further comprise:
The one PMOS transistor Mp1, grid is connected to said Node B, and source electrode is connected to said power pin, and drain electrode is connected to said node C;
The first nmos pass transistor Mn1, grid are connected to said node A, and source electrode is connected to said ground pin, and drain electrode links to each other with the drain electrode of a said PMOS transistor Mp1;
The 2nd PMOS transistor Mp2, grid is connected to said node C, and source electrode is connected to said power pin, and drain electrode is connected to said output node D; And,
The second nmos pass transistor Mn2, grid are connected to said node C, and source electrode is connected to said ground pin, and drain electrode links to each other with the drain electrode of said the 2nd PMOS transistor Mp2.
Preferably, said biasing circuit further comprises:
The 3rd PMOS transistor Mp3, grid is connected to said node C, and source electrode is connected to said ground pin, and drain electrode is connected to said Node B;
Wherein, The drain electrode of said the 3rd PMOS transistor Mp3 is as the output node of said biasing circuit, for the said Node B of said electric capacity-resistance circuit provides bias voltage, simultaneously; The grid of Mp3 is connected to said node C, to realize the feedback of said circuits for triggering to said biasing circuit.
Preferably, said clamp circuit further comprises:
N-raceway groove clamp transistor Mbig, grid is connected to the output node D of said circuits for triggering, and its source electrode is connected to said ground pin, and its drain electrode is connected to said power pin.
(3) beneficial effect
Power supply clamper esd protection circuit according to the present invention can be applicable to present nano-scale technological level, can when the circuit operate as normal, reduce the leakage current of electrostatic discharge protective circuit greatly, thereby avoids the false triggering equivalent risk of esd clamp position circuit; Come to have good clamping action at esd pulse simultaneously temporarily, can effectively protect internal circuit not receive electrostatic damage.
Description of drawings
Fig. 1 is the structural representation of the power supply clamper esd protection circuit realized of employing traditional capacitance-resistance (C-R) structure of prior art;
Fig. 2 is the structural representation of electric capacity-resistance (C-R) type power supply clamper esd protection circuit of the technical scheme according to the present invention;
Fig. 3 a, Fig. 3 b are respectively the leakage current simulation result of two kinds of esd detection circuits under power supply normal power-up situation among Fig. 1, Fig. 2.
Embodiment
Hereinafter, will combine accompanying drawing to describe embodiments of the invention in detail.
Core concept of the present invention is: esd detection circuit is not directly connected to power vd D, but is coupled to VDD indirectly through a biasing circuit.Through using this biasing circuit, can reduce the voltage difference at mos capacitance two ends, thereby reduce the leakage current of this mos capacitance, and then suppress other transistorized subthreshold value electric leakage in the esd protection circuit, improve the reliability of circuit.
Thus; The invention provides a kind of power supply clamper esd protection circuit; Be a kind of power supply of biasing circuit and feedback technique realization and low leakage type clamp circuit between the ground (power-to-ground) of adopting; It comprises: power pin VDD, and ground pin VSS, and be coupled to esd detection circuit and the clamp circuit between this power pin VDD and the ground pin VSS.With the traditional esd detection circuit (esd detection circuit among Fig. 1 for example; Constitute by electric capacity-resistance (C-R) circuit and circuits for triggering) different a bit be; Remove outside electric capacity-resistance (C-R) circuit and the circuits for triggering, the esd detection circuit among the present invention also comprises a biasing circuit.
Fig. 2 shows the structural representation according to an embodiment of the power supply clamper esd protection circuit of technical scheme of the present invention; As shown in Figure 2; Power supply clamper esd protection circuit in the present embodiment comprises: power pin VDD; Ground pin VSS, and be coupling in esd detection circuit and the clamp circuit between power vd D and the ground VSS.Further, the esd detection circuit in the present embodiment comprises electric capacity-resistance (C-R) circuit, circuits for triggering and three parts of biasing circuit.
Electric capacity-resistance in the present embodiment (C-R) circuit is used to respond to static discharge ESD voltage, comprises a capacitive reactive element and an impedance component.Wherein, impedance component is connected between ground connection VSS and the node A, and capacitive reactive element is connected between this node A and the Node B, and this Node B is not directly to connect power supply.Preferably, this capacitive reactive element can be passed through the realization of Metal-oxide-semicondutor (MOS) electric capacity under advanced nanometer technology level.
As shown in Figure 2, more specifically, the C-R circuit in the present embodiment comprises mos capacitance Mcap and resistance R 1.More specifically, resistance R 1 is connected between ground VSS and the node A, and mos capacitance Mcap is connected between node A and the Node B, rather than directly connects power supply.Because the two ends of this mos capacitance are all earth-free, can only realize through the PMOS transistor.In the practical implementation process, the grid of mos capacitance Mcap is connected to node A, and its source electrode, drain electrode and substrate all are connected to Node B.
Circuits for triggering in the present embodiment are used to produce the ESD triggering signal.As shown in Figure 2, the circuits for triggering in the present embodiment can comprise a PMOS transistor Mp1, the first nmos pass transistor Mn1, the 2nd PMOS transistor Mp2 and the second nmos pass transistor Mn2.Wherein, the grid of a PMOS transistor Mp1 is connected to Node B, and its source electrode is connected to power vd D, and drain electrode is connected to node C.The grid of the first nmos pass transistor Mn1 is connected to node A, and its source electrode is connected to said ground pin, and drain electrode also is connected to node C.The grid of the 2nd PMOS transistor Mp2 is connected to node C; Its source electrode is connected to said power pin; Its drain electrode is connected to node D as the output of circuits for triggering; Be used to export the esd clamp position circuit Mbig of an ESD triggering signal, make it when esd pulse arrives, to open, provide power supply to the low impedance path between the ground to the back.Simultaneously, the grid of the second nmos pass transistor Mn2 is connected to node C, and its source electrode is connected to said ground pin, and its drain electrode links to each other with the drain electrode of the 2nd PMOS transistor Mp2, also is connected to the output node D of circuits for triggering.
Biasing circuit in the present embodiment is connected between Node B and the VDD, and the top crown (being Node B) that is used to the mos capacitance Mcap in the C-R circuit provides a bias voltage, and this bias voltage is lower than VDD.Through this biasing circuit, can reduce the voltage difference of mos capacitance Mcap substrate and grid, thereby reduce its leakage current.
Still with reference to figure 2, the biasing circuit in the present embodiment only comprises a PMOS transistor Mcap.The grid receiving node C of this nmos pass transistor Mcap realizes the feedback of circuits for triggering to biasing circuit thus.Its source ground, drain electrode are connected to the grid of mos capacitance Mcap, for Node B provides bias voltage as the output of biasing circuit.Through this biasing circuit, the grid of mos capacitance Mcap no longer directly connects power supply, but and differed the drain-source voltage of a PMOS transistor Mp3 between the VDD, thereby the voltage difference of having dwindled these mos capacitance two ends.
As shown in Figure 2, the clamp circuit in the present embodiment is made up of a large-sized N-raceway groove clamp transistor Mbig, and its grid receives the ESD triggering signal, is connected to the output node D of circuits for triggering, and source electrode meets VSS and VDD respectively with drain electrode.The effect of this clamp circuit is after receiving the ESD triggering signal, to open clamp transistor, the current drain path that provides power supply to arrive ground, protection internal circuit.Need to prove that the N-raceway groove clamp transistor Mbig here can be replaced by other clamps, for example: silicon controlled rectifier (SCR) etc. are confined to a kind of structure among Fig. 2 incessantly.
To describe the operation principle of this power supply clamper esd protection circuit below in detail, comprise under the normal condition two kinds of situation when taking place with esd event.
When esd event takes place, that is: when occurring a power supply to the high-voltage pulse on ground (VDD-to-VSS) suddenly, because the coupling of mos capacitance Mcap; Node A level rising causes nmos pass transistor Mn1 conducting, and pull-down node C is to low level VSS; And then cause PMOS transistor Mp1 conducting, on draw node D to high level VDD, and then open clamp circuit; Make N-raceway groove clamp transistor Mbig conducting; The low impedance path of a power supply to ground is provided, the electrostatic charge of releasing, the protection internal circuit is avoided electrostatic damage.
Simultaneously, biasing circuit also helps the realization of clamper function.Node C feeds back to the grid of PMOS transistor Mp3 with low level, thereby makes its conducting, drags down the level of Node B; Make the PMOS transistor Mp1 in the circuits for triggering keep turn-offing; Can't on draw node C level, and then make in the circuits for triggering nmos pass transistor Mn1 keep turn-offing, can't pull-down node D level; Clamp circuit can be opened the long period, the electrostatic charge of fully releasing.
On the other hand; When not having esd event to take place (that is: under the normal condition), node A remains on low level VSS through the effect of pull down resistor R1, makes PMOS transistor Mp1 be in opening; Node C is pulled to high level VDD; Thereby make nmos pass transistor Mn2 be in opening, node D is pulled down to low level VSS, and then turn-offs N-raceway groove clamp transistor.Simultaneously, the low level of node C makes that also the PMOS transistor Mp3 in the biasing circuit can't conducting, thereby makes its drain electrode (being Node B) keep lower voltage.Node B is a low level; Can open PMOS transistor Mp1 on the one hand, node C further is pulled to VDD, and then open nmos pass transistor Mn2; To trigger output node D and further be pulled down to VSS, guarantee that N-raceway groove clamp transistor Mbig is in the state that turn-offs fully; On the other hand, the level of Node B means that far below VDD the voltage difference at mos capacitance Mcap two ends reduces greatly, and the circuit in Fig. 1 has had very big improving (voltage difference at mos capacitance Mcap two ends is approximately the poor of VDD and VSS among Fig. 1).The voltage difference at mos capacitance Mcap two ends is more little, and then its gate oxide electric leakage is just more little, and the subthreshold value electric leakage that this can further suppress other metal-oxide-semiconductors in the circuit prevents the generation of false triggering phenomenon.
Below, with utilizing circuit simulation tools HSPICE respectively the power supply clamper esd protection circuit according to the embodiment of the invention among the available circuit among Fig. 1 and Fig. 2 to be carried out emulation, and its simulation result is compared.Based on the analysis of compared result, advantage of the present invention will be more obvious.
The measured 65 nanometer technology storehouses of this emulation are with the advantage of proof the present invention under advanced nano-scale process conditions.Because Fig. 1 has used identical N-raceway groove clamp transistor as the current drain device with circuit among Fig. 2, and the circuit among Fig. 2 is with respect to the main improvement of circuit among Fig. 1: the grid control circuit of N-raceway groove clamp transistor, that is: esd detection circuit.Therefore, emulation is only carried out to esd detection circuit, does not comprise N-raceway groove clamp transistor.
Fig. 3 a and Fig. 3 b have shown when the power supply normal power-up, two kinds of esd detection circuits total leakage current size separately among Fig. 1, Fig. 2.Can know like Fig. 3 a and Fig. 3 b; The leakage current of the esd detection circuit of traditional structure is about 5.47 μ A; And the leakage current of the new E SD testing circuit that the present invention proposes only has 62nA; Reduced two most magnitudes than the former, thereby confirmed that ESD power supply clamp circuit has good low leakage current characteristic among the present invention.
As stated; Under normal condition; Biasing circuit according to the embodiment of the invention can make the voltage difference between node A and the Section Point B maintain in the lower scope; Thereby reduce the gate oxide electric leakage of mos capacitance Mcap, reduce the leakage current of entire circuit afterwards, improve the reliability of esd protection circuit.
Present embodiment only is used to explain the purpose of technical scheme of the present invention.Therefore, technical scheme of the present invention should not limited present embodiment.Employed key element equally also shall not be applied to and limits technical scheme of the present invention in the present embodiment.
Claims (5)
1. a power supply clamper esd protection circuit is characterized in that, comprising:
Power pin is used to provide supply voltage VDD;
Ground pin is used to provide ground level VSS;
Electric capacity-resistance circuit is used to respond to the static discharge esd pulse, and said electric capacity-resistance circuit comprises: impedance component and capacitive reactive element, said impedance component are connected between said ground pin and the node A; Said capacitive reactive element is connected between node A and the Node B;
Biasing circuit is connected between said Node B and the power pin, is used to said Node B bias voltage is provided;
Circuits for triggering are connected between said power pin, ground pin and electric capacity-resistance circuit three, are used for producing according to the level of said node A and Node B the triggering signal of static discharge; Wherein, said triggering signal is through output node D output; And,
Clamp circuit is connected between said power pin, ground pin and the circuits for triggering three, and being used for provides the low impedance path between a power supply and the ground after receiving said static discharge ESD triggering signal, with the electrostatic charge of releasing.
2. power supply clamper esd protection circuit as claimed in claim 1; It is characterized in that; Capacitive reactive element in said electric capacity-resistance circuit realizes that through PMOS electric capacity the grid of PMOS electric capacity is connected to said node A, and source electrode, drain electrode and substrate all are connected to said Node B.
3. power supply clamper esd protection circuit as claimed in claim 1 is characterized in that said circuits for triggering further comprise:
The one PMOS transistor Mp1, grid is connected to said Node B, and source electrode is connected to said power pin, and drain electrode is connected to node C;
The first nmos pass transistor Mn1, grid are connected to said node A, and source electrode is connected to said ground pin, and drain electrode links to each other with the drain electrode of a said PMOS transistor Mp1;
The 2nd PMOS transistor Mp2, grid is connected to said node C, and source electrode is connected to said power pin, and drain electrode is connected to said output node D; And,
The second nmos pass transistor Mn2, grid are connected to said node C, and source electrode is connected to said ground pin, and drain electrode links to each other with the drain electrode of said the 2nd PMOS transistor Mp2.
4. power supply clamper esd protection circuit as claimed in claim 1 is characterized in that said biasing circuit further comprises:
The 3rd PMOS transistor Mp3, grid is connected to said node C, and source electrode is connected to said ground pin, and drain electrode is connected to said Node B;
Wherein, the drain electrode of said the 3rd PMOS transistor Mp3 is as the output node of said biasing circuit, for the said Node B of said electric capacity-resistance circuit provides bias voltage.
5. like each described power supply clamper esd protection circuit in the claim 1 ~ 4, it is characterized in that said clamp circuit further comprises:
N-raceway groove clamp transistor Mbig, grid is connected to the output node D of said circuits for triggering, and source electrode is connected to said ground pin, and drain electrode is connected to said power pin.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012103060293A CN102801146A (en) | 2012-08-24 | 2012-08-24 | Power clamp ESD (Electronic Static Discharge) protective circuit |
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| CN2012103060293A CN102801146A (en) | 2012-08-24 | 2012-08-24 | Power clamp ESD (Electronic Static Discharge) protective circuit |
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Cited By (9)
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| CN103107528A (en) * | 2012-12-26 | 2013-05-15 | 北京大学 | Power clamping electrostatic discharge protection circuit |
| CN104362606A (en) * | 2014-11-20 | 2015-02-18 | 辽宁大学 | Electrostatic discharge power source clamping circuit for integrated circuit and control method thereof |
| CN107026434A (en) * | 2016-01-29 | 2017-08-08 | 联发科技股份有限公司 | ESD protection circuit and method |
| CN109148439A (en) * | 2018-08-14 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Full chip electrostatic releasing network |
| CN110855277A (en) * | 2019-12-02 | 2020-02-28 | 思瑞浦微电子科技（苏州）股份有限公司 | Adjustable clamping circuit |
| CN112448380A (en) * | 2020-12-24 | 2021-03-05 | 成都思瑞浦微电子科技有限公司 | Bidirectional ESD protection circuit |
| CN113242035A (en) * | 2021-05-08 | 2021-08-10 | 上海数明半导体有限公司 | Driver circuit based on capacitive isolation and electronic device |
| CN114123147A (en) * | 2021-10-11 | 2022-03-01 | 杭州傲芯科技有限公司 | Electrostatic discharge protection module for chip and device thereof |
| WO2023279486A1 (en) * | 2021-07-08 | 2023-01-12 | 长鑫存储技术有限公司 | Electrostatic protection circuit and chip |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103107528A (en) * | 2012-12-26 | 2013-05-15 | 北京大学 | Power clamping electrostatic discharge protection circuit |
| CN103107528B (en) * | 2012-12-26 | 2014-12-10 | 北京大学 | Power clamping electrostatic discharge protection circuit |
| CN104362606A (en) * | 2014-11-20 | 2015-02-18 | 辽宁大学 | Electrostatic discharge power source clamping circuit for integrated circuit and control method thereof |
| CN104362606B (en) * | 2014-11-20 | 2018-06-26 | 辽宁大学 | For the static discharge power clamping circuit and its control method of integrated circuit |
| CN107026434A (en) * | 2016-01-29 | 2017-08-08 | 联发科技股份有限公司 | ESD protection circuit and method |
| CN109148439A (en) * | 2018-08-14 | 2019-01-04 | 上海华虹宏力半导体制造有限公司 | Full chip electrostatic releasing network |
| CN110855277A (en) * | 2019-12-02 | 2020-02-28 | 思瑞浦微电子科技（苏州）股份有限公司 | Adjustable clamping circuit |
| CN112448380A (en) * | 2020-12-24 | 2021-03-05 | 成都思瑞浦微电子科技有限公司 | Bidirectional ESD protection circuit |
| CN112448380B (en) * | 2020-12-24 | 2023-04-07 | 成都思瑞浦微电子科技有限公司 | Bidirectional ESD protection circuit |
| CN113242035A (en) * | 2021-05-08 | 2021-08-10 | 上海数明半导体有限公司 | Driver circuit based on capacitive isolation and electronic device |
| WO2023279486A1 (en) * | 2021-07-08 | 2023-01-12 | 长鑫存储技术有限公司 | Electrostatic protection circuit and chip |
| CN114123147A (en) * | 2021-10-11 | 2022-03-01 | 杭州傲芯科技有限公司 | Electrostatic discharge protection module for chip and device thereof |
| CN114123147B (en) * | 2021-10-11 | 2022-08-09 | 杭州傲芯科技有限公司 | Electrostatic discharge protection module for chip and device thereof |
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Application publication date: 20121128 |