CN112448380B - Bidirectional ESD protection circuit - Google Patents
Bidirectional ESD protection circuit Download PDFInfo
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- CN112448380B CN112448380B CN202011546107.8A CN202011546107A CN112448380B CN 112448380 B CN112448380 B CN 112448380B CN 202011546107 A CN202011546107 A CN 202011546107A CN 112448380 B CN112448380 B CN 112448380B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a bidirectional ESD protection circuit, which is connected between a PIN PIN at a power supply end of a chip and a PIN GND at a ground end and is formed by connecting diodes D1, PMOS tubes MP 1-MP 5 and a resistor R1, wherein drain electrodes of the PMOS tubes MP1 and MP2 and grid electrodes of the MP4 are connected with the PIN PIN, a source electrode and a drain electrode of the MP4 are connected with a grid electrode of the MP2 in a common way, a source electrode of the PMOS tube MP1, a drain electrode of the MP3 and a grid electrode of the MP5 are connected with a cathode electrode of the diode D1 at a node Vminus, a source electrode and a drain electrode of the MP5 are connected with a grid electrode of the MP3 in a common way, an anode of the diode D1 is connected with the PIN GND, common source electrodes of the PMOS tubes MP2 and MP3 and substrate substrates of all PMOS tubes are connected with a homogeneous phase node Vbody, and the resistor R1 is connected between the grid electrode of the PMOS tube MP1 and the node Vbody. By applying the ESD protection circuit design, when positive static electricity or negative static electricity is generated, the positive static electricity can be absorbed by a positive high-voltage-resistant diode, and the negative diode is subjected to voltage division limitation; through simple design and smaller area occupation, the reliability of ESD protection is improved, and internal circuits of the chip are effectively prevented from being damaged.
Description
Technical Field
The invention relates to a chip protection circuit, in particular to a bidirectional ESD protection circuit for positive high voltage and negative low voltage.
Background
An ESD (Electro-Static discharge) protection circuit is an indispensable part of an integrated circuit. The chip is mainly responsible for protecting devices inside the chip from being damaged by ESD, and the reliability of the chip or a system is improved.
With the popularization of the application of high-voltage and high-current application scenes, a large negative voltage peak appears when the ground of a power supply system has instantaneous high current, so that the application of a chip needs to cover the application scenes of positive high voltage and negative low voltage, and a bidirectional ESD structure of the positive high voltage and the negative low voltage is generated. Taking a driver chip of the MOSFET as an example, the maximum working voltage of the chip is more than 20V, the instantaneous peak current of the chip driving the MOSFET can reach 7A, the instantaneous peak current generates a large ground noise on a chip ground and a system ground due to the existence of parasitic inductance, and a noise signal of minus several volts appears, so that a voltage requirement range suitable for minus 5V to plus 20V appears. A bidirectional ESD protection circuit with high positive voltage and low negative voltage is required.
Most of the conventional bidirectional ESD structures are structures with low voltage in both directions or high voltage in both directions, and are not suitable for the application scenarios.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a bidirectional ESD protection circuit, which can improve the reliability of ESD protection with a small area.
In order to achieve the above object, the technical solution adopted by the present invention is a bidirectional ESD protection circuit, connected between a PIN at a power supply end of a chip and a PIN GND at a ground end, and characterized in that: the diode is formed by connecting diodes D1 and PMOS tubes MP 1-MP 5, wherein the drains of the PMOS tubes MP1 and MP2 and the gates of MP4 are connected with a PIN PIN, the source and the drain of MP4 are connected with the gate of MP2 in a common way, the source of the PMOS tube MP1, the drain of MP3 and the gate of MP5 are connected with the cathode of the diode D1 at a node Vminus, the source and the drain of MP5 are connected with the gate of MP3 in a common way, the anode of the diode D1 is connected with the PIN GND and the common sources of the PMOS tubes MP2 and MP3, the gates of MP1 and the substrates of all PMOS tubes are connected with a node Vbody.
Further, the transistor also comprises a resistor R1 connected between the grid of the PMOS tube MP1 and the node Vbody.
Further, the power supply further comprises a resistor R2 and a resistor R3, wherein one end of the resistor R2 is connected with the PIN PIN, and the other end of the resistor R2 is connected with the source electrode of the PMOS transistor MP 5; one end of the resistor R3 is connected to the node Vminus, and the other end of the resistor R3 is connected with the source electrode of the PMOS tube MP 4.
The protection circuit design of the invention has prominent substantive features and remarkable progress: when positive static electricity or negative static electricity is generated, the circuit can correspondingly switch the conductivity of the joint substrate nodes of all PMOS tubes facing different pin directions, and the positive static electricity is absorbed by using positive high-voltage-resistant diodes and is limited by using negative diodes in a voltage division manner; through simple design and smaller area occupation, the reliability of ESD protection is improved, and internal circuits of the chip are effectively prevented from being damaged.
Drawings
Fig. 1 is a schematic diagram of a preferred implementation of the bidirectional ESD protection circuit for high-voltage positive and low-voltage negative of the present invention.
Detailed Description
The following detailed description of the present invention is provided with reference to the accompanying drawings for illustrating embodiments of the present invention so that the technical solutions of the present invention can be understood and appreciated more clearly, and thus the scope of the present invention is defined more clearly.
The invention provides a novel bidirectional ESD protection circuit aiming at solving the defects that the bidirectional high-low voltage structure of the traditional bidirectional ESD structure is not suitable for partial application scenes and has poor protection reliability, combining self experience and creative labor, and aiming at seeking breakthrough on the optimization of the circuit performance, so as to meet the ESD protection requirements of positive high voltage and negative low voltage.
In order to realize that various functional chips can cope with noise impact of forward static electricity or reverse static electricity, a flexibly jumping protection branch circuit for voltage-resistant interception or current-guiding voltage division is required to be introduced between an energy supply pin and a grounding pin of the chip. To solve this problem, as can be seen from the schematic diagram of the preferred implementation structure of the bidirectional ESD protection circuit shown in fig. 1, the technical solution is summarized as follows: the power supply circuit mainly comprises diodes D1, PMOS tubes MP 1-MP 5 and a resistor R1 which are connected, wherein drain electrodes of the PMOS tubes MP1 and MP2 and grid electrodes of the MP4 are connected with an energy supply PIN PIN, a source electrode and a drain electrode of the MP4 are connected with a grid electrode of the MP2, a source electrode of the PMOS tube MP1, a drain electrode of the MP3 and a grid electrode of the MP5 are connected with a cathode of the diode D1 at a node Vminus, a source electrode and a drain electrode of the MP5 are connected with a grid electrode of the MP3, an anode of the diode D1 is connected with a PIN GND at the ground, and common source electrodes of the PMOS tubes MP2 and MP3, a grid electrode of the MP1 and substrates of all the PMOS tubes are connected with a node Vbody. The node Vbody is mainly used for adapting to the generated positive static electricity or negative static electricity, and switches the conductivity facing different pins to adjust the direction of the current flowing through the PMOS transistor MP 1. And the node Vminus is the minimum negative potential after being subjected to positive conduction and voltage division by the diode D1 after negative static electricity is generated. In the preferred embodiment shown in the figure, a resistor R1 is connected between the gate of the PMOS transistor MP1 and the node Vbody. R1 and MP1 form a bidirectional GCNMOS structure, and when ESD occurs, the channel of MP1 is enabled to be conducted briefly to trigger ESD.
The basic protection circuit structure further comprises a resistor R2 and a resistor R3, wherein one end of the resistor R2 is connected with the PIN PIN, and the other end of the resistor R2 is connected with a source electrode of the PMOS tube MP 5; one end of the resistor R3 is connected to the node Vminus, and the other end of the resistor R3 is connected with the source electrode of the PMOS tube MP 4. Here, the resistor R2 is mainly used for gate oxide of the ESD protection MP 3; similarly, the resistor R3 is mainly used for gate oxide of the ESD protection MP 2.
On the basis of the bidirectional ESD protection circuit, the electrostatic pulse discharge principle is further understood: when forward static arrives between chip energy supply PIN PIN and ground connection PIN GND, PMOS pipe MP2 switches on, promptly from this switches on energy supply PIN PIN and node Vbody. At this moment, the current of the forward static electricity flows into the ground pin GND through the PMOS transistor MP1 and the diode D1 according to the voltage difference distribution, and the diode D1 is a high voltage resistant ESD diode, so that the forward high voltage resistant performance of the protection circuit is excellent. When negative static electricity arrives between the chip energy supply PIN PIN and the grounding PIN GND, the PMOS tube MP3 is conducted, namely the node Vminus and the node Vbody are conducted. The current of the negative static electricity will flow to the power supply PIN through the diode D1 and the PMOS transistor MP1 according to the voltage difference. At this moment, because the diode D1 is in a positive conducting state, the divided negative electrostatic discharge voltage is suppressed to be small, so that the internal circuit of the chip can be protected from being damaged.
In summary, it can be seen from the detailed description of the illustrated embodiments that the bidirectional ESD protection circuit with the optimized design of the present invention has the outstanding substantive features and significant improvements: when positive static electricity or negative static electricity is generated, the circuit can correspondingly switch the conductivity of the joint of the common substrate of each PMOS tube facing different pin directions, the positive static electricity is absorbed by the positive high-voltage-resistant diode, and the negative diode is used for voltage division limitation, so that the reliability of ESD protection is improved, and the internal circuit of the chip is effectively prevented from being damaged. More significantly, the protection circuit has simple structural design and small occupied area, thereby being beneficial to the popularization and the application of various miniaturized integrated circuits.
The preferred embodiments of the present invention have been described in detail, however, the present invention is not limited to the above specific embodiments, and those skilled in the art can make modifications or equivalent changes within the scope of the claims and all the modifications and equivalent changes should be included in the scope of the present invention.
Claims (4)
1. The utility model provides a two-way ESD protection circuit, connects to locate between the PIN PIN of chip supply terminal and the PIN GND of earthing terminal, its characterized in that: the diode is formed by connecting diodes D1 and PMOS tubes MP 1-MP 5, wherein the drains of the PMOS tubes MP1 and MP2 and the gates of MP4 are connected with a PIN PIN, the source and the drain of MP4 are connected with the gate of MP2 in a common way, the source of the PMOS tube MP1, the drain of MP3 and the gate of MP5 are connected with the cathode of the diode D1 at a node Vminus, the source and the drain of MP5 are connected with the gate of MP3 in a common way, the anode of the diode D1 is connected with the PIN GND and the common sources of the PMOS tubes MP2 and MP3, the gates of MP1 and the substrates of all PMOS tubes are connected with a node Vbody.
2. The bi-directional ESD protection circuit of claim 1, wherein: the transistor also comprises a resistor R1 connected between the grid electrode of the PMOS pipe MP1 and the node Vbody.
3. The bi-directional ESD protection circuit of claim 1, wherein: still include resistance R2, resistance R2's one end is connected with PIN PIN, and resistance R2's the other end is connected with PMOS pipe MP 5's source electrode.
4. The bi-directional ESD protection circuit of claim 1, wherein: the transistor also comprises a resistor R3, one end of the resistor R3 is connected to the node Vminus, and the other end of the resistor R3 is connected with the source electrode of the PMOS transistor MP 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011546107.8A CN112448380B (en) | 2020-12-24 | 2020-12-24 | Bidirectional ESD protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011546107.8A CN112448380B (en) | 2020-12-24 | 2020-12-24 | Bidirectional ESD protection circuit |
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| CN112448380A CN112448380A (en) | 2021-03-05 |
| CN112448380B true CN112448380B (en) | 2023-04-07 |
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| CN202011546107.8A Active CN112448380B (en) | 2020-12-24 | 2020-12-24 | Bidirectional ESD protection circuit |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2194578A1 (en) * | 2008-12-04 | 2010-06-09 | Imec | Bidirectional ESD power clamp |
| CN102801146A (en) * | 2012-08-24 | 2012-11-28 | 北京大学 | Power clamp ESD (Electronic Static Discharge) protective circuit |
| CN111599806A (en) * | 2020-05-18 | 2020-08-28 | 深圳市晶扬电子有限公司 | Low-power bidirectional SCR device for ESD protection and electrostatic protection circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100744123B1 (en) * | 2006-01-27 | 2007-08-01 | 삼성전자주식회사 | Esd protection circuit improving tolerance for electrostatic discharge |
| DE102006026691B4 (en) * | 2006-06-08 | 2018-02-01 | Infineon Technologies Ag | ESD protection circuit and method |
| TWI358872B (en) * | 2008-01-09 | 2012-02-21 | Chunghwa Picture Tubes Ltd | Two-way electrostatic discharge protection circuit |
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2020
- 2020-12-24 CN CN202011546107.8A patent/CN112448380B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2194578A1 (en) * | 2008-12-04 | 2010-06-09 | Imec | Bidirectional ESD power clamp |
| CN102801146A (en) * | 2012-08-24 | 2012-11-28 | 北京大学 | Power clamp ESD (Electronic Static Discharge) protective circuit |
| CN111599806A (en) * | 2020-05-18 | 2020-08-28 | 深圳市晶扬电子有限公司 | Low-power bidirectional SCR device for ESD protection and electrostatic protection circuit |
Non-Patent Citations (2)
| Title |
|---|
| 基于SOI工艺集成电路ESD保护网络分析与设计;胡永强等;《电子与封装》;20140331;第14卷(第3期);第29-32页 * |
| 曾庆贵等.全芯片ESD版图设计技术.《集成电路版图设计教程》.上海科学技术出版社,2012,第235-239页. * |
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| CN112448380A (en) | 2021-03-05 |
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