CN211789010U - High-speed switch circuit for eliminating parasitic capacitance of electrostatic discharge device - Google Patents
High-speed switch circuit for eliminating parasitic capacitance of electrostatic discharge device Download PDFInfo
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- CN211789010U CN211789010U CN202021000367.0U CN202021000367U CN211789010U CN 211789010 U CN211789010 U CN 211789010U CN 202021000367 U CN202021000367 U CN 202021000367U CN 211789010 U CN211789010 U CN 211789010U
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Abstract
The utility model discloses a eliminate electrostatic discharge device parasitic capacitance's high-speed switch circuit, include: the protection circuit comprises a first switch tube, a second switch tube, a first protection tube and a second protection tube; the first switch tube is connected with the second switch tube in parallel, the first protection tube is arranged at a body region node of the first switch tube, the second protection tube is arranged at a body region node of the second switch tube, and the first protection tube is connected with the second protection tube; the utility model discloses thoroughly eliminate parasitic capacitance to ground that electrostatic discharge device part brought to greatly reduced high frequency signal transmission decay.
Description
Technical Field
The utility model relates to a semiconductor integrated circuit device technical field, more specifically the high-speed switch circuit who relates to an elimination electrostatic discharge device parasitic capacitance that says so.
Background
Currently, high-speed switch Integrated Circuits (ICs) are a type of integrated circuits widely used in mobile portable devices, such as mobile industry processor interface switches, USB2.0, USB3.0 switches, and so on.
However, the esd protection schemes for high speed switch channels are usually diode protection schemes, and the prior art protection scheme is shown in fig. 1, where 1 is the input node of the high speed switch, 2 is the output node, 5 is the NMOS switch tube, 6 is the PMOS switch tube connected in parallel with the NMOS switch tube 5, and their source and drain terminals are connected to the circuit nodes 1 and 2, respectively, 3 is the esd protection device for the input terminal, 4 is the esd protection device for the output terminal, 7 and 8 are the parasitic diodes from the NMOS source and drain terminals to the NMOS body terminal, and 9 is the NMOS body terminal node. 10 and 11 are parasitic diodes from the NMOS source and drain terminals to the PMOS body terminal, respectively, and 12 is the PMOS body terminal node. When the circuit normally works, when a high-speed signal passes through the switch path of fig. 1, the parasitic capacitance of the switch tube to the ground and the parasitic capacitance of the electrostatic discharge device protection devices of the additional 3 and 4 are directly generated on the path from the input node to the output node, thereby affecting the overall performance of the circuit.
Therefore, how to provide a high-speed switch circuit capable of completely eliminating the parasitic capacitance of the electrostatic discharge device is a problem that needs to be solved by those skilled in the art.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model provides an eliminate electrostatic discharge device parasitic capacitance's high-speed switch circuit realizes that electrostatic discharge device's parasitic capacitance can not be seen completely to high-speed channel's input and output pin, thoroughly eliminates the parasitic capacitance to ground that electrostatic discharge device part brought to greatly reduced high frequency signal transmission decay has promoted high-speed switch's bandwidth.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
a high-speed switch circuit for eliminating parasitic capacitance of electrostatic discharge device includes: the protection circuit comprises a first switch tube, a second switch tube, a first protection tube and a second protection tube;
the first switch tube is connected with the second switch tube in parallel, the first protection tube is arranged at a body region node of the first switch tube, the second protection tube is arranged at a body region node of the second switch tube, and the first protection tube is connected with the second protection tube.
The beneficial effect who adopts above-mentioned device does: a first protection tube is added on a body region node of the first switch tube, and a second protection tube is added on a body region node of the second switch tube; when the circuit works normally, the parasitic capacitance caused by an additional protection device is eliminated on the path of the high-speed signal from the input node to the output node.
Preferably, the method further comprises the following steps: the first parasitic tube and the second parasitic tube are positioned between the source electrode and the body region node and between the drain electrode and the body region node of the first switch tube, and are parasitic diodes between the source electrode and the body region of the first switch tube and between the drain electrode and the body region respectively.
Preferably, the method further comprises the following steps: and the third parasitic tube and the fourth parasitic tube are positioned between the source electrode and the body region node and between the drain electrode and the body region node of the second switch tube, and are parasitic diodes between the source electrode and the body region of the second switch tube and between the drain electrode and the body region respectively.
According to the technical scheme, compare with prior art, the utility model discloses an eliminate static discharge device parasitic capacitance's high-speed switch circuit is provided, utilize the parasitic diode of the inherent district region of switch and source electrode and district region and drain electrode, add static discharge device protection device in the district region, make input node and output node need not any static discharge device pipe of direct connection on the high-speed channel and can realize that bidirectional protection has all eliminated extra static discharge device parasitic capacitance at input and output, and because static discharge device capacitance is one of the main factor that influences the high-speed switch bandwidth, can the switch channel that significantly reduces is to ground parasitic capacitance, thereby do not increase technology and circuit degree of difficulty when effectively promoting the signal bandwidth of passageway.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a diagram of a prior art protection circuit of the present invention;
fig. 2 is a schematic diagram of a high-speed switching circuit for eliminating parasitic capacitance of an electrostatic discharge device according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Example 1
Referring to fig. 2, embodiment 1 of the present invention discloses a high-speed switching circuit for eliminating parasitic capacitance of an electrostatic discharge device, wherein 1 is an input node of a high-speed switch, and 2 is an output node, and specifically includes: the protection circuit comprises a first switch tube 5, a second switch tube 6, a first protection tube 14 and a second protection tube 13, wherein the first switch tube 5 can be an NMOS switch tube, the second switch tube 6 can be a PMOS switch tube, 9 can be an NMOS body area node, and 12 can be a PMOS body area node;
the first switch tube 5 is connected in parallel with the second switch tube 6, specifically, the source electrode of the first switch tube 5 is connected with the drain electrode of the second switch tube 6, and the drain electrode of the first switch tube 5 is connected with the source electrode of the second switch tube 6; one end of the first protection tube 14 is arranged on the body region node 9 of the first switch tube 5, one end of the second protection tube 13 is arranged on the body region node 12 of the second switch tube, and the other end of the first protection tube 14 is connected with the other end of the second protection tube 13.
Specifically, the other end of the first protection tube 14 is grounded, and the other end of the second protection tube 13 is also connected to a power supply voltage.
Specifically, the second protection tube 13 may also be one or more ESD protection tubes connected in series in the same direction, and the connection mode is that the anode of the ESD protection tube is connected to the body region node 12 of the second switching tube 6, and the cathode is connected to the power supply voltage.
Specifically, the first protection tube 14 may also be an ESD protection tube formed by connecting one forward diode or a plurality of forward diodes in series, and the connection mode is that the anode of the ESD protection tube is connected to the body region node 9 of the first switching tube 5, and the cathode is grounded.
Specifically, a power-to-ground ESD clamp may be further disposed between the other end of the first protection tube 14 and the other end of the second protection tube 13, and functions as a protection circuit.
In a specific embodiment, the method further comprises the following steps: and one end of the grid control circuit 15 is connected with the grid of the first switch tube 5, the other end of the grid control circuit 15 is connected with the grid of the second switch tube 6, and the grid control circuit 15 is used for controlling the opening and closing of the N-type switch tube and the P-type switch tube.
In a specific embodiment, the method further comprises the following steps: the first parasitic tube 7 and the second parasitic tube 8, and the first parasitic tube 7 and the second parasitic tube 8 are disposed between the source and the drain of the first switch tube 5, and the specific connection mode is as follows: the negative electrode of the first parasitic tube 7 is connected with the source electrode of the first switch tube 5, the positive electrode of the first parasitic tube 7 is connected with the positive electrode of the second parasitic tube 8, and the negative electrode of the second parasitic tube 8 is connected with the drain electrode of the first switch tube 5.
In a specific embodiment, the method further comprises the following steps: the third parasitic tube 10 and the fourth parasitic tube 11, and the third parasitic tube 10 and the fourth parasitic tube 11 are disposed between the drain and the source of the second switch tube 6, and the specific connection mode is as follows: the positive electrode of the third parasitic tube 10 is connected with the drain electrode of the second switching tube 6, the negative electrode of the third parasitic tube 10 is connected with the negative electrode of the fourth parasitic tube 11, and the positive electrode of the fourth parasitic tube 11 is connected with the source electrode of the second switching tube 6.
In a specific embodiment, the method further comprises the following steps: a first switch body region bias circuit 16, which is disposed at the body region node 9 of the first switch tube 5, wherein the first switch tube body region bias circuit 16 may be an N-type switch body region bias circuit.
In a specific embodiment, the method further comprises the following steps: and the second switch tube body area biasing circuit 17, wherein the second switch tube body area biasing circuit 17 is arranged on the body area node 12 of the second switch tube 6, the first switch tube body area biasing circuit 17 may be a P-type switch tube body area biasing circuit, and the body area biasing circuit provides a body area biasing voltage according to the input and output signal potential.
Specifically, the gate control circuit 15, the first switch body region bias circuit 16, and the second switch body region bias circuit 17 are all common circuits in the prior art.
The utility model discloses a eliminate static discharge device parasitic capacitance's high-speed switch circuit when using, its output or output pin ESD release route circulation to ground as follows: because the source region and the drain region of the first switch tube 5 have reverse-biased PN junctions with the body region itself of itself, when one or more protection tubes equivalent to reverse-biased diode protection are connected in series between the body region P-well and the ground, an ESD unidirectional discharge path composed of series diodes is formed between the substrate ground and the source and the drain, when negative ESD occurs to the ground of the input or output pin, the ESD discharge current flows from the first protection tube 14 between the body region of the first switch tube 5 and the ground to the body region junction 9, and then flows to the input pin 1 through the first parasitic tube 7 of the body region and the drain or the source, because the whole discharge path is a forward-biased diode connected in series, the conduction voltage drop is also low, the ESD discharge capability is also strong, and effective negative ESD protection to the ground can be realized.
When the input pin is in positive ESD to ground, the ESD leakage current flows from the input pin 1 to the body region 12 through the parasitic forward biased PN junction between the source or drain of the second switch tube 6 and the body region, then flows from the body region to the power supply through the second protection tube 13 between the body region and the power supply, and finally flows from the power supply to ground through the ESD protection tube.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (3)
1. A high-speed switch circuit for eliminating parasitic capacitance of electrostatic discharge devices, comprising: the protection circuit comprises a first switch tube, a second switch tube, a first protection tube and a second protection tube;
the first switch tube is connected with the second switch tube in parallel, the first protection tube is arranged at a body region node of the first switch tube, the second protection tube is arranged at a body region node of the second switch tube, and the first protection tube is connected with the second protection tube.
2. The high-speed switching circuit for eliminating parasitic capacitance of electrostatic discharge devices according to claim 1, further comprising: the first parasitic tube and the second parasitic tube are positioned between the source electrode and the body area node and between the drain electrode and the body area node of the first switch tube.
3. The high-speed switching circuit for eliminating parasitic capacitance of electrostatic discharge devices according to claim 1, further comprising: the third parasitic tube and the fourth parasitic tube are positioned between the source electrode and the body area node and between the drain electrode and the body area node of the second switch tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021000367.0U CN211789010U (en) | 2020-06-03 | 2020-06-03 | High-speed switch circuit for eliminating parasitic capacitance of electrostatic discharge device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021000367.0U CN211789010U (en) | 2020-06-03 | 2020-06-03 | High-speed switch circuit for eliminating parasitic capacitance of electrostatic discharge device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211789010U true CN211789010U (en) | 2020-10-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021000367.0U Active CN211789010U (en) | 2020-06-03 | 2020-06-03 | High-speed switch circuit for eliminating parasitic capacitance of electrostatic discharge device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211789010U (en) |
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2020
- 2020-06-03 CN CN202021000367.0U patent/CN211789010U/en active Active
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Address after: 6 / F, building 8, Zilang science and Technology City, Nantong Innovation Zone, 60 Chongzhou Avenue, Nantong City, Jiangsu Province 226000 Patentee after: Jiangsu Dior Microelectronics Co., Ltd Address before: Room 501, building D, 1799 Wuzhong Road, Minhang District, Shanghai Patentee before: DIAO MICROELECTRONICS Co.,Ltd. |