CN113363253B - Silicon controlled rectifier layout structure of integrated reverse conducting diode - Google Patents
Silicon controlled rectifier layout structure of integrated reverse conducting diode Download PDFInfo
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- CN113363253B CN113363253B CN202110920348.2A CN202110920348A CN113363253B CN 113363253 B CN113363253 B CN 113363253B CN 202110920348 A CN202110920348 A CN 202110920348A CN 113363253 B CN113363253 B CN 113363253B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 11
- 239000010703 silicon Substances 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000002184 metal Substances 0.000 claims description 35
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 239000003990 capacitor Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
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- Semiconductor Integrated Circuits (AREA)
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Abstract
The invention provides a silicon controlled layout structure integrated with a reverse conducting diode, which comprises an N-type substrate, wherein a P-type well region for forming an SCR device is manufactured in the top area of the right part of the N-type substrate; an N-type well region for reducing the resistance of the reverse conducting diode is manufactured on the front side of the P-type well region in the N-type substrate; a first N + region and a first P + region which form anode contacts are formed in the N-type substrate outside the left side of the P-type well region and behind the N-type well region; the first N + region is arranged at the left side of the first P + region and is tangent with the first P + region; forming a second N + region and a second P + region forming a cathode contact in the P-type well region; the second N + region is arranged at the left side of the second P + region and is tangent with the second P + region; a third N + region is arranged at the boundary between the left boundary of the P-type trap region and the N-type substrate and is bridged; a fourth N + region and a fourth P + region for a reverse conducting diode D are manufactured in the N-type well region; the layout is simple, parasitic parameters are few, and the cost is low.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a Silicon Controlled Rectifier (SCR) integrated with a reverse conducting diode.
Background
Electrostatic discharge (ESD) is ubiquitous in the processes of manufacturing, packaging, testing and using chips, accumulated static charges are released in a nanosecond-microsecond time by a current of several amperes or dozens of amperes, instantaneous power is up to dozens or hundreds of watts, and the destruction strength of the ESD (electrostatic discharge) to the chips in a circuit system is very high. Statistically, more than 35% of chip failures are due to ESD damage. Therefore, in the design of chips or systems, the design of the esd protection module is directly related to the functional stability of the circuit system and the system reliability, and is very important for electronic products. TVSs are core devices for system-level ESD/EOS protection, the performance of which is critical to the reliability of an electronic system.
For the unidirectional array TVS protection circuit, a negative electric pulse test is required besides positive ESD/EOS protection, and the SCR with the reverse conducting diode can bear higher negative pulse energy because the reverse conducting diode can greatly reduce the reverse resistance. The reverse diode is essentially an additional device, and the layout thereof is very important for the overall cost of the chip or the reverse ESD performance.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a silicon controlled rectifier layout structure integrated with a reverse conducting diode, wherein in the layout, the reverse conducting diode and an SCR device are integrated in the same N-type substrate, isolation under certain voltage is realized through reverse bias junction of the reverse conducting diode, and meanwhile, the SCR and the reverse conducting diode are connected through only one layer of metal to form a required circuit; the layout is simple, parasitic parameters are few, the cost is low, and the method is suitable for design and expansion of the SCR device. In order to achieve the technical purpose, the embodiment of the invention adopts the technical scheme that:
the embodiment of the invention provides a silicon controlled layout structure integrated with a reverse conducting diode, which comprises an N-type substrate, wherein a P-type well region for forming an SCR device is manufactured in the top region of the right part of the N-type substrate; an N-type well region for reducing the resistance of the reverse conducting diode is manufactured on the front side of the P-type well region in the N-type substrate; a first N + region and a first P + region which form anode contacts are formed in the N-type substrate outside the left side of the P-type well region and behind the N-type well region; the first N + region is arranged at the left side of the first P + region and is tangent with the first P + region; forming a second N + region and a second P + region forming a cathode contact in the P-type well region; the second N + region is arranged at the left side of the second P + region and is tangent with the second P + region;
a third N + region is arranged at the boundary between the left boundary of the P-type trap region and the N-type substrate and is bridged;
a fourth N + region and a fourth P + region for a reverse conducting diode D are manufactured in the N-type well region;
contact holes used for being connected with the metal layer are formed in the first N + region, the first P + region, the second N + region, the second P + region, the third N + region, the fourth N + region and the fourth P + region;
the first N + region and the first P + region are connected with SCR anode metal through contact holes to form an SCR device anode A; the second N + region and the second P + region are connected with SCR cathode metal through contact holes to form an SCR device cathode K; the third N + region and a fourth P + region in the N-type well region are respectively connected with the intermediate metal through contact holes; and a fourth N + region in the N-type well region is connected with the SCR anode metal through a contact hole.
Further, the SCR anode metal, the SCR cathode metal and the intermediate metal are located in the same layer.
Further, inside the N-type well region, a fourth N + region is located in a front half portion of the N-type well region, and a fourth P + region is located in a rear half portion of the N-type well region.
Furthermore, inside the N-type well region, a reverse conducting diode D region adopts a longitudinal finger layout, and a plurality of fourth N + regions and fourth P + regions are alternately arranged in the N-type well region from left to right.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
after the layout of the application is adopted, the reverse conducting diode can obtain very low resistance, meanwhile, a reverse voltage-resistant junction of the reverse conducting diode is formed by an N-type well region and a fourth P + region, enough voltage resistance can be provided for electrical isolation between the SCR and the reverse conducting diode, and meanwhile, the layout only uses one layer of metal and the same layout number as that of a conventional SCR, so that the cost is reduced to the maximum extent; because the reverse conducting diode is still made in the N-type substrate, the fourth P + region and the substrate do not have extra parasitic capacitance except the junction capacitance.
Drawings
Fig. 1 is a schematic diagram of an SCR structure of an integrated reverse conducting diode according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of a layout structure in the first embodiment of the present invention.
Fig. 3 is a schematic diagram of a layout structure in the second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Embodiment one, as shown in fig. 1 and fig. 2;
the embodiment provides a silicon controlled layout structure integrated with a reverse conducting diode, which comprises an N-type substrate 1, wherein a P-type well region 2 for forming an SCR device is manufactured in the top region of the right part of the N-type substrate 1; in the N-type substrate 1, an N-type well region 3 for reducing the reverse diode resistance is formed on the front side (the lower side is defined as the front side in the orientation of fig. 2) of the P-type well region 2; a first N + region 401 and a first P + region 501 which form anode contacts are manufactured in the N-type substrate 1 at the rear side of the N-type well region 3 outside the left side of the P-type well region 2; the first N + region 401 is to the left of the first P + region 501 and is tangent to both; inside the P-type well region 2, a second N + region 402 and a second P + region 502 forming a cathode contact are formed; the second N + region 402 is to the left of the second P + region 502 and is tangent to both;
a third N + region 403 is arranged at the left boundary of the P-type well region 2 and the boundary of the N-type substrate 1 and bridged at the boundary;
inside the N-type well region 3, a fourth N + region 404 for a reverse conducting diode D is formed in the first half, and a fourth P + region 504 for a reverse conducting diode D is formed in the second half;
contact holes 6 for connecting with a metal layer are formed in the first N + region 401, the first P + region 501, the second N + region 402, the second P + region 502, the third N + region 403, the fourth N + region 404 and the fourth P + region 504;
the first N + region 401 and the first P + region 501 are connected with SCR anode metal 7 through a contact hole 6 to form an SCR device anode A; the second N + region 402 and the second P + region 502 are connected with the SCR cathode metal 8 through the contact hole 6 to form an SCR device cathode K; the third N + region 403 and the fourth P + region 504 in the N-type well region 3 are respectively connected with the intermediate metal 9 through the contact hole 6; a fourth N + region 404 in the N-type well region 3 is connected with the SCR anode metal 7 through a contact hole 6;
preferably, the SCR anode metal 7, the SCR cathode metal 8 and the intermediate metal 9 are located in the same layer;
the working principle is that when the capacitor of the SCR device is tested in the forward direction, the N-type well region 3/fourth P + region 504 capacitor of the reverse conducting diode D is short-circuited by the N-type substrate 1 of the SCR, so that the influence on the whole capacitor is small; on the other hand, when negative ESD/EOS energy appears, current flows to the reverse conducting diode D through the middle metal 9 through a diode formed by the second P + region 502, the P-type well region 2 and the bridged third N + region 403 at the cathode end of the SCR, and the width-length ratio of the reverse conducting diode is designed to be larger, and the distance between the anode and the cathode is designed to be very close, so that the negative resistance can be greatly reduced, and the negative ESD/EOS performance is improved.
Embodiment two, as shown in fig. 1 and 3;
the embodiment provides a silicon controlled layout structure integrated with a reverse conducting diode, which comprises an N-type substrate 1, wherein a P-type well region 2 for forming an SCR device is manufactured in the top region of the right part of the N-type substrate 1; in the N-type substrate 1, an N-type well region 3 for reducing the reverse diode resistance is formed on the front side (the lower side is defined as the front side in the orientation of fig. 2) of the P-type well region 2; a first N + region 401 and a first P + region 501 which form anode contacts are manufactured in the N-type substrate 1 at the rear side of the N-type well region 3 outside the left side of the P-type well region 2; the first N + region 401 is to the left of the first P + region 501 and is tangent to both; inside the P-type well region 2, a second N + region 402 and a second P + region 502 forming a cathode contact are formed; the second N + region 402 is to the left of the second P + region 502 and is tangent to both;
a third N + region 403 is arranged at the left boundary of the P-type well region 2 and the boundary of the N-type substrate 1 and bridged at the boundary;
inside the N-type well region 3, the reverse conducting diode D region adopts a longitudinal finger layout, and includes a plurality of fourth N + regions 404 and fourth P + regions 504 alternately arranged from left to right in the N-type well region 3; in fig. 3, a fourth N + region 404, a fourth P + region 504, and a fourth N + region 404 are exemplarily drawn to alternate from left to right; actually, more fourth N + regions 404 and fourth P + regions 504 may be provided as required;
contact holes 6 for connecting with a metal layer are formed in the first N + region 401, the first P + region 501, the second N + region 402, the second P + region 502, the third N + region 403, the fourth N + region 404 and the fourth P + region 504;
the first N + region 401 and the first P + region 501 are connected with SCR anode metal 7 through a contact hole 6 to form an SCR device anode A; the second N + region 402 and the second P + region 502 are connected with the SCR cathode metal 8 through the contact hole 6 to form an SCR device cathode K; the third N + region 403 and the fourth P + region 504 in the N-type well region 3 are respectively connected with the intermediate metal 9 through the contact hole 6; a fourth N + region 404 in the N-type well region 3 is connected with the SCR anode metal 7 through a contact hole 6;
preferably, the SCR anode metal 7, the SCR cathode metal 8 and the intermediate metal 9 are located in the same layer;
the working principle is that when the capacitor of the SCR device is tested in the forward direction, the N-type well region 3/fourth P + region 504 capacitor of the reverse conducting diode D is short-circuited by the N-type substrate 1 of the SCR, so that the influence on the whole capacitor is small; on the other hand, when negative ESD/EOS energy is present, the current channel is wider, the parasitic resistance is lower, and the current capability is stronger because more fourth N + regions 404 and fourth P + regions 504 can be placed in the finger layout.
In summary, the layout of the thyristor integrated with the reverse conducting diode provided by the application can well solve the problems of parasitic capacitance of the substrate of the reverse conducting diode, isolation and process compatibility. The compact layout and the electrical isolation are realized under the conditions that no mask is added and no additional process flow is required. On the other hand, the reverse conducting diode layout with high width-length ratio can realize better negative current performance and has little influence on input capacitance.
Finally, it should be noted that the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to examples, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (3)
1. A silicon controlled layout structure of an integrated reverse conducting diode comprises an N-type substrate (1), and is characterized in that a P-type well region (2) for forming an SCR device is manufactured in the top area of the right side part of the N-type substrate (1); an N-type well region (3) is manufactured on the front side of a P-type well region (2) in an N-type substrate (1); a first N + region (401) and a first P + region (501) which form anode contact are manufactured in the N-type substrate (1) outside the left side of the P-type well region (2) and behind the N-type well region (3); the first N + region (401) is at the left side of the first P + region (501) and is tangent to the two; forming a second N + region (402) and a second P + region (502) which form a cathode contact in the P-type well region (2); the second N + region (402) is to the left of the second P + region (502) and is tangent to both;
a third N + region (403) is arranged at the left boundary of the P-type well region (2) and the boundary of the N-type substrate (1) in a bridging mode;
a fourth N + region (404) and a fourth P + region (504) for a reverse conducting diode D are manufactured in the N-type well region (3);
contact holes (6) used for being connected with the metal layer are formed in the first N + region (401), the first P + region (501), the second N + region (402), the second P + region (502), the third N + region (403), the fourth N + region (404) and the fourth P + region (504);
the first N + region (401) and the first P + region (501) are connected with SCR anode metal (7) through a contact hole (6) to form an SCR device anode A; the second N + region (402) and the second P + region (502) are connected with SCR cathode metal (8) through a contact hole (6) to form an SCR device cathode K; the third N + region (403) and a fourth P + region (504) in the N-type well region (3) are respectively connected with the intermediate metal (9) through a contact hole (6); a fourth N + region (404) in the N-type well region (3) is connected with SCR anode metal (7) through a contact hole (6);
the SCR anode metal (7), the SCR cathode metal (8) and the intermediate metal (9) are positioned in the same layer.
2. The silicon controlled rectifier layout structure of integrated reverse conducting diode of claim 1,
inside the N-type well region (3), a fourth N + region (404) is positioned in the front half part of the N-type well region (3), and a fourth P + region (504) is positioned in the rear half part of the N-type well region (3).
3. The silicon controlled rectifier layout structure of integrated reverse conducting diode of claim 1,
in the N-type well region (3), a reverse conducting diode D region adopts a longitudinal finger layout, and a plurality of fourth N + regions (404) and fourth P + regions (504) are alternately arranged in the N-type well region (3) from left to right.
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| CN102569360A (en) * | 2012-03-09 | 2012-07-11 | 浙江大学 | Bidirectional triode thyristor based on diode auxiliary triggering |
| CN104600104A (en) * | 2014-12-12 | 2015-05-06 | 上海贝岭股份有限公司 | Controllable silicon structure with high sustaining voltage |
| CN107731810A (en) * | 2017-09-06 | 2018-02-23 | 电子科技大学 | A kind of low trigger voltage MLSCR devices for ESD protection |
| CN211507641U (en) * | 2020-02-21 | 2020-09-15 | 上海维安半导体有限公司 | Novel silicon controlled rectifier device with low-clamping embedded capacitor-reducing diode |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20110133247A1 (en) * | 2009-12-08 | 2011-06-09 | Hossein Sarbishaei | Zener-Triggered SCR-Based Electrostatic Discharge Protection Devices For CDM And HBM Stress Conditions |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569360A (en) * | 2012-03-09 | 2012-07-11 | 浙江大学 | Bidirectional triode thyristor based on diode auxiliary triggering |
| CN104600104A (en) * | 2014-12-12 | 2015-05-06 | 上海贝岭股份有限公司 | Controllable silicon structure with high sustaining voltage |
| CN107731810A (en) * | 2017-09-06 | 2018-02-23 | 电子科技大学 | A kind of low trigger voltage MLSCR devices for ESD protection |
| CN211507641U (en) * | 2020-02-21 | 2020-09-15 | 上海维安半导体有限公司 | Novel silicon controlled rectifier device with low-clamping embedded capacitor-reducing diode |
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Address after: Building 4 (8th and 9th floor), No. 5 Chuangzhi Road, Tianning District, Changzhou City, Jiangsu Province, 213000 Patentee after: Jiangsu Yingneng Microelectronics Co.,Ltd. Address before: 213002 building 8-5, Huashan Road, Xinbei District, Changzhou City, Jiangsu Province Patentee before: JIANGSU APPLIED POWER MICROELECTRONICS Co.,Ltd. |