CN219123236U

CN219123236U - Electrostatic protection device and electrostatic protection circuit based on silicon-controlled diode

Info

Publication number: CN219123236U
Application number: CN202223517005.0U
Authority: CN
Inventors: 赖大伟; 王迪; 邹池佳; 郑飞君
Original assignee: Hangzhou Aoxin Technology Co ltd
Current assignee: Hangzhou Aoxin Technology Co ltd
Priority date: 2022-12-28
Filing date: 2022-12-28
Publication date: 2023-06-02
Anticipated expiration: 2032-12-28

Abstract

The utility model discloses an electrostatic protection device and an electrostatic protection circuit based on a silicon-controlled diode, wherein the electrostatic protection device comprises: a semiconductor substrate; a deep buried layer isolation region embedded into the semiconductor substrate; the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region are sequentially arranged on the deep buried layer isolation region; the shallow trench isolation areas are sequentially arranged at the upper half parts of the interfaces of the first N-type doped area, the first P-type doped area, the second N-type doped area and the second P-type doped area, and the four areas are isolated on the surface layer; a third N-type doped region, a third P-type doped region, a fourth P-type doped region and a fourth N-type doped region are sequentially arranged on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region from left to right; the grounding end is electrically connected with the semiconductor substrate through the fifth P-type doped region; the input end is electrically connected with the semiconductor substrate through the fourth P-type doped region; and an output terminal.

Description

Electrostatic protection device and electrostatic protection circuit based on silicon-controlled diode

Technical Field

The utility model belongs to the technical field of electronic chips, and particularly relates to an electrostatic protection device and an electrostatic protection circuit based on a silicon-like diode.

Background

Electrostatic discharge is a common cause of reliability problems in integrated circuits, and ESD protection devices can quickly respond when electrostatic discharge occurs, providing a low-impedance path for the instantaneous energy of the static electricity, and improving the reliability of the integrated circuit. The ESD protection device is widely used in various electronic products, the requirements of the non-passing components on the ESD protection device are different, the high-definition digital interface (High Definition Multimedia Interface, HDMI), the universal serial bus (Universal Serial Bus, USB), the Ethernet (Ethernet) and the like have very high transmission rate, and the ESD protection unit is connected in parallel with the protected unit, so that the protection principle is as shown in fig. 1, the smaller the capacitance of the ESD protection unit is, the better the interference on the protected device is required to be reduced. For an ESD protection device, the size of the capacitor is directly related to the junction area of the ESD protection unit, and the smaller the junction area is, the smaller the capacitor is; however, in order to have a large ESD capability, a large junction area is required, so a high ESD capability and a low capacitance requirement are major contradictions of ESD protection.

In order to reduce the capacitance of the ESD diode, a low-capacitance diode is often integrated in the ESD protection device in the conventional process, so that the low-capacitance diode is connected in series with the ESD protection unit, and the larger the number of series connection is, the smaller the capacitance is, as shown in fig. 2 and fig. 3, which are schematic diagrams of internal circuits of the conventional unidirectional ESD protection device and the bidirectional ESD protection device, respectively. The new ESD protection unit is composed of D1, D2 and ESD/TVS in series-parallel connection, the unit capacitance is determined by the sum of the capacitance values of two low-capacitance diodes, different connecting lines are adopted according to the requirement, and a bidirectional or unidirectional ESD protection unit or a 4-channel or 8-channel ESD protection unit is formed. The method for reducing the capacitance by the serial diode has two implementation methods, namely, the diode is integrated on a chip, and the serial connection can be carried out by connecting the diode through a copper wire during packaging. Whether the series diode is integrated in an Integrated Circuit (IC) or the copper wire series diode is adopted in a packaging body, the series diode can lead in a bulk resistor, so that the clamping voltage of an ESD protection device is increased, the protection function cannot be effectively realized, and the more the series diodes, the larger the resistance is; the method of connecting the copper wires in series during packaging is adopted, so that not only the body resistance of the diode is introduced, but also the copper wire resistance is introduced, the overall ESD drainage capacity is obviously reduced, the packaging size is correspondingly increased, and the cost is increased as more diodes are connected in series. So that typically only one diode can be connected in series.

In the process of implementing the ESD protection unit, various devices are used, and a commonly used silicon controlled rectifier (Silicon Controlled Rectifier, SCR), GGNMOS, diode, etc. are used, and the current capability of the SCR, GGNMOS, diode is sequentially reduced.

The SCR structure generally consists of PNPN, equivalent two forward diodes are connected in series, the capacitance is half of that of a single diode, the SCR structure is shown in fig. 4, the SCR current capability is strong, the current capability of the SCR structure is about twice that of the forward diode under the same condition, but the trigger voltage of the whole ESD device is overlarge due to the existence of NW-PW reverse diode, and the IV curve has the phenomenon of reverse (snapback), which causes the problem that latch up is easy to occur, the application requirement cannot be met, and the parasitic IV curve is shown in fig. 5.

Although the SCR structure has a relatively low capacitance and a relatively high current capability, the SCR structure can cause an excessive trigger voltage of the whole ESD device due to the NWPW reverse diode, and the IV curve of the SCR structure has a phenomenon of reverse (snapback), which can cause a problem that latch up is easy to occur, and cannot meet application requirements.

Disclosure of Invention

In view of the above, the present utility model provides an electrostatic protection device and an electrostatic protection circuit based on a silicon-like diode, which are used for reducing the capacitance of an ESD protection unit and increasing the ESD capability thereof.

In order to solve the technical problems, the utility model adopts the following technical scheme:

in a first aspect, the present utility model provides a silicon-like diode based electrostatic protection device comprising:

a semiconductor substrate;

a deep buried layer isolation region embedded into the semiconductor substrate;

the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region are sequentially arranged on the deep buried layer isolation region;

the shallow trench isolation areas are sequentially arranged at the upper half parts of the interfaces of the first N-type doped area, the first P-type doped area, the second N-type doped area and the second P-type doped area, and the four areas are isolated on the surface layer;

and a third N-type doped region, a third P-type doped region, a fourth P-type doped region and a fourth N-type doped region are sequentially arranged on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region from left to right.

The grounding end is electrically connected with the semiconductor substrate through the fifth P-type doped region;

the input end is electrically connected with the semiconductor substrate through the fourth P-type doped region;

the output end is electrically connected with the semiconductor substrate through the third N-type doped region.

In one possible embodiment, the ground terminal is electrically connected to the semiconductor substrate through the third P-type doped region.

In one possible embodiment, the input terminal is electrically connected to the semiconductor substrate through the third P-type doped region.

In one possible embodiment, the power terminal is electrically connected to the semiconductor substrate through the third P-type doped region.

In a possible implementation manner, the semiconductor device further comprises a forward diode, wherein the ground terminal is electrically connected with the positive electrode of the forward diode, and the negative electrode of the forward diode is electrically connected with the semiconductor substrate through the third N-type doped region.

In one possible embodiment, the semiconductor substrate is a P-type semiconductor substrate; the P-type epitaxial layer is formed on the N-type semiconductor substrate in an epitaxial manner, or the P-type epitaxial layer is formed on the N-type semiconductor substrate in an epitaxial manner:

in a second aspect, the present utility model provides a rail-based ESD electrostatic protection circuit, where two or more diodes connected end to end are used in series between PAD and VDD, the anode of the diode is connected to PAD, the cathode is connected to VDD, and the electrostatic charge of PAD is discharged to VDD; two or more diodes connected in series from PAD to VSS at the first position are used, the anode of each diode is connected to VSS, the cathode of each diode is connected to PAD, and static electricity of the PAD is discharged to VSS; the voltage between VDD and VSS is connected by using a transient voltage suppression diode, static electricity between VDD and VSS is discharged, and the diode and the transient voltage suppression diode adopt the electrostatic protection device based on the similar silicon controlled diode.

In a possible embodiment, the diodes are connected in series such that the output of the last scr-based electrostatic protection device is connected to the input of the next scr-based electrostatic protection device.

In a third aspect, the present utility model provides an ESD electrostatic protection circuit for a local floating rail, where two or more diodes connected first are connected in series between a PAD and an ESDP, an anode of the diode is connected to the PAD, a cathode of the diode is connected to the ESDP, and positive static electricity of the PAD is discharged to the ESDP; two or more diodes connected in series from PAD to ESDN are arranged between the PAD and the ESDN, the anode of each diode is connected to the ESDN, the cathode of each diode is connected to the PAD, and negative static electricity of the PAD is discharged to the ESDN; the ESDP to ESDN are connected by using a transient voltage suppression diode, and positive electrostatic pulse between VDD and VSS is discharged, wherein the diode or the transient voltage suppression diode adopts the electrostatic protection device based on the similar silicon controlled diode.

In one possible implementation, the diodes are connected in series: the output end of the last electrostatic protection device based on the silicon-controlled diode is connected with the input end of the next electrostatic protection device based on the silicon-controlled diode.

The utility model has the following beneficial effects: the utility model provides a novel electrostatic protection device based on a silicon-like diode, wherein two (or more) internally connected and serially connected forward diode structures replace a single diode D1 or D2 in the traditional process, and for convenience of expression, the structure of connecting two or more forward diodes in series is defined as a diode-like silicon-like structure: diode-Like SCR, abbreviated as DL-SCR). The DL-SCR is formed by connecting P/NW (first forward diode) and PW/N (second forward diode) in vivo, and the DL-SCR is surrounded by P/PW+N/NW+DNW for isolation, so that parasitic effect of the DL-SCR and other devices is removed, the DL-SCR does not generate snapback effect, and the capacitance of the DL-SCR is half that of a single diode due to the fact that two diodes are connected in series. The structure Pad is connected with the P area, the VDD is connected with the N area, and the structure Pad and the ESD/TVS protection unit are integrated on one chip by using a metal connection wire, wherein the path is responsible for a forward ESD pulse path. The negative-going ESD pulse path is discharged through the other DL-SCR structure. The low-capacitance structure of the series-parallel connection is one time lower than that of the low-capacitance diode of the traditional technology, so that the capacitance of the whole structure is one time lower than that of the traditional method. Meanwhile, the DL-SCR is changed from a low-current-capability forward diode structure of the traditional method to a high-current-capability SCR structure due to the structure of the SCR, and the resistance value of the unit area is correspondingly reduced. On the premise of not increasing the cost and losing the performance, the design requirement of low capacitance is achieved. The utility model not only reduces the capacitance, but also improves the overall ESD capacity of the module and reduces the clamping voltage of the module. Therefore, the utility model has important breakthrough in improving the contradiction between ESD protection capability and capacitance.

Drawings

FIG. 1 is a schematic diagram of a prior art ESD protection circuit;

FIG. 2 is a schematic diagram of a prior art unidirectional ESD protection circuit;

FIG. 3 is a schematic diagram of a prior art bi-directional ESD protection circuit;

FIG. 4 is a schematic diagram of an equivalent circuit of a SCR in the prior art;

FIG. 5 is a graph of the parasitic generation IV of an SCR equivalent circuit in the prior art;

FIG. 6 is a schematic diagram of an electrostatic protection device based on a silicon-like diode according to embodiment 1 of the present utility model;

FIG. 7 is a schematic diagram of an electrostatic protection device based on a silicon-like diode according to embodiment 2 of the present utility model;

FIG. 8 is a schematic diagram of an electrostatic protection device based on a silicon-like diode according to embodiment 3 of the present utility model;

FIG. 9 is a schematic diagram of an electrostatic protection device based on a silicon-like diode according to embodiment 4 of the present utility model;

FIG. 10 is a schematic diagram of an electrostatic protection device based on a silicon-like diode according to embodiment 5 of the present utility model;

FIG. 11 is a schematic diagram of a rail-based ESD protection circuit of embodiment 6 of the present utility model;

fig. 12 is a schematic diagram of an ESD electrostatic protection circuit for a local floating rail according to embodiment 7 of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Example 1

Referring to fig. 6, there is shown an electrostatic protection device based on a silicon-like diode according to an embodiment of the present utility model, and the upper right part of fig. 6 includes:

a semiconductor substrate (P-sub);

deep buried isolation regions (DNWs) embedded into the semiconductor substrate;

the first N-type doped region (NW), the first P-type doped region (PW), the second N-type doped region (NW) and the second P-type doped region (PW) are sequentially arranged on the deep buried layer isolation region;

a plurality of Shallow Trench Isolation (STI) regions, which are sequentially arranged at the upper half parts of the interfaces of the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region, and isolate the four regions on the surface layer;

a third N-type doped region, a third P-type doped region, a fourth P-type doped region and a fourth N-type doped region are sequentially arranged on the first N-type doped region, the first P-type doped region, the second N-type doped region and the second P-type doped region from left to right;

a ground terminal (Gnd) electrically connected to the semiconductor substrate through the fifth P-type doped region;

an input terminal (Vin) electrically connected to the semiconductor substrate through the fourth P-type doped region;

the output terminal (Vout) is electrically connected with the semiconductor substrate through the third N-type doped region.

In the structure, the DL-SCR is formed by connecting P/NW/PW/N internally, wherein an input end is arranged above the P/NW, and an output end is arranged above the N/PW. The DL-SCR is positioned in an isolation region consisting of N/NW+DNW+P/PW, the P/PW is positioned between the P/NW and the N/NW, and the N/NW+DNW+P/PW is suspended and does not lead out any electrode. All the above structures are located on a P-Sub which leads through P to Gnd. The structure can be repeatedly changed into multiple channels according to application requirements. As shown for two channels, PAD1 and PAD2 are equivalent.

In practical application, as shown in the left part of the circuit of FIG. 6, the upward SCR1 is replaced by DL-SCR, the input end of the DL-SCR is connected with PAD, the output end is linked with VDD, and the GND electrode is grounded; the downward SCR2 is replaced by DL-SCR, the input end of the DL-SCR is connected with Gnd, the output end of the DL-SCR is connected with PAD, and the VSS electrode and the GND electrode are both grounding electrodes.

When the forward ESD pulse occurs in the PAD1 or the PAD2, the current path flows to the upper DL-SCR structure through the PAD1 or the PAD2, the current path in the DL-SCR is P- & gtNW- & gtPW- & lt N, then flows to the ESD/TVS unit through the VDD, and finally flows to the VSS bleeder.

When negative ESD pulse occurs in PAD1 or PAD2, the current path flows into the lower series DL-SCR structure through VSS, and the current path in the structure is P- & gtNW- & gtPW- & gtN, and then flows into the PAD for discharging.

When a forward ESD occurs between VSS and VDD, there are two current paths, the first path is the parasitic SCR3 of DL-SCR: P-sub-DNW-PW-N, and the other path is the forward direction of the ESD/TVS. There is only one bleed path from VSS to PAD, which is vss→p→nw pw→n→pad described in SCR 2. In a specific application example, the semiconductor substrate is a P-type semiconductor substrate; the N-type semiconductor substrate is epitaxially provided with a P-type epitaxial layer or the N-type semiconductor substrate is epitaxially provided with a P-type epitaxial layer.

Example 2

On the basis of embodiment 1, referring to fig. 7, a silicon-like diode based electrostatic protection device according to still another embodiment of the present utility model includes:

a semiconductor substrate;

a deep buried layer isolation region embedded into the semiconductor substrate;

the output end is electrically connected with the semiconductor substrate through the third N-type doped region;

the grounding end is electrically connected with the semiconductor substrate through the third P-type doped region.

In the structure, the DL-SCR is formed by connecting P/NW/PW/N internally, wherein an input end is arranged above the P/NW, and an output end is arranged above the N/PW. The DL-SCR is positioned in an isolation region consisting of N/NW+DNW+P/PW, the P/PW is positioned between the P/NW and the N/NW, the N/NW+DNW is suspended, the P/PW is led out to a ground Gnd electrode, and the current leakage path of the forward ESD pulse of VSS can be increased. All the above structures are located on the P-Sub, which leads out the ground Gnd electrode through P. The structure can be repeatedly changed into multiple channels according to application requirements, such as two channels in the figure, and PAD1 and PAD2 are equivalent.

In practical application, as shown in the circuit of FIG. 7, the upward SCR1 is replaced by DL-SCR, the input end of DL-SCR is connected with PAD, the output end is linked with VDD, and GND electrode is grounded; the downward SCR2 is replaced by DL-SCR, the input end of the DL-SCR is connected with Gnd, the output end of the DL-SCR is connected with PAD, and the VSS electrode and the GND electrode are both grounding electrodes.

When the forward ESD occurs in the PAD1 or the PAD2, the current path flows to the upper DL-SCR structure through the PAD1 or the PAD2, the current path in the low-capacity structure is P- & gtNW- & gtPW- & lt N, then flows to the ESD/TVS device through the VDD, and finally flows to the VSS for discharging.

When negative ESD occurs in PAD1 or PAD2, the current path flows into the lower series DL-SCR structure through VSS, and the current path in the structure is P- & gtNW- & gtPW- & gtN, and then flows into the PAD for discharging.

When VSS has a positive ESD pulse, there are two current paths from VSS to VDD, the first path is SCR3 parasitic to DL-SCR: P-sub-DNW-PW-N, and the other path is the forward direction of the ESD/TVS. There is only one bleed path from VSS to PAD, which is vss→p→nw pw→n→pad described in SCR 2.

Example 3

Based on embodiment 1, referring to fig. 8, an electrostatic protection device based on a silicon-like diode according to an embodiment of the present utility model includes:

a semiconductor substrate;

a deep buried layer isolation region embedded into the semiconductor substrate;

the input end is electrically connected with the semiconductor substrate through the third P-type doped region.

In the structure, the DL-SCR is formed by connecting P/NW/PW/N internally, wherein an input end is arranged above the P/NW, and an output end is arranged above the N/PW. The DL-SCR is positioned in an isolation area formed by N/NW+DNW+P/PW, the P/PW is positioned between the P/NW and the N/NW, the N/NW+DNW floats, the P/PW is short-circuited to the input end, and a current discharge path of forward ESD pulse at the input end can be increased. All of the above structures are located on a P-Sub that leads out of the Vss electrode through P. The structure can be repeatedly changed into multiple channels according to application requirements, such as two channels in the figure, and PAD1 and PAD2 are equivalent.

In practical application, as shown in the circuit of FIG. 8, the upward SCR1 is replaced by DL-SCR, the input end of DL-SCR is connected with PAD, the output end is linked with VDD, and GND electrode is grounded; the downward SCR2 is replaced by DL-SCR, the input end of the DL-SCR is connected with Gnd, the output end of the DL-SCR is connected with PAD, and the VSS electrode and the GND electrode are both grounding electrodes.

When a positive ESD occurs at PAD1 or PAD2, there are two current paths, one is:

PAD, P, PW, DNW, PW, N and VDD; the other path is: PAD→P→NW→PW→N→VDD, then flows to the ESD/TVS device through VDD, and finally flows to VSS bleeder.

When negative ESD occurs in PAD1 or PAD2, the current path flows into the lower serial low-capacitance structure through VSS, and the current path in the structure is P- & gtNW- & gtPW- & gtN, and then flows into the PAD for discharging.

Example 4

Referring to fig. 9, there is shown an electrostatic protection device based on a silicon-like diode according to an embodiment of the present utility model, including:

a semiconductor substrate;

a deep buried layer isolation region embedded into the semiconductor substrate;

the output end is electrically connected with the semiconductor substrate through the third N-type doped region and is also electrically connected with the semiconductor substrate through the third P-type doped region.

The DL-SCR is isolated by P/PW+N/NW+DNW, and in the structure, the DL-SCR is formed by connecting P/NW/PW/N internally, wherein an input end is arranged above P/NW, and an output end is arranged above N/PW. The DL-SCR is positioned in an isolation area consisting of N/NW+DNW+P/PW, the P/PW is positioned between the P/NW and the N/NW, the N/NW+DNW floats, the P/PW is led out to an output end, and a negative pulse discharge path from the input end to the output end is added. All of the above structures are located on a P-Sub that leads out of the Vss electrode through P. The structure can be repeatedly changed into multiple channels according to application requirements, such as two channels in the figure, and PAD1 and PAD2 are equivalent.

In practical application, as shown in the circuit of FIG. 9, the upward SCR1 is replaced by DL-SCR, the input end of DL-SCR is connected with PAD, the output end is linked with VDD, and GND electrode is grounded; the downward SCR2 is replaced by DL-SCR, the input end of the DL-SCR is connected with Gnd, the output end of the DL-SCR is connected with PAD, and the VSS electrode and the GND electrode are both grounding electrodes.

When the positive ESD occurs in the PAD1 or PAD2, the current path is as follows: PAD→P→NW→PW→N→VDD, then flows to the ESD/TVS device through VDD, and finally flows to VSS bleeder.

When negative ESD occurs in PAD1 or PAD2, three current discharge paths are provided, one current path flows into the lower serial low-capacity structure through VSS, and the current paths in the structure are VSS, P, NW, PW, N, PAD and flow into the PAD for discharge. Another current path is VDD

Example 5

Referring to fig. 10, there is shown an electrostatic protection device based on a silicon-like diode according to an embodiment of the present utility model, including:

a semiconductor substrate;

a deep buried layer isolation region embedded into the semiconductor substrate;

the grounding end of the forward diode is electrically connected with the positive electrode of the forward diode, and the negative electrode of the forward diode is electrically connected with the semiconductor substrate through the third N-type doped region. The forward diode may be a clamp diode, a MOS diode, a schottky diode, or the like.

The N region of the DL-SCR is connected with the outside through a forward Diode (also can be any other ESD device, such as GGNMOS, SCR, zener-Diode etc.), so as to realize the purpose of controlling the basic carrier.

In practical application, as shown in the circuit of FIG. 10, the upward SCR1 is replaced by DL-SCR, the input end of DL-SCR is connected with PAD, the output end is linked with VDD, and GND electrode is grounded; the downward SCR2 is replaced by DL-SCR, the input end of the DL-SCR is connected with Gnd, the output end of the DL-SCR is connected with PAD, and the VSS electrode and the GND electrode are both grounding electrodes.

Example 6

Referring to FIG. 11, a rail-based ESD protection circuit for PAD-to-rail and inter-PAD electrostatic protection design for a common rail is shown in accordance with an embodiment of the present utility model. Two or more diodes connected end to end are connected in series between the PAD and the VDD, the anode of each diode is connected to the PAD, the cathode of each diode is connected to the VDD, and static electricity of the PAD is discharged to the VDD; two or more diodes connected in series from PAD to VSS at the first position are used, the anode of each diode is connected to VSS, the cathode of each diode is connected to PAD, and static electricity of the PAD is discharged to VSS; the voltage between VDD and VSS is connected by using a transient voltage suppression diode, and static electricity between VDD and VSS is discharged. The diode or the transient voltage suppression diode adopts the electrostatic protection device based on the silicon-controlled diode in any one of the embodiment 1 to the embodiment 5. Wherein the diode is connected in series: the output end of the last electrostatic protection device based on the silicon-controlled diode is connected with the input end of the next electrostatic protection device based on the silicon-controlled diode.

Example 7

Referring to fig. 12, an ESD electrostatic protection circuit for a local floating rail according to an embodiment of the present utility model is shown, in which two or more diodes connected first are connected in series between a PAD and an ESDP, an anode of the diode is connected to the PAD, a cathode of the diode is connected to the ESDP, and positive static electricity of the PAD is discharged to the ESDP; two or more diodes connected in series from PAD to ESDN are arranged between the PAD and the ESDN, the anode of each diode is connected to the ESDN, the cathode of each diode is connected to the PAD, and negative static electricity of the PAD is discharged to the ESDN; the ESDP to ESDN are connected by using transient voltage suppression diodes, and positive electrostatic pulses between VDD and VSS are discharged, wherein the diodes or the transient voltage suppression diodes adopt the electrostatic protection device based on the silicon-controlled diode in any one of the embodiment 1 to the embodiment 5. Wherein the diode is connected in series: the output end of the last electrostatic protection device based on the silicon-controlled diode is connected with the input end of the next electrostatic protection device based on the silicon-controlled diode.

It should be understood that the exemplary embodiments described herein are illustrative and not limiting. Although one or more embodiments of the present utility model have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present utility model as defined by the following claims.

Claims

1. An electrostatic protection device based on a silicon-like diode, comprising:

a semiconductor substrate;

a deep buried layer isolation region embedded into the semiconductor substrate;

2. The silicon-like diode based electrostatic protection device of claim 1, wherein the ground is electrically connected to the semiconductor substrate through a third P-type doped region.

3. The silicon-like diode based electrostatic protection device of claim 1, wherein the input terminal is electrically connected to the semiconductor substrate through a third P-type doped region.

4. The silicon-like diode based electrostatic protection device of claim 1, wherein the output is electrically connected to the semiconductor substrate through a third P-type doped region.

5. The silicon-like diode electrostatic protection device of claim 2, further comprising a forward diode, the ground terminal electrically connected to a forward diode anode, the forward diode cathode electrically connected to the semiconductor substrate through a third N-doped region.

6. The silicon-like diode based electrostatic protection device according to any one of claims 1 to 5, wherein the semiconductor substrate is a P-type semiconductor substrate; the N-type semiconductor substrate is epitaxially provided with a P-type epitaxial layer or the N-type semiconductor substrate is epitaxially provided with a P-type epitaxial layer.

7. The rail-based ESD electrostatic protection circuit is characterized in that two or more diodes connected end to end are used between PAD and VDD to be connected in series, the anode of each diode is connected to the PAD, the cathode of each diode is connected to VDD, and the static electricity of the PAD is discharged to the VDD; two or more diodes connected in series from PAD to VSS at the first position are used, the anode of each diode is connected to VSS, the cathode of each diode is connected to PAD, and static electricity of the PAD is discharged to VSS; the use of a tvs diode connection between VDD and VSS to bleed off static electricity between VDD and VSS, wherein the diode and tvs diode employ a scr-like based electrostatic protection device as defined in any of claims 1 to 6.

8. The rail-based ESD protection circuit of claim 7 wherein the diode series is: the output end of the last electrostatic protection device based on the silicon-controlled diode is connected with the input end of the next electrostatic protection device based on the silicon-controlled diode.

9. An ESD electrostatic protection circuit of a local floating rail is characterized in that two or more diodes connected at first are connected in series between a PAD and an ESDP, the anode of each diode is connected to the PAD, the cathode of each diode is connected to the ESDP, and positive static electricity of the PAD is discharged to the ESDP; two or more diodes connected in series from PAD to ESDN are arranged between the PAD and the ESDN, the anode of each diode is connected to the ESDN, the cathode of each diode is connected to the PAD, and negative static electricity of the PAD is discharged to the ESDN; a transient voltage suppression diode connection is used between ESDP and ESDN to bleed off positive electrostatic pulses between VDD and VSS, wherein the diode or transient voltage suppression diode employs a silicon-like diode based electrostatic protection device as defined in any of claims 1 to 6.

10. The ESD protection circuit of claim 9 wherein the diodes are connected in series to: the output end of the last electrostatic protection device based on the silicon-controlled diode is connected with the input end of the next electrostatic protection device based on the silicon-controlled diode.