CN111312710B - ESD device with low residual voltage and low capacitance value and preparation method thereof - Google Patents

ESD device with low residual voltage and low capacitance value and preparation method thereof Download PDF

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CN111312710B
CN111312710B CN202010260317.4A CN202010260317A CN111312710B CN 111312710 B CN111312710 B CN 111312710B CN 202010260317 A CN202010260317 A CN 202010260317A CN 111312710 B CN111312710 B CN 111312710B
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pplus
nwell
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CN111312710A (en
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张跃
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Ouyue Semiconductor Xi'an Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

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Abstract

The invention discloses a low-capacitance low-residual voltage ESD protection device and a preparation method thereof, wherein a three-terminal device is formed by two low-capacitance diodes (D1 and D2), an SCR tube and a punch-through clamp TVS, the anode of a first capacitance-reducing tube D1 is connected with the cathode of the SCR tube, the cathode of the D1 tube is connected with the cathode of the D2 to form a first port IO1, the anode of the T1 and the cathode of the TVS tube form a second port IO2, and the anode of the TVS and the anode of the D2 form a third port GND. According to the invention, the low-capacity low-residual voltage protection is realized by integrating the SCR tube structure and the drop capacitance tube, the residual voltage of the device is effectively reduced by utilizing the semi-snapback characteristic of the SCR tube on the device structure, and the junction capacitance of the device is reduced by the high-resistance epitaxial layer.

Description

ESD device with low residual voltage and low capacitance value and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and relates to an ESD device with low residual voltage and low capacitance and a preparation method thereof.
Background
As feature sizes further decrease, ICs are more sensitive to ESD (electrostatic resistors) and withstand voltages are also greatly reduced. Most of the current ESD protection products generally adopt the r2r+zener mode to realize low-capacity ESD protection, however, the IC is damaged by static electricity too early due to the residual voltage problem, so that the ESD protection cannot meet the test requirement. Particularly for the TypeC interface, both low capacitance and very low residual voltage of the ESD protection product are required.
At present, HDMI2.0 and TypeC interface protection generally adopt a differential common mode for protection, and a product with snapback characteristics can more easily pass ESD test, and snapback voltage between IO-GND is too low (lower than working voltage) to easily form free-wheeling burn to burn out protection devices, so that a compromise between low residual voltage and maintenance Voltage (VH) is particularly important.
Therefore, the capacitance in the existing product meets the requirement, and the residual voltage cannot meet the protection requirement, or the residual voltage reduces the capacitance and cannot meet the requirement.
Disclosure of Invention
The technical problem solved by the invention is to provide the ESD device with low residual voltage and low capacity value and the preparation method thereof, which effectively solve the residual voltage problem in the low capacity structure through structural innovation and overcome the defect that the ESD protection of the high-speed interface is difficult to pass.
The invention is realized by the following technical scheme:
The low-capacitance low-residual voltage ESD device comprises an N substrate, a buried layer and a P-epitaxy, wherein a back metal layer is arranged on the back surface of the N substrate, and two low-capacitance diodes D1 and D2, an SCR tube T1 and a punch-through clamp TVS tube T2 are formed on the P-epitaxy;
the anode of the first low-capacitance diode D1 is connected with the cathode of the SCR tube T1, and the cathode of the first low-capacitance diode D1 is connected with the cathode of the second low-capacitance diode D2 to form a first port IO1; the anode of the SCR tube T1 is connected with the cathode of the punch-through clamp TVS tube T2 to form a second port IO2; the anode of the punch-through clamp TVS tube T2 and the anode of the second low-capacitance diode D2 are connected with the back metal layer through packaging wire bonding to form a third port GND.
The SCR tube T1 is a low residual voltage device, and differential mode current is discharged from the second port IO2 to the first port IO1 through the SCR tube T1 and the first low capacitance tube D1;
The through type clamping TVS tube T2 is a clamping type low-capacity component, and the common mode protection is realized by enabling the second port IO2 port to reach the third port GND through the through type clamping TVS tube T2.
An Nwell layer, a NPlus layer and a PPlus layer are respectively arranged on the P-epitaxy;
the Nwell layers comprise a first Nwell layer, a second Nwell layer and a third Nwell layer; NPlus layers include a first NPlus layer, a second NPlus layer, a third NPlus layer, and a fourth NPlus layer;
PPlus layers include a first PPlus layer, a second PPlus layer, and a third PPlus layer;
Wherein the first PPlus layers are anodes of the SCR T1, and the second NPlus layers are cathodes of the SCR T1;
The second PPlus layer is the anode of the first low-capacitance diode D1, and the third NPlus layer is the cathode of the first low-capacitance diode D1;
The first Nwell layer, the P-epitaxy and the N+ substrate together form a low residual voltage TVS tube T2;
The third PPlus layer is the anode of the second low-capacitance diode D2, and the third NPlus layer is the cathode of the second low-capacitance diode D2.
The second NPlus layer is connected with the second PPlus layer through a second metal electrode; the fourth NPlus layer is connected with the third PPlus layer through a fourth metal electrode; the fourth NPlus layer and the third Nwell layer are connected to the N+ substrate through packaging and wire bonding;
Forming a first P region by the first PPlus layers, forming a first N region by the first Nwell layer and the first NPlus layers, forming a second P region by P-epitaxy, and forming a second N region by the second NPlus layers to form a PNPN structure between IO-IO;
And forming an NPN structure between IO and GND by the first Nwell layer, the P-epitaxy and the N+ substrate.
Further, the ESD device is further expanded to form an IO-IO symmetrical device through the structure:
And connecting the IO1 port of the first ESD device with the IO2 port of the second ESD device, connecting the IO2 port of the first ESD device with the IO1 port of the second ESD device, sharing the substrate and GND, and forming a third port of the symmetrical device structure.
The invention also provides a preparation method of the low-capacitance low-residual voltage ESD device, which comprises the following operations:
1) Forming an N+ buried layer 101 and a P+ buried layer 102 which are spaced apart from each other on an N+ substrate 100 in an implantation doping manner;
2) After the N+ buried layer and the P+ buried layer are completed, forming a P-epitaxy 103 through epitaxial production;
3) Injecting P in the P-epitaxy through a photoetching mask to form Nwell layers, wherein the Nwell layers comprise a first Nwell layer, a second Nwell layer and a third Nwell layer;
4) P is implanted into the P-epitaxy 103 through a photoetching mask, so that NPlus layers and PPlus layers are respectively formed; NPlus layers include a first NPlus layer, a second NPlus layer, a third NPlus layer, and a fourth NPlus layer;
5) Evaporating and sputtering a metal layer after SiO 2 is subjected to photoetching, and forming a metal electrode through photoetching, wherein the metal electrode comprises a first metal electrode, a second metal electrode, a third metal electrode and a fourth metal electrode; wherein the first metal electrode is arranged on the first PPlus layer, the second metal electrode is connected with the second NPlus layer and the second NPlus layer, the third metal electrode is arranged on the third NPlus layer, and the fourth metal electrode is connected with the third PPlus layer and the fourth NPlus layer;
6) Deep trench isolation is respectively carried out at two ends of the N+ buried layer and the P+ buried layer, so that an isolation trench penetrating through the P-epitaxy is formed;
7) The back surface of the n+ substrate 100 is metallized to form the terminal GND.
The thickness of the buried layers of the N+ buried layer 101 and the P+ buried layer 102 is 0.7-3 um, and the distance l between the buried layers is larger than 6um;
the epitaxial thickness of the P-epitaxy 103 is 3.5-15 um.
The junction depth of the Nwell layer is 1-3 um, the junction depth of the NPlus layer is 0.5-1 um, and the junction depth of the PPlus layer is 0.5-1 um;
the implantation energy of 80-100 kev is used in the lithography mask implantation.
Compared with the prior art, the invention has the following beneficial technical effects:
The low-capacitance low-residual voltage ESD device provided by the invention adopts a high-resistance epitaxy (P epitaxy) structure, so that low-capacitance diode D1 and D2 are realized, and then are connected in series with the SCR T1 of the PNPN structure, and the low-capacitance low-residual voltage structure is realized through the capacitance reduction of the low-capacitance diode D1 and D2; meanwhile, the low-voltage breakdown characteristic between IO and GND is realized by utilizing the low-voltage breakdown characteristic (TVS of an NPN structure can realize the breakdown characteristic lower than an avalanche breakdown point), so that the low-residual voltage protection to the ground is realized;
Meanwhile, the characteristic of a PNPN structure device with a semi-snapback structure is realized through an SCR tube structure, a first P region is formed by PPlus, a first N region is formed by a first Nwell layer 201 and a first NPlus layer 205, a second P region is formed by P-epitaxy, and a second N region is formed by a second NPlus layer 206, so that residual voltage between IO-IO is reduced;
the punch-through breakdown between IO-GND is further realized through an NPN structure formed by the first Nwell layer 201, the epitaxial P region and the substrate, so that the breakdown characteristics of 2.5V and 3.3V are realized.
The invention can effectively solve the problem of high residual voltage of the original low-capacity product, provide Vcc to GND low-voltage clamp protection, solve the problem that the ESD is difficult to pass through when high-speed interface circuits such as HDMI2.0 and TypeC are protected currently, and effectively solve the problem of residual voltage in a low-capacity structure through structural innovation.
Compared with the R2R+Zener structure, the product can realize low-voltage protection of 1.8V, 2.5V, 3.3V and the like; compared with the SCR structure, the low-voltage clamping protection between IO and GND can be realized; in addition, the invention can realize multi-path ESD protection through the combined encapsulation of the products.
Drawings
FIG. 1 is a schematic diagram of the electrical principle of the present invention;
Fig. 2 is a schematic diagram of forming an n+ buried layer and a p+ buried layer;
FIG. 3 is a schematic illustration of P-epitaxial formation;
FIG. 4 is a schematic illustration of Nwell layer formation;
FIG. 5 is a schematic diagram of NPlus and PPlus layers;
FIG. 6 is a schematic diagram of the formation and structure of a completed device of the present invention;
FIG. 7 is a schematic diagram of a dual device extension architecture;
FIG. 8 is a schematic diagram of the I-V characteristics of the device of the present invention;
FIG. 9 shows a TLP test curve for a device of the invention;
Detailed Description
The invention is described in further detail below in connection with examples, which are intended to be illustrative rather than limiting.
According to the low-capacitance low-residual voltage ESD device provided by the invention, the integration of the SCR tube structure and the capacitor reducing tube is adopted, so that the low-capacitance low-residual voltage protection is realized, the residual voltage of the device is effectively reduced by utilizing the half snapback characteristic of the SCR tube in the device structure, and the junction capacitance of the device is reduced by the high-resistance epitaxial layer.
Referring to fig. 1-6, a low-capacitance low-residual voltage ESD device includes an N substrate, a buried layer, and a P-epi, wherein a back metal layer is disposed on the back surface of the N substrate, and two low-capacitance diodes D1, D2, an SCR tube T1, and a punch-through clamp TVS tube T2 are formed on the P-epi;
the anode of the first low-capacitance diode D1 is connected with the cathode of the SCR tube T1, and the cathode of the first low-capacitance diode D1 is connected with the cathode of the second low-capacitance diode D2 to form a first port IO1; the anode of the SCR tube T1 is connected with the cathode of the punch-through clamp TVS tube T2 to form a second port IO2; the anode of the punch-through clamp TVS tube T2 and the anode of the second low-capacitance diode D2 are connected with the back metal layer through packaging wire bonding to form a third port GND.
Further, the SCR tube T1 is a low residual voltage device with PNPN structure, and the differential mode current is discharged from the second port IO2 to reach the first port IO1 through the SCR tube T1 and the first low capacitance tube D1;
The through type clamping TVS tube T2 is a clamping type low-voltage container piece with an NPN structure, and the common mode protection is realized by enabling a second port IO2 port to reach a third port GND through the through type clamping TVS tube T2.
Further, an Nwell layer, a NPlus layer and a PPlus layer are respectively arranged on the P-epitaxy;
The Nwell layers include a first Nwell layer 201, a second Nwell layer 202, and a third Nwell layer 203; NPlus layers include a first NPlus layer 205, a second NPlus layer 206, a third NPlus layer 208, and a fourth NPlus layer 210;
PPlus layers include a first PPlus layer 204, a second PPlus layer 207, and a third PPlus layer 209;
Wherein the first PPlus layer 204 is the anode of the SCR tube T1, and the second NPlus layer 206 is the cathode of the SCR tube T1;
The second PPlus layer 207 is the anode of the first low-capacitance diode D1, and the third NPlus layer 208 is the cathode of the first low-capacitance diode D1;
The first Nwell layer 201, the P-epi 103 and the n+ substrate 100 together form a low residual voltage TVS tube T2;
The third PPlus layer 209 is the anode of the second low-capacitance diode D2 and the third NPlus layer 208 is the cathode of the second low-capacitance diode D2.
Specifically, the second NPlus layer 206 and the second PPlus layer 207 are connected through a second metal electrode 302; the fourth NPlus layer 210 is connected to the third PPlus layer 209 by a fourth metal electrode 304; the fourth NPlus layer 210 and the third Nwell layer 203 are connected to the n+ substrate 100 by package routing;
A first P region is formed by the first PPlus layer 204, a first N region is formed by the first Nwell layer 201 and the first NPlus layer 205, a second P region is formed by the P-epi 103, and a second N region is formed by the second NPlus layer 206, so as to form a PNPN structure between IO-IOs;
an NPN structure between IO-GND is formed by the first Nwell layer 201, the P-epi 103 and the n+ substrate 100.
Referring to fig. 7, the ESD device is also extended by the structure to form an IO-IO symmetric device:
And connecting the IO1 port of the first ESD device with the IO2 port of the second ESD device, connecting the IO2 port of the first ESD device with the IO1 port of the second ESD device, sharing the substrate and GND, and forming a third port of the symmetrical device structure.
Referring to fig. 2-6, the present invention provides a method for manufacturing the low capacitance low residual voltage ESD device, comprising the following operations:
1) Forming an N+ buried layer 101 and a P+ buried layer 102 which are spaced apart from each other on an N+ substrate 100 in an implantation doping manner;
2) After the N+ buried layer and the P+ buried layer are completed, forming a P-epitaxy 103 through epitaxial production;
3) Implanting P within the P-epi 103 through a photolithographic mask to form Nwell layers including a first Nwell layer 201, a second Nwell layer 202 and a third Nwell layer 203;
4) P is implanted into the P-epitaxy 103 through a photoetching mask, so that NPlus layers and PPlus layers are respectively formed; NPlus layers include a first NPlus layer 205, a second NPlus layer 206, a third NPlus layer 208, and a fourth NPlus layer 210;
PPlus layers include a first PPlus layer 204, a second PPlus layer 207, and a third PPlus layer 209;
Wherein the first PPlus layer 204 is located within the first Nwell layer 201, the third NPlus layer 208 is located within the second Nwell layer 202, and the fourth NPlus layer 210 is located within the third Nwell layer 203;
The second PPlus layer 207 is located between the first Nwell layer 201 and the second Nwell layer 202, and the third PPlus layer 209 is located between the second Nwell layer 202 and the third Nwell layer 203;
the second NPlus layer 206 is located between the first Nwell layer 201 and the second PPlus layer 207, and the first NPlus layer 205 is located between the first PPlus layer 204 and the second NPlus layer 206;
5) Evaporating and sputtering a metal layer after SiO 2 is subjected to photoetching, and forming a metal electrode through photoetching, wherein the metal electrode comprises a first metal electrode 301, a second metal electrode 302, a third metal electrode 303 and a fourth metal electrode 304; wherein, the first metal electrode 301 is disposed on the first PPlus layer 204, the second metal electrode 302 connects the second NPlus layer with the second NPlus layer 207, the third metal electrode 303 is disposed on the third NPlus layer 208, and the fourth metal electrode 304 connects the third PPlus layer 209 with the fourth NPlus layer 210;
6) Deep trench isolation is respectively carried out at two ends of the N+ buried layer 101 and the P+ buried layer 102 to form an isolation trench penetrating through the P-epitaxy 103;
7) The back surface of the n+ substrate 100 is metallized to form the terminal GND.
Wherein the first PPlus layer 204 is the anode of the SCR tube T1, and the second NPlus layer 206 is the cathode of the SCR tube T1;
The second PPlus layer 207 is the anode of the first low-capacitance diode D1, and the third NPlus layer 208 is the cathode of the first low-capacitance diode D1;
The first Nwell layer 201, the P-epi 103 and the n+ substrate 100 together form a low residual voltage TVS tube T2;
The third PPlus layer 209 is the anode of the second low-capacitance diode D2, and the third NPlus layer 208 is the cathode of the second low-capacitance diode D2;
The first metal electrode 301 is the outlet end of the second port IO2 of the device, the third metal electrode 303 is the outlet end of the first port IO1 of the device, and the fourth metal electrode 304 and the back metal of the substrate together form the outlet end of the third port GND of the device through package routing.
Specific examples are given below.
Referring to fig. 2-6, a method of manufacturing a low capacitance low residual voltage ESD device includes the operations of:
1) Forming an N+ buried layer 101 and a P+ buried layer 102 with a distance of l (l >6 um) on the N+ substrate material 100 in an implantation doping manner, wherein the thickness of the buried layer is 0.7um-3um;
2) After the N+ buried layer and the P+ buried layer are completed, forming a P-epitaxy 103 through epitaxy production, wherein the epitaxy thickness is 3.5um-15um, and different working voltage requirements can be realized according to epitaxy;
3) Phosphorus (P) is injected into the P-epitaxy 103 through a photoetching mask, and the junction depth is 1um-3um, so that Nwell layers 201, 202 and 203 are formed;
4) Phosphorus is injected through a photoetching mask to form NPlus layers (205, 206, 208, 210, energy of 80-100kev and junction depth of 0.5-1 um) and PPlus layers (204, 207, 209, energy of 80-100kev and junction depth of 0.5-1 um);
5) In the process of photoetching SIO 2, contact holes are formed on PPlus (204), NPlus (206), NPlus (208), NPlus (210), nwell (201), nwell (202) and PPlus (207), PPLus (209) in a photoetching manner, then a sputtered metal layer (the thickness of the metal layer is 2-4 um) is evaporated, and metal electrodes (301, 302, 303 and 304) are formed in a photoetching manner, wherein a second metal electrode 302 is used for connecting NPlus (207) and PPlus (206);
6) Forming Trench isolation (221, 222, 223, 224, trench width 0.8-2 um) by deep Trench for forming isolation wall;
7) The back surface is metallized to form a leading-out end GND; the metal electrode 301 forms the device outlet IO2, the metal electrode 303 forms the outlet IO1, and the metal electrode 304 forms the outlet GND together with the back metal by wire bonding and substrate connection.
Respectively performing I-V characteristic detection and TLP test on the ESD device;
Fig. 8 is a schematic diagram of the I-V characteristics of the device of the present invention, which shows that the device of the present invention has a large snapback characteristic and can provide very low ESD/surge residual voltage.
Fig. 9 is a TLP test curve of the inventive device, which visually demonstrates the transmission line pulse test effect, providing lower clamp protection due to the negative resistance effect.
According to the ESD device provided by the invention, the low-capacitance diode D1 and D2 are connected in series with the SCR tube T1 of the PNPN structure, and the low-capacitance low-residual voltage structure is realized through the capacitance reduction of the low-capacitance diode D1 and D2; meanwhile, the low-voltage breakdown characteristic between IO and GND is realized by utilizing the low-voltage breakdown characteristic (TVS of an NPN structure can realize the breakdown characteristic lower than an avalanche breakdown point), so that the low-residual voltage protection to the ground is realized;
Meanwhile, the characteristic of a PNPN structure device with a semi-snapback structure is realized through an SCR tube structure, a first P region is formed by PPlus, a first N region is formed by a first Nwell layer 201 and a first NPlus layer 205, a second P region is formed by P-epitaxy, and a second N region is formed by a second NPlus layer 206, so that residual voltage between IO-IO is reduced; the punch-through breakdown between IO-GND is further realized through an NPN structure formed by the first Nwell layer 201, the epitaxial P region and the substrate, so that the breakdown characteristics of 2.5V and 3.3V are realized.
The embodiments given above are preferred examples for realizing the present invention, and the present invention is not limited to the above-described embodiments. Any immaterial additions and substitutions made by those skilled in the art according to the technical features of the technical scheme of the invention are all within the protection scope of the invention.

Claims (7)

1. The low-capacitance low-residual voltage ESD device is characterized by comprising an N substrate, a buried layer and a P-epitaxy, wherein a back metal layer is arranged on the back surface of the N substrate, and two low-capacitance diodes (D1 and D2), an SCR tube (T1) and a through clamp TVS tube (T2) are formed on the P-epitaxy;
The anode of the first low-capacity diode (D1) is connected with the cathode of the SCR tube (T1), and the cathode of the first low-capacity diode (D1) is connected with the cathode of the second low-capacity diode (D2) to form a first port IO1; the anode of the SCR tube (T1) is connected with the cathode of the punch-through clamp TVS tube (T2) to form a second port IO2; the anode of the punch-through clamp TVS tube (T2) and the anode of the second low-capacitance diode (D2) are connected with the back metal layer through packaging wire bonding to form a third port GND;
the SCR tube (T1) is a low residual voltage device with a PNPN structure, and differential mode current is discharged from the second port IO2 to the first port IO1 through the SCR tube (T1) and the first low-capacitance tube D1;
the through type clamping TVS tube (T2) is a clamping type low-container part with an NPN structure, and the common mode protection is realized by enabling a second port IO2 port to reach a third port GND through the through type clamping TVS tube (T2);
An Nwell layer, a NPlus layer and a PPlus layer are respectively arranged on the P-epitaxy;
The Nwell layers comprise a first Nwell layer (201), a second Nwell layer (202) and a third Nwell layer (203); NPlus layers include a first NPlus layer (205), a second NPlus layer (206), a third NPlus layer (208), and a fourth NPlus layer (210);
PPlus layers include a first PPlus layer (204), a second PPlus layer (207), and a third PPlus layer (209);
wherein the first PPlus layer (204) is the anode of the SCR tube (T1), and the second NPlus layer (206) is the cathode of the SCR tube (T1);
the second PPlus layer (207) is the anode of the first low-capacitance diode (D1), and the third NPlus layer (208) is the cathode of the first low-capacitance diode (D1);
the first Nwell layer (201), the P-epitaxy (103) and the N+ substrate (100) together form a low residual voltage TVS tube (T2);
the third PPlus layer (209) is the anode of the second low-capacitance diode (D2), and the third NPlus layer (208) is the cathode of the second low-capacitance diode (D2).
2. The low capacitance low residual voltage ESD device of claim 1 wherein said second NPlus layer (206) is connected to said second PPlus layer (207) by a second metal electrode (302); the fourth NPlus layer (210) is connected to the third PPlus layer (209) by a fourth metal electrode (304); the fourth NPlus layer (210) and the third Nwell layer (203) are connected to the N+ substrate (100) through package routing;
Forming a first P region by the first PPlus layers (204), forming a first N region by the first Nwell layer (201) and the first NPlus layers (205), forming a second P region by the P-epitaxy (103), and forming a second N region by the second NPlus layers (206), thereby forming a PNPN structure between IO-IO;
And an NPN structure between IO-GND is formed by the first Nwell layer (201), the P-epitaxy (103) and the N+ substrate (100).
3. The low capacitance low residual voltage ESD device of claim 1 further characterized by forming the ESD device as IO-IO symmetric devices by structure expansion:
And connecting the IO1 port of the first ESD device with the IO2 port of the second ESD device, connecting the IO2 port of the first ESD device with the IO1 port of the second ESD device, sharing the substrate and GND, and forming a third port of the symmetrical device structure.
4. A method of making a low capacitance low residual voltage ESD device comprising the operations of:
1) Forming an N+ buried layer (101) and a P+ buried layer (102) which are spaced on an N+ substrate (100) respectively in an implantation doping manner;
2) After the N+ buried layer and the P+ buried layer are completed, forming a P-epitaxy (103) through epitaxial production;
3) Implanting P within the P-epi (103) through a photolithographic mask to form Nwell layers comprising a first Nwell layer (201), a second Nwell layer (202) and a third Nwell layer (203);
4) P is implanted into the P-epitaxy (103) through a photoetching mask to form NPlus layers and PPlus layers respectively; NPlus layers include a first NPlus layer (205), a second NPlus layer (206), a third NPlus layer (208), and a fourth NPlus layer (210);
PPlus layers include a first PPlus layer (204), a second PPlus layer (207), and a third PPlus layer (209);
Wherein the first PPlus layer (204) is located within the first Nwell layer (201), the third NPlus layer (208) is located within the second Nwell layer (202), and the fourth NPlus layer (210) is located within the third Nwell layer (203);
The second PPlus layer (207) is positioned between the first Nwell layer (201) and the second Nwell layer (202), and the third PPlus layer (209) is positioned between the second Nwell layer (202) and the third Nwell layer (203);
the second NPlus layer (206) is located between the first Nwell layer (201) and the second PPlus layer (207), and the first NPlus layer (205) is located between the first PPlus layer (204) and the second NPlus layer (206);
5) Evaporating and sputtering a metal layer after SiO 2 is subjected to photoetching, and forming a metal electrode through photoetching, wherein the metal electrode comprises a first metal electrode (301), a second metal electrode (302), a third metal electrode (303) and a fourth metal electrode (304); wherein the first metal electrode (301) is disposed on the first PPlus layer (204), the second metal electrode (302) connects the second NPlus layer with the second NPlus layer (207), the third metal electrode (303) is disposed on the third NPlus layer (208), and the fourth metal electrode (304) connects the third PPlus layer (209) with the fourth NPlus layer (210);
6) Deep trench isolation is respectively carried out at two ends of the N+ buried layer (101) and the P+ buried layer (102) to form an isolation trench penetrating through the P-epitaxy (103);
7) Carrying out metallization treatment on the back surface of the N+ substrate (100) to form a lead-out end GND;
wherein the first PPlus layer (204) is the anode of the SCR tube (T1), and the second NPlus layer (206) is the cathode of the SCR tube (T1);
the second PPlus layer (207) is the anode of the first low-capacitance diode (D1), and the third NPlus layer (208) is the cathode of the first low-capacitance diode (D1);
the first Nwell layer (201), the P-epitaxy (103) and the N+ substrate (100) together form a low residual voltage TVS tube (T2);
the third PPlus layer (209) is the anode of the second low-capacitance diode (D2), and the third NPlus layer (208) is the cathode of the second low-capacitance diode (D2);
The first metal electrode (301) is an outlet end of the second port IO2 of the device, the third metal electrode (303) is an outlet end of the first port IO1 of the device, and the fourth metal electrode (304) and the back metal of the substrate form an outlet end of the third port GND of the device together through package wire bonding.
5. The method for manufacturing the low-capacitance low-residual voltage ESD device of claim 4, wherein the thicknesses of the buried layers of the n+ buried layer (101) and the p+ buried layer (102) are 0.7-3 um, and the distance l between the two is greater than 6um;
the epitaxial thickness of the P-epitaxy (103) is 3.5-15 um.
6. The method for manufacturing the low-capacitance low-residual voltage ESD device of claim 4, wherein the junction depth of the Nwell layer is 1-3 um, the junction depth of the NPlus layer is 0.5-1 um, and the junction depth of the PPlus layer is 0.5-1 um;
The implantation energy of 80-100 kev is adopted in the process of photoetching mask implantation.
7. The method for manufacturing the low-capacitance low-residual voltage ESD device of claim 4 wherein said photolithography of SiO 2 is performed by photolithography of contact holes on the first PPlus layer (204), the second NPlus layer (206), the third NPlus layer (208), the fourth NPlus layer (210), the first Nwell layer (201), the second PPlus layer (207) and the third PPLus layer (209), respectively;
The thickness of the metal electrode layer is 2-4um.
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