CN211507635U

CN211507635U - ESD device with low residual voltage and low capacitance value

Info

Publication number: CN211507635U
Application number: CN202020477945.3U
Authority: CN
Inventors: 张跃
Original assignee: Ouyue Semiconductor Xi'an Co Ltd
Current assignee: Ouyue Semiconductor Xi'an Co Ltd
Priority date: 2020-04-03
Filing date: 2020-04-03
Publication date: 2020-09-15
Anticipated expiration: 2030-04-03

Abstract

The utility model discloses a low residual voltage ESD protection device of low appearance value, by two low appearance diodes (D1, D2), a SCR pipe and a punch-through type clamp TVS constitute three terminal device, first appearance pipe D1's that falls positive pole links to each other with the negative pole of SCR pipe, the negative pole of D1 pipe links to each other with D2's negative pole and forms first port IO1, T1's positive pole forms second port IO2 with the negative pole of TVS pipe, TVS's positive pole and D2's positive pole constitute third port GND. The utility model discloses a with SCR tube structure and the integration of falling the appearance pipe, realized low-volume low residual voltage protection, the device is structural to utilize the half sudden return characteristic of SCR pipe effectively to reduce the residual voltage of device to reduce the junction electric capacity of device through the high resistance epitaxial layer.

Description

ESD device with low residual voltage and low capacitance value

Technical Field

The utility model belongs to the technical field of semiconductor device, a ESD device of low residual voltage low capacity value is related to.

Background

As feature sizes are further reduced, ICs are more sensitive to ESD (electrostatic discharge) and withstand voltages are also greatly reduced. Most current ESD protection products generally adopt an R2R + Zener method to realize low-capacitance ESD protection, however, due to the problem of residual voltage, the IC is damaged by static electricity too early, so that the ESD protection cannot meet the test requirement. Especially for Type C interface, both low capacitance values and very low residual voltages of ESD protection products are required.

At present, the HDMI2.0 and Type C interface protection generally adopts a differential-common mode for protection, products with snapback characteristics can pass an ESD test more easily, and the snapback voltage between IO-GND is too low (lower than the working voltage) and is easy to form follow current burning to burn out a protection device, so that compromise between low residual voltage and maintenance Voltage (VH) is particularly important.

Therefore, the capacitor in the existing product meets the requirement, the residual voltage cannot meet the protection requirement, or the residual voltage reduces the capacitance and cannot meet the requirement.

SUMMERY OF THE UTILITY MODEL

The utility model provides a technical problem provide a low residual voltage holds ESD device of value low, effectively solves the low residual voltage problem of holding in the structure through the structural innovation, overcomes the defect that high-speed interface ESD protection is difficult to pass through.

The utility model discloses a realize through following technical scheme:

an ESD device with low capacitance value and low residual voltage comprises an N substrate, a buried layer and a P-epitaxy, wherein a back metal layer is arranged on the back of the N substrate, and two low-capacitance diodes D1 and D2, an SCR (silicon controlled rectifier) tube T1 and a punch-through clamping TVS (transient voltage suppressor) tube T2 are formed on the P-epitaxy;

the anode of the first low-capacitance diode D1 is connected with the cathode of the SCR tube T1, and the cathode of the first low-capacitance diode D1 is connected with the cathode of the second low-capacitance diode D2 to form a first port IO 1; the anode of the SCR tube T1 is connected with the cathode of the punch-through clamp TVS tube T2 to form a second port IO 2; the anode of the punch-through clamp TVS transistor T2 and the anode of the second low-capacitance diode D2 are connected to the back metal layer by a package wire to form a third port GND.

The SCR tube T1 is a low residual voltage device, differential mode current leakage reaches the first port IO1 from the second port IO2 through the SCR tube T1 and the first low-capacitance tube D1;

the punch-through clamp TVS transistor T2 is a clamp low-voltage device, common mode protection is achieved from a second port IO2 port to a third port GND through the punch-through clamp TVS transistor T2, and low-capacitance clamp protection is achieved.

The P-epitaxy is respectively provided with an Nwell layer, an NPlus layer and a PPlus layer;

the Nwell layers comprise a first Nwell layer, a second Nwell layer and a third Nwell layer; the NPlus layers comprise a first NPlus layer, a second NPlus layer, a third NPlus layer and a fourth NPlus layer;

the PPlus layer comprises a first PPlus layer, a second PPlus layer and a third PPlus layer;

wherein the first PPlus layer is the anode of the SCR tube T1, and the second NPlus layer is the cathode of the SCR tube T1;

the second PPlus layer is the anode of the first low-capacity diode D1, and the third NPlus layer is the cathode of the first low-capacity diode D1;

the first Nwell layer, the P-epitaxy and the N + substrate form a low residual voltage TVS (transient voltage suppressor) T2;

the third PPlus layer is the anode of the second low-capacitance diode D2 and the third NPlus layer is the cathode of the second low-capacitance diode D2.

The second NPlus layer is connected with the second PPlus layer through a second metal electrode; the fourth NPlus layer is connected with the third PPlus layer through a fourth metal electrode; the fourth NPlus layer and the third Nwell layer are connected to the N + substrate through packaging routing;

forming a first P area by the first PPlus layer, forming a first N area by the first Nwell layer and the first NPlus layer, forming a second P area by P-epitaxy, and forming a second N area by the second NPlus layer to form a PNPN structure between IO and IO;

and the first Nwell layer, the P-epitaxy and the N + substrate form an NPN structure between IO and GND.

Further, the ESD device is expanded through a structure to form an IO-IO symmetrical device:

and connecting an IO1 port of the first ESD device with an IO2 port of the second ESD device, connecting an IO2 port of the first ESD device with an IO1 port of the second ESD device, and sharing the substrate and GND to form a third port of the symmetrical device structure.

The first PPlus layer is positioned in the first Nwell layer, the third NPlus layer is positioned in the second Nwell layer, and the fourth NPlus layer is positioned in the third Nwell layer;

the second PPlus layer is positioned between the first Nwell layer and the second Nwell layer, and the third PPlus layer is positioned between the second Nwell layer and the third Nwell layer;

the second NPlus layer is positioned between the first Nwell layer and the second PPlus layer, and the first NPlus layer is positioned between the first PPlus layer and the second NPlus layer.

The thickness of the buried layers of the N + buried layer and the P + buried layer is 0.7-3 um, and the distance between the N + buried layer and the P + buried layer is l, l is more than 6 um;

the epitaxial thickness of the P-epitaxy is 3.5-15 um.

The junction depth of the Nwell layer is 1-3 um, the junction depth of the NPlus layer is 0.5-1um, and the junction depth of the PPlus layer is 0.5-1 um.

Compared with the prior art, the utility model discloses following profitable technological effect has:

the utility model provides a low-capacitance value low residual voltage's ESD device adopts high resistance epitaxy (P epitaxy) structure, has realized low-capacitance pipe diode D1, D2, and is established ties with the SCR pipe T1 of PNPN structure again, through the low-capacitance pipe diode D1, the low-capacitance low residual voltage structure of falling holds of D2; meanwhile, the low-voltage breakdown characteristic between IO-GND is realized by utilizing the low-voltage breakdown characteristic (the TVS of the NPN structure can realize the breakdown characteristic lower than the avalanche breakdown point), so that the low residual voltage protection to the ground is realized;

meanwhile, the characteristics of a PNPN structure device with a semi-snapback structure are realized through an SCR tube structure, a first P area is formed by PPlus204, a first N area is formed by the first Nwell layer 201 and the first NPlus layer 205, a second P area is formed by P-epitaxy, and a second N area is formed by the second NPlus layer 206, so that the residual voltage between IO and IO is reduced;

and the punch-through breakdown between IO-GND is realized through an NPN structure formed by the first Nwell layer 201, the epitaxial P region and the substrate, so that the breakdown characteristics of 2.5V and 3.3V are realized.

The utility model discloses can effectively solve original low-volume product residual voltage problem on the high side to provide Vcc to GND low pressure clamp protection, solved high speed interface circuit protection ESD such as current HDMI2.0, TypeC and be difficult to through that problem, effectively solve the residual voltage problem in the low-volume structure through structural innovation.

Compared with the R2R + Zener structure, the product can realize low-voltage protection of 1.8V, 2.5V, 3.3V and the like; compared with an SCR structure, the low-voltage clamping protection between IO-GND can be realized; and the utility model discloses a combination encapsulation of product can realize multichannel ESD protection.

Drawings

Fig. 1 is a schematic electrical diagram of the present invention;

FIG. 2 is a schematic diagram of N + buried layer and P + buried layer formation;

FIG. 3 is a schematic view of P-epi formation;

FIG. 4 is a schematic diagram of Nwell layer formation;

FIG. 5 is a schematic representation of the formation of NPlus and PPlus layers;

fig. 6 is a schematic diagram of the formation and structure of the complete device of the present invention;

FIG. 7 is a schematic diagram of a dual device expansion structure;

FIG. 8 is a schematic diagram of the I-V characteristics of the device of the present invention;

FIG. 9 is a TLP test curve for a device of the present invention;

Detailed Description

The present invention will be described in further detail with reference to the following examples, which are intended to be illustrative, but not limiting, of the present invention.

The utility model provides a pair of ESD device of low residual voltage of low appearance value through will adopting SCR tubular construction and fall the integration of holding the pipe, has realized the low residual voltage protection of low appearance, and the device is structural to utilize the half sudden return characteristic of SCR pipe effectively to reduce the residual voltage of device to reduce the junction electric capacity of device through the high resistance epitaxial layer.

Referring to fig. 1-6, an ESD device with low capacitance and low residual voltage includes an N substrate, a buried layer, and a P-epi, wherein a back metal layer is disposed on the back of the N substrate, and two low-capacitance diodes D1, D2, an SCR transistor T1, and a punch-through clamp TVS transistor T2 are formed on the P-epi;

Further, the SCR tube T1 is a low residual voltage device with a PNPN structure, and differential mode current leakage reaches the first port IO1 from the second port IO2 through the SCR tube T1 and the first low-capacitance tube D1;

the punch-through clamping TVS transistor T2 is a NPN structure clamping low-voltage device, common mode protection is achieved from a second port IO2 port to a third port GND through the punch-through clamping TVS transistor T2, and low-capacitance clamping protection is achieved.

Further, an Nwell layer, an NPlus layer and a PPlus layer are respectively arranged on the P-epitaxy;

the Nwell layers comprise a first Nwell layer 201, a second Nwell layer 202 and a third Nwell layer 203; the NPlus layers include a first NPlus layer 205, a second NPlus layer 206, a third NPlus layer 208, and a fourth NPlus layer 210;

the PPlus layers include a first PPlus layer 204, a second PPlus layer 207, and a third PPlus layer 209;

wherein the first PPlus layer 204 is an anode of the SCR tube T1, and the second NPlus layer 206 is a cathode of the SCR tube T1;

the second PPlus layer 207 is the anode of the first low-capacitance diode D1, and the third NPlus layer 208 is the cathode of the first low-capacitance diode D1;

the first Nwell layer 201, the P-epitaxy 103 and the N + substrate 100 together form a low residual voltage TVS (transient voltage suppressor) T2;

the third PPlus layer 209 is the anode of the second low-capacitance diode D2 and the third NPlus layer 208 is the cathode of the second low-capacitance diode D2.

Specifically, the second NPlus layer 206 and the second PPlus layer 207 are connected through a second metal electrode 302; the fourth NPlus layer 210 is connected to the third PPlus layer 209 via a fourth metal electrode 304; the fourth NPlus layer 210 and the third Nwell layer 203 are connected to the N + substrate 100 through packaging and routing;

a first P area is formed by the first PPlus layer 204, a first N area is formed by the first Nwell layer 201 and the first NPlus layer 205, a second P area is formed by the P-epitaxy layer 103, and a second N area is formed by the second NPlus layer 206 to form a PNPN structure between IO and IO;

and an NPN structure between IO-GND is formed by the first Nwell layer 201, the P-epitaxy 103 and the N + substrate 100.

Referring to fig. 7, the ESD device is also extended by a structure to form an IO-IO symmetric device:

Referring to fig. 2 to fig. 6, the present invention provides a method for manufacturing the ESD device with low capacitance and low residual voltage, including the following operations:

1) forming an N + buried layer 101 and a P + buried layer 102 which are spaced on an N + substrate 100 respectively in an implantation doping mode;

2) after the N + buried layer and the P + buried layer are finished, forming a P-epitaxy 103 through epitaxy production;

3) implanting P through a photolithographic mask in the P-epi 103 to form Nwell layers, including a first Nwell layer 201, a second Nwell layer 202, and a third Nwell layer 203;

4) injecting P in the P-epitaxy 103 through a photoetching mask to form an NPlus layer and a PPlus layer respectively; the NPlus layers include a first NPlus layer 205, a second NPlus layer 206, a third NPlus layer 208, and a fourth NPlus layer 210;

wherein the first PPlus layer 204 is located within the first Nwell layer 201, the third NPlus layer 208 is located within the second Nwell layer 202, and the fourth NPlus layer 210 is located within the third Nwell layer 203;

a second PPlus layer 207 is positioned between the first Nwell layer 201 and the second Nwell layer 202, and a third PPlus layer 209 is positioned between the second Nwell layer 202 and the third Nwell layer 203;

the second NPlus layer 206 is located between the first Nwell layer 201 and the second PPlus layer 207, and the first NPlus layer 205 is located between the first PPlus layer 204 and the second NPlus layer 206;

5) photoetching SiO₂Post-evaporating and sputtering the metal layer and forming the metal by photolithographyElectrodes including a first metal electrode 301, a second metal electrode 302, a third metal electrode 303, and a fourth metal electrode 304; wherein, the first metal electrode 301 is arranged on the first PPlus layer 204, the second metal electrode 302 is connected with the second NPlus layer and the second NPlus layer 207, the third metal electrode 303 is arranged on the third NPlus layer 208, and the fourth metal electrode 304 is connected with the third PPlus layer 209 and the fourth NPlus layer 210;

6) deep trench isolation is respectively carried out at two ends of the N + buried layer 101 and the P + buried layer 102 to form an isolation trench penetrating through the P-epitaxy 103;

7) and carrying out metallization treatment on the back surface of the N + substrate 100 to form a terminal GND.

the third PPlus layer 209 is the anode of the second low-capacitance diode D2, and the third NPlus layer 208 is the cathode of the second low-capacitance diode D2;

the first metal electrode 301 is a leading-out terminal of the second port IO2 of the device, the third metal electrode 303 is a leading-out terminal of the first port IO1 of the device, and the fourth metal electrode 304 and the substrate back metal jointly form a leading-out terminal of the third port GND of the device through packaging and routing.

Specific examples are given below.

Referring to fig. 2 to 6, a method for manufacturing a low-capacitance low-residual-voltage ESD device includes the following operations:

1) forming an N + buried layer 101 and a P + buried layer 102 which are separated by l (l >6um) on an N + substrate material 100 respectively in an implantation doping mode, wherein the buried layers are 0.7-3 um thick;

2) after the N + buried layer and the P + buried layer are finished, a P-epitaxy 103 is formed through epitaxy production, the epitaxy thickness is 3.5-15 um, and different working voltage requirements can be realized according to the epitaxy;

3) injecting phosphorus (P) into the P-epitaxy 103 through a photoetching mask, wherein the junction depth is 1um-3um, and Nwell layers 201, 202 and 203 are formed;

4) implanting phosphorus through a photolithographic mask to form an NPlus layer (205, 206, 208, 210, energy 80-100kev, junction depth 0.5-1um) and a PPlus layer (204, 207, 209, energy 80-100kev, junction depth 0.5-1 um);

5) photolithographic SIO₂At the same time, contact holes are etched on PPlus (204), NPlus (206), NPlus (208), NPlus (210), Nwell (201), Nwell (202), PPlus (207) and PPlus (209), then a metal layer (the thickness of the metal layer is 2-4um) is evaporated and sputtered, and metal electrodes (301, 302, 303, 304) are formed by photoetching, wherein the second metal electrode 302 is used for connecting NPlus (207) with PPlus (206);

6) forming Trench isolations (221, 222, 223, 224, the Trench width is 0.8-2um) through the deep Trench Trench for forming isolation walls;

7) carrying out metallization treatment on the back surface to form a leading-out end GND; the metal electrode 301 forms a device lead terminal IO2, the metal electrode 303 forms a lead terminal IO1, and the metal electrode 304 is connected to the substrate by wire bonding and forms a lead terminal GND together with the back metal.

I-V characteristic detection and TLP test are respectively carried out on the ESD device;

fig. 8 is a schematic diagram of the I-V characteristic of the device of the present invention, showing that the device of the present invention has a large snapback characteristic and can provide a very low ESD/surge residual voltage.

Fig. 9 is a TLP test curve of the device of the utility model, the curve visually represents the transmission line pulse test effect, and due to the negative resistance effect, lower clamp protection can be provided.

The utility model provides an ESD device, low-capacitance tube diode D1, D2 and PNPN SCR pipe T1 of structure establish ties, fall through low-capacitance tube diode D1, D2 and hold, realized low-capacitance low residual voltage structure; meanwhile, the low-voltage breakdown characteristic between IO-GND is realized by utilizing the low-voltage breakdown characteristic (the TVS of the NPN structure can realize the breakdown characteristic lower than the avalanche breakdown point), so that the low residual voltage protection to the ground is realized;

meanwhile, the characteristics of a PNPN structure device with a semi-snapback structure are realized through an SCR tube structure, a first P area is formed by PPlus204, a first N area is formed by the first Nwell layer 201 and the first NPlus layer 205, a second P area is formed by P-epitaxy, and a second N area is formed by the second NPlus layer 206, so that the residual voltage between IO and IO is reduced; and the punch-through breakdown between IO-GND is realized through an NPN structure formed by the first Nwell layer 201, the epitaxial P region and the substrate, so that the breakdown characteristics of 2.5V and 3.3V are realized.

The embodiments given above are preferred examples for implementing the present invention, and the present invention is not limited to the above-described embodiments. Any non-essential addition and replacement made by the technical features of the technical solution of the present invention by those skilled in the art all belong to the protection scope of the present invention.

Claims

1. An ESD device with low capacitance value and low residual voltage is characterized by comprising an N substrate, a buried layer and a P-epitaxy, wherein a back metal layer is arranged on the back of the N substrate, and two low-capacitance diodes (D1 and D2), an SCR (selective catalytic reduction) tube (T1) and a punch-through clamping TVS tube (T2) are formed on the P-epitaxy;

the anode of the first low-capacitance diode (D1) is connected with the cathode of the SCR tube (T1), and the cathode of the first low-capacitance diode (D1) is connected with the cathode of the second low-capacitance diode (D2) to form a first port IO 1; the anode of the SCR tube (T1) is connected with the cathode of the punch-through clamp TVS tube (T2) to form a second port IO 2; the anode of the punch-through clamping TVS tube (T2) and the anode of the second low-capacitance diode (D2) are connected with the back metal layer through packaging and routing to form a third port GND.

2. The low-capacitance low-residual-voltage ESD device according to claim 1, wherein the SCR (T1) is a PNPN low-residual-voltage device, and differential mode current is discharged from the second port IO2 to the first port IO1 through the SCR (T1) and the first low-capacitance tube D1;

the punch-through type clamping TVS tube (T2) is a clamping type low-voltage device with an NPN structure, common mode protection is achieved from a second port IO2 port to a third port GND through the punch-through type clamping TVS tube (T2), and low-capacitance clamping protection is achieved.

3. The low-capacitance low-residual-voltage ESD device according to claim 1, wherein the P-epi is respectively provided with an Nwell layer, an NPlus layer and a PPlus layer;

the Nwell layers comprise a first Nwell layer (201), a second Nwell layer (202) and a third Nwell layer (203); the NPlus layers comprise a first NPlus layer (205), a second NPlus layer (206), a third NPlus layer (208), and a fourth NPlus layer (210);

the PPlus layers comprise a first PPlus layer (204), a second PPlus layer (207) and a third PPlus layer (209);

wherein the first PPlus layer (204) is an anode of the SCR tube (T1) and the second NPlus layer (206) is a cathode of the SCR tube (T1);

the second PPlus layer (207) is the anode of the first low-capacitance diode (D1), and the third NPlus layer (208) is the cathode of the first low-capacitance diode (D1);

the first Nwell layer (201), the P-epitaxy layer (103) and the N + substrate (100) jointly form a low residual voltage TVS tube (T2);

the third PPlus layer (209) is the anode of the second low-capacitance diode (D2) and the third NPlus layer (208) is the cathode of the second low-capacitance diode (D2).

4. A low-capacitance low-residual-voltage ESD device according to claim 3, wherein the second NPlus layer (206) and the second PPlus layer (207) are connected via a second metal electrode (302); the fourth NPlus layer (210) is connected with the third PPlus layer (209) through a fourth metal electrode (304); the fourth NPlus layer (210) and the third Nwell layer (203) are connected to the N + substrate (100) through packaging and routing;

a first P area is formed by the first PPlus layer (204), a first N area is formed by the first Nwell layer (201) and the first NPlus layer (205), a second P area is formed by the P-epitaxy layer (103), and a second N area is formed by the second NPlus layer (206) to form a PNPN structure between IO and IO;

and an NPN structure between IO-GND is formed by the first Nwell layer (201), the P-epitaxy (103) and the N + substrate (100).

5. The low-capacitance-value low-residual-voltage ESD device according to claim 1, wherein the ESD device is further expanded by a structure to form an IO-IO symmetric device:

6. The low-capacitance low-residual-voltage ESD device according to claim 3, wherein the first PPlus layer (204) is located in the first Nwell layer (201), the third NPlus layer (208) is located in the second Nwell layer (202), and the fourth NPlus layer (210) is located in the third Nwell layer (203);

a second PPlus layer (207) is located between the first Nwell layer (201) and the second Nwell layer (202), and a third PPlus layer (209) is located between the second Nwell layer (202) and the third Nwell layer (203);

the second NPlus layer (206) is located between the first Nwell layer (201) and the second PPlus layer (207), and the first NPlus layer (205) is located between the first PPlus layer (204) and the second NPlus layer (206).

7. The low-capacitance low-residual-voltage ESD device according to claim 1, wherein the buried layer comprises an N + buried layer (101) and a P + buried layer (102), the buried layer thickness of the N + buried layer (101) and the P + buried layer (102) is 0.7-3 um, and the distance between the N + buried layer and the P + buried layer is l, l >6 um;

the epitaxial thickness of the P-epitaxy (103) is 3.5-15 um.

8. The low-capacitance low-residual-voltage ESD device according to claim 3, wherein the Nwell layer has a junction depth of 1-3 um, the NPlus layer has a junction depth of 0.5-1um, and the PPlus layer has a junction depth of 0.5-1 um.