CN211858652U - Silicon controlled electrostatic discharge device and integrated circuit - Google Patents

Abstract

The controllable silicon type electrostatic discharge device takes a traditional LDMOS-SCR device as a basis, an N well region at a drain end is split into a first N well region and a second N well region which are matched with a second P doping region and a second N doping region in the N well region, the parasitic resistance of the N well region is improved, the voltage drop of the N well region under the ESD discharge current is improved more quickly, the starting speed of a parasitic PNP tube is increased, the starting speed of the controllable silicon type electrostatic discharge device is improved, and the electrostatic discharge protection level is improved. The integrated circuit comprises the silicon controlled electrostatic discharge device. The utility model discloses a silicon controlled electrostatic discharge device's institutional advancement is simple and easy, and silicon controlled electrostatic discharge device's opening speed that has promoted under the condition that does not have the increase of process cost has promoted electrostatic discharge protection level.

Description

Silicon controlled electrostatic discharge device and integrated circuit

Technical Field

The utility model relates to an integrated circuit's electrostatic discharge protection technical field, in particular to thyristor type electrostatic discharge device and integrated circuit.

Background

Electrostatic Discharge (ESD) is a common phenomenon in daily life, and although not easily perceived by human body, it can pose a serious threat to integrated circuit products.

The modes of electrostatic discharge phenomena are generally divided into several categories: human body discharge mode (HBM), machine discharge mode (MM), component Charge Discharge Mode (CDM). In contrast to HBM and MM discharges, CDM is an ESD mode in which some pin of a chip, which is itself electrostatically charged, contacts ground, causing electrostatic charge inside the chip to be transferred to ground. Because the charges are stored in the relatively small parasitic capacitance of the chip and the total resistance of the discharge loop in the CDM mode is small, the rising speed of the waveform is very fast and is about 0.2-0.4 ns, the pulse duration is about 5ns, and the peak current can reach 15-20 times of the HBM discharge peak value under the same ESD stress. This requires that the ESD protection device be turned on fast enough and have high robustness.

According to the data statistics of National-Semiconductor (National-Semiconductor) companies, the current integrated circuit has 38 percent of all products with ESD/EOS (Electrical-Over-Stress) caused failure. For a high voltage CMOS (Complementary Metal Oxide Semiconductor) or a high voltage BCD (bipolar-CMOS-DMOS), the technology is widely used for manufacturing integrated circuit products in the fields of power management, high voltage driving, automotive electronics, and the like. However, such integrated circuit products often work in environments with large current, large voltage and strong electromagnetic interference, the ESD protection device has problems of low robustness, false triggering and the like, and a highly reliable and robust ESD device solution protection scheme is needed.

For high voltage power integrated circuits, LDMOS (laterally double diffused Metal-Oxide-Semiconductor) transistors are widely used as protection devices for high voltage input/output pins because they can withstand high breakdown voltages. An LDMOS device is an ESD protection device. Fig. 1 shows a schematic structural diagram of a conventional LDMOS device according to the prior art. The conventional LDMOS device 100 includes a P-type substrate 110, a P-well region 120 and an N-drift region 130 formed on the P-type substrate 110 without overlapping each other. A P-doped region 121 and an N-doped region 122 are disposed in the P-well region 120, and the P-doped region 121 and the N-doped region 122 are separated by an isolation layer 123; an N well region 131 and a gate oxide layer 140 are arranged in the N drift region 130, and an N doped region 132 is arranged in the N well region 131; both ends of the gate oxide layer 140 are connected to the N-doped region 122 and the N-doped region 132, respectively, and the gate 150 is disposed on a partial region of the gate oxide layer 140. The N-doped region 132 has a drain electrode as an anode, and the P-doped region, the N-doped region and the gate have active electrodes as cathodes, wherein the electrode layer is not shown and the anode is an electrostatic input.

The working principle of the conventional LDMOS device shown in fig. 1 when an ESD surge occurs at the anode of the electrostatic input terminal is as follows: when the electric field intensity born by the pn junction of the drain region of the LDMOS transistor is larger than the avalanche breakdown critical electric field, the current carrier of the drain region obtains enough energy under the acceleration of the electric field to generate an avalanche multiplication effect, a large number of electron-hole pairs are generated, the current of the drain region is increased sharply, meanwhile, the parasitic bipolar transistor in the LDMOS transistor is started to generate the current from a collector to an emitter, the voltage for maintaining the avalanche breakdown is reduced, the negative resistance hysteresis effect that the voltage is reduced and the current is increased is formed, and the device is burnt out by thermal breakdown. The trigger voltage of the LDMOS transistor is not only dependent on the avalanche breakdown critical electric field of the pn junction of the drain region, but also the transverse withstand voltage of the drift region of the LDMOS transistor plays a great role, the trigger voltage of the LDMOS ESD device is effectively improved, and the trigger voltage of the LDMOS ESD device can be adjusted by changing the length of the drift region. However, the parasitic bipolar transistor inside the LDMOS transistor is affected by the base region widening effect, large hysteresis occurs after avalanche breakdown occurs, and the current rapidly rises, and when the current enters a hysteresis point, the LDMOS transistor rapidly enters a thermal breakdown state, and cannot continue to perform electrostatic discharge. Therefore, the conventional LDMOS ESD device has small electrostatic discharge current per unit area and is difficult to obtain a high ESD protection level.

Fig. 2 shows a schematic structural diagram of a conventional LDMOS-SCR device according to the prior art. The conventional LDMOS-SCR device 200 is formed with a P-well region 220 and an N-drift region 230 that do not overlap each other on a P-type substrate 210. A P-doped region 221 and an N-doped region 222 are disposed in the P-well region 220, and the P-doped region 221 and the N-doped region 222 are separated by an isolation layer 223; an N well region 231 and a gate oxide layer 240 are arranged in the N drift region 230, an N doped region 232 and a P doped region 233 are arranged in the N well region 231, and the N doped region 232 and the P doped region 233 are isolated by an isolation layer 234; both ends of the gate oxide layer 240 are connected to the N-doped region 222 and the P-doped region 233, respectively, and the gate 250 is disposed on a partial region of the gate oxide layer 240. The N-doped region 232 and the P-doped region 233 are provided with drain electrodes interconnected as anodes, and the P-doped region, the N-doped region and the gates are provided with active electrodes interconnected as cathodes, wherein electrode layers are not shown, and the anodes are electrostatic input terminals.

The equivalent circuit diagram of the LDMOS-SCR device shown in fig. 2 is shown in fig. 3, and mainly comprises two parasitic bipolar transistors, including a PNP transistor T1 and an NPN transistor T2, where R1 is the equivalent parasitic resistance of the N-well region, and R2 is the equivalent parasitic resistance of the P-well region. When a forward ESD pulse comes, the positive voltage makes a PN junction formed by an N drift region and a P well region in the SCR generate reverse bias, and the PN junction gradually enters avalanche breakdown along with the gradual increase of the ESD voltage. Holes generated by PN junction avalanche flow into the P well region from the N well region, and are collected by the P doping region in the P well region to generate current; similarly, the generated electrons flow from the P-well region into the N-well region and are finally collected by the N-doped region of the N-well region to generate a current. Since both the nwell and pwell regions have parasitic resistances R1 and R2, voltage drops are formed across the nwell and pwell regions. When the voltage drop on the N well region or the P well region reaches 0.7V, one of the parasitic transistors NPN or PNP is started. When one triode is started, the voltage drop caused by the current generated on the collector of the triode can immediately start the other parasitic triode. Finally, the two triodes form an open-circuit positive feedback mechanism, the SCR is completely started, and a low-resistance passage is formed. When the parasitic resistances R1 and R2 of the nwell and pwell regions are small, a larger ESD current is needed to trigger the SCR path to turn on, resulting in slow SCR turn-on, which may cause the system to be damaged by the electrostatic discharge in a short time.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention is directed to a thyristor-type electrostatic discharge device and an integrated circuit, so as to improve the response speed of electrostatic discharge protection.

According to an aspect of the present invention, there is provided a thyristor type electrostatic discharge device, comprising:

a substrate;

the P well region is positioned in the substrate;

the drift region is positioned in the substrate and does not overlap with the P well region;

a first P-doped region and a first N-doped region located in the P-well region, the first P-doped region being farther from the drift region than the first N-doped region;

the first N well region and the second N well region are positioned in the drift region, and the distance between the first N well region and the second N well region is greater than zero;

a second P-doped region and a second N-doped region respectively located in the first N-well region and the second N-well region, the second P-doped region being closer to the P-well region than the second N-doped region;

the gate oxide layer is arranged between the P well region and the N well region, one end of the gate oxide layer is contacted with the first N doping region, and the other end of the gate oxide layer is contacted with the second P doping region;

and the polycrystalline silicon layer is arranged on the gate oxide layer.

Optionally, a pitch of the first nwell region and the second nwell region is adjustable.

Optionally, the first P-doped region, the first N-doped region, and the gate layer are all electrically connected to a cathode of the scr-type electrostatic discharge device, and the second P-doped region and the second N-doped region are all electrically connected to an anode of the scr-type electrostatic discharge device.

Optionally, the gate oxide layer includes a first segment and a second segment in series, the thickness of the first segment is smaller than that of the second segment, the first segment extends to the first N-doped region, the second segment extends to the second P-doped region, and the second segment is located in the drift region.

Optionally, the polysilicon layer is a stepped structure matched with the gate oxide layer, and completely covers the first segment and partially covers the second segment.

Optionally, the distance between the P-well region and the drift region is greater than zero.

According to another aspect of the present invention, there is provided an integrated circuit, including:

according to the utility model discloses a silicon controlled rectifier nature electrostatic discharge device that an aspect provided.

The utility model provides a silicon controlled type electrostatic discharge device uses traditional LDMOS-SCR device as the basis, with the well region split of N of drain terminal for with the well region of this N in second P doping district and the first well region of second N doping district assorted and the well region of second N, the parasitic resistance of the well region of N has been improved, it is faster to make its pressure drop promotion under ESD discharge current, make the opening rate of parasitic PNP pipe faster, improve silicon controlled type electrostatic discharge device's opening speed, the electrostatic discharge protection level has been improved.

The quantity of the N well regions with the transverse structures is changed without additionally increasing the using amount of a patterned mask in the manufacturing process, so that the increase of the process cost is avoided, and the feasibility is high.

The size of the parasitic resistance of the N well region is influenced by the distance between the first N well region and the second N well region, and the adjustment of the distance can realize the adjustment of the trigger voltage.

The thickness that the gate oxide is located the second section part in the drift region is thick, can promote the current driving ability, promotes the device and opens electric current lifting speed, improves device electrostatic protection opening speed.

The utility model discloses an integrated circuit includes the utility model provides a thyristor type electrostatic discharge device, its electrostatic discharge protects the response speed fast, and electrostatic discharge protects the reliability high.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic structural diagram of a conventional LDMOS device according to the prior art;

FIG. 2 illustrates a schematic structural diagram of a conventional LDMOS-SCR device according to the prior art;

FIG. 3 illustrates an equivalent circuit diagram of a conventional LDMOS-SCR device according to the prior art;

fig. 4 shows a schematic structural view of a thyristor-type electrostatic discharge device according to the invention;

fig. 5 shows a graph comparing the performance of a thyristor-type electrostatic discharge device according to the present invention and a prior art LDMOS-SCR device.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.

The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.

Fig. 4 shows a schematic structural view of a thyristor-type electrostatic discharge device according to the present invention. As shown, the scr-type electrostatic discharge device 300 of the present invention includes a P-well region 320 and an N-drift region 330 on a P-substrate 310 without overlapping each other. The depth of drift region 330 is greater than the depth of P-well region 320.

The distance between the N drift region 330 and the P well region 320 is greater than zero, which can inhibit the P well region from extracting holes in the drift region, thereby improving the hole concentration and reducing the conduction voltage drop.

The P-well 320 has a P-doped region 321, an N-doped region 322, and an isolation layer 323, wherein the isolation layer 323 separates the P-doped region 321 from the N-doped region 322.

An N well region 331 and an N well region 332 which are separated are arranged in the N drift region 330, a P doped region 333 is arranged in the N well region 331, an N doped region 334 is arranged in the N well region 332, and the P doped region 333 and the N doped region 334 are separated by an isolation layer 335, wherein the P doped region 333 and the N doped region 334 form a drain terminal.

The gate oxide layer 340 is disposed between the P-doped region 333 and the N-doped region 322. The polysilicon layer 350 is disposed on a partial region of the gate oxide layer 340. In this embodiment, the gate oxide layer 340 includes a first section and a second section that are continuous and have different thicknesses, wherein the first section has a smaller thickness than the second section, the second section is located in the N drift region 330, one end of the second section is connected to the first section, and the other end of the second section extends to the edge region of the P-doped region 333; the first segment extends to the edge region of the N-doped region 322. The polysilicon layer 350 is designed to have a step structure matching with the gate oxide layer 240, and completely covers the first segment of the gate oxide layer 340 and covers a part of the second segment. The high-thickness gate oxide layer can also improve the heavy current load capacity of the device, improve the pressure resistance and improve the robustness of the device. The polysilicon layer 350 and the gate oxide layer 340 are designed in a matching way, so that the corresponding electrical characteristics can be optimized, and the reliability is improved. The gate oxide layer may also serve as a mask for forming the doped regions.

Electrode layers not shown are further arranged on the P-doped region 321, the N-doped region 322, the P-doped region 333, the N-doped region 334 and the polysilicon layer 350, wherein the electrode layers of the P-doped region 321, the N-doped region 322P and the polysilicon layer 350 are interconnected to form a cathode, the electrode layers of the P-doped region 333 and the N-doped region 334 are interconnected to form an anode, the anode is an electrostatic voltage input end, and the cathode can be grounded.

The silicon controlled electrostatic discharge device 300 of the embodiment of the present invention is the same as the equivalent circuit diagram of the conventional LDMOS-SCR device 200 shown in fig. 2, and the main differences are as follows: the utility model discloses a P of thyristor type electrostatic discharge device 300 drain end dopes district 333 and the N trap region that N dopes the district 334 and corresponds and separates for N trap region 331 and N trap region 332, in order to improve parasitic resistance R1, accelerate parasitic resistance R1's pressure drop along with the slew velocity of electrostatic discharge current, accelerate the opening rate of parasitic transistor (parasitic resistance R1 pressure drop reaches 0.7V more fast, in order to open parasitic PNP transistor T1 fast, thereby open whole SCR route), thereby it opens required trigger current to have reduced the SCR route, the opening rate of SCR has been promoted.

The distance between the N-well region 332 and the N-well region 331 can be adjusted as required, actual parameters are not uniquely fixed, and the larger the distance is, the larger the parasitic resistance of the N-well region is, and the faster the turn-on speed is.

And, the improvement of structure lies in the increase of well region quantity of horizontal structure, does not have the increase of fore-and-aft layer structure, need not to increase the number of piles of graphical mask promptly in the manufacturing process of device, can obtain under the condition that does not increase the processing cost the utility model discloses a controllable silicon type electrostatic discharge device that opening speed is fast. Just the utility model discloses a silicon controlled electrostatic discharge device's technology suitability is high, can adopt high-pressure silicon Local Oxidation to keep apart (Local Oxidation of silicon) technique to realize the isolation layer preparation, or adopt other high-pressure technologies also to be suitable for.

Fig. 5 shows a graph comparing the performance of a thyristor-type electrostatic discharge device according to the present invention and a prior art LDMOS-SCR device. As shown in the figure, the TLP (Transmission Line Pulse) curves of the thyristor (also referred to as SCR) and the conventional SCR (LDMOS-SCR shown in fig. 2) are substantially the same, i.e. have the basic esd protection function and have high robustness. Further, the utility model discloses a trigger voltage of SCR device is low, and trigger current is little, just can form under less ESD electric current and trigger, and then hysteresis discharge ESD electric current, and its opening time shortens greatly. The trigger voltage is low, and the protection reliability of the protected device is high. The secondary breakdown current is higher than that of the traditional SCR device, and the SCR device has stronger robustness and higher ESD protection level.

The utility model discloses a silicon controlled electrostatic discharge device uses traditional LDMOS-SCR device as the basis, separate the N well region in drain region for with the P doping area and two N well regions of N doping district assorted of drain region N well region, with the parasitic well region resistance of increase parasitic PNP transistor, reduce the opening current in silicon controlled electrostatic discharge path of silicon controlled electrostatic discharge device, make just can trigger the SCR route under less ESD electric current, shorten the device opening time, make it can open fast under the CDM mode, play and protect effectively the integrated circuit who has used this silicon controlled electrostatic discharge device. The device overall structure is simple and effective, and the device is simply improved on the basis of the traditional device and has excellent practicability.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.

Claims (7)

1. A thyristor-type electrostatic discharge device comprising:

a substrate;

the P well region is positioned in the substrate;

the drift region is positioned in the substrate and does not overlap with the P well region;

a first P-doped region and a first N-doped region located in the P-well region, the first P-doped region being farther from the drift region than the first N-doped region;

the first N well region and the second N well region are positioned in the drift region, and the distance between the first N well region and the second N well region is greater than zero;

a second P-doped region and a second N-doped region respectively located in the first N-well region and the second N-well region, the second P-doped region being closer to the P-well region than the second N-doped region;

the gate oxide layer is arranged between the P well region and the N well region, one end of the gate oxide layer is contacted with the first N doping region, and the other end of the gate oxide layer is contacted with the second P doping region;

and the polycrystalline silicon layer is arranged on the gate oxide layer.

2. The SCR type electrostatic discharge device of claim 1,

the distance between the first N well region and the second N well region can be adjusted.

3. The SCR type electrostatic discharge device of claim 1,

the first P-doped region, the first N-doped region and the gate oxide layer are all electrically connected with the cathode of the silicon controlled electrostatic discharge device, and the second P-doped region and the second N-doped region are all electrically connected with the anode of the silicon controlled electrostatic discharge device.

4. The SCR type electrostatic discharge device of claim 1,

the gate oxide layer comprises a first section and a second section which are continuous, the thickness of the first section is smaller than that of the second section, the first section extends to the first N-doped region, the second section extends to the second P-doped region, and the second section is located in the drift region.

5. The SCR type electrostatic discharge device of claim 4,

the polycrystalline silicon layer is of a ladder structure matched with the gate oxide layer, completely covers the first section, and partially covers the second section.

6. The SCR type electrostatic discharge device of claim 1,

the distance between the P well region and the drift region is larger than zero.

7. An integrated circuit, comprising:

the silicon controlled electrostatic discharge device according to any one of claims 1 to 6.

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