CN107017248B - Low trigger voltage SCR structure based on floating trap triggering - Google Patents
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- CN107017248B CN107017248B CN201710149961.2A CN201710149961A CN107017248B CN 107017248 B CN107017248 B CN 107017248B CN 201710149961 A CN201710149961 A CN 201710149961A CN 107017248 B CN107017248 B CN 107017248B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
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- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 19
- 230000001960 triggered effect Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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Abstract
The invention belongs to the field of electrostatic discharge protection of integrated circuits, and particularly provides a floating well trigger-based low trigger voltage SCR structure for ESD protection, which is used for further reducing the trigger voltage of an LVTSCR device. According to the invention, through the internal structure design, a floating well structure is introduced into the device; the floating well structure is equivalent to a diode structure, the anode of the floating well structure is connected with the polysilicon grid of the PMOS, and the cathode of the floating well structure is connected with the anode of the SCR; when an ESD pulse arrives, the potential of the floating trap is lower relative to the anode potential of the SCR device, and when the potential difference between the floating trap and the SCR device is enough to enable the PMOS to be started; after the P-channel MOSFET is started, a parasitic NPN transistor in the SCR device is triggered to be started, a parasitic PNP transistor is triggered to be started, and finally the SCR device is started to discharge ESD current. Therefore, the trigger voltage of the device is determined by the floating well structure and the gate-source capacitance of the parasitic PMOS, so that the purpose of reducing the trigger voltage of the SCR device can be realized, and the trigger voltage can be modulated.
Description
Technical Field
The invention belongs to the field of electrostatic discharge (ESD) protection of an integrated circuit, relates to an ESD protection structure device, and particularly relates to a novel Silicon Controlled Rectifier (SCR) device structure with low trigger voltage for ESD protection.
Background
Electrostatic discharge is one of the important branches of reliability of integrated circuits, and occurs along with electrostatic discharge phenomena during the whole life cycle of electronic products, from chip manufacturing to production assembly, and from product transportation to daily use. Statistically, over one-third of electronic product failures are caused by ESD/EOS problems. In view of such a large number, attention is increasingly paid to designing ESD protection devices having superior performance.
In order to protect the chip against the static electricity attack, various static electricity protection devices have been proposed. In an integrated circuit, diodes, MOSFETs, SCRs, etc. may be used to function as ESD protection devices, with SCR being one of the most efficient ESD protection devices. After the SCR enters a conducting state, the voltage on the device is rapidly reduced to a very low value, so that the low thermal power loss of the device is ensured, and the SCR has very strong current discharge capacity. And compared with other ESD protection devices, the ESD protection capability per unit area of the SCR device is strongest.
In order to realize the protection function of the ESD protection device in a specific semiconductor process, the ESD protection device needs to realize a strong current discharge capability, and an ESD operating window formed by a trigger voltage and a holding voltage of the ESD protection device is within an ESD design window. Generally, the safe range of the device operating window should be less than the gate oxide breakdown voltage BV of conventional MOSFET devices in integrated circuitsox. This requires a turn-on voltage V of the ESD protection devicet1Must be less than BVox. Moreover, with the continuous progress of the manufacturing process of the integrated circuit in the 21 st century, the CMOS circuit formally enters the nanometer scale, and the ultrathin gate oxide layer is very fragile in the ESD stress surface. In this trend, it is important for the SCR device with low trigger voltage to discharge electrostatic charges to protect the gate oxide layer.
In a CMOS process, a device structure that a PMOS is embedded in an SCR device structure to reduce the trigger voltage of an SCR is generally adopted to reduce the turn-on voltage V of the SCR devicet1. The device is called LVTSCR (low voltage triggerring SCR), and the structure and the equivalent circuit diagram of the device are shown in FIG. 3; the device structure includes:
a p-type silicon substrate 110;
forming a well region on the substrate 110, wherein the well region comprises an n-type well region 120 and a p-type well region 130, and the well region 120 is adjacent to the well region 130;
an n-type heavily doped region 121 and a p-type doped region 122 are arranged in the n-type well region 120, and the region 121 and the region 122 are connected with an anode;
an n-type heavily doped region 131 and a p-type heavily doped region 132 are arranged in the p-type well region 130, and the region 131 and the region 132 are connected with a cathode;
a p-type heavily doped region 123 is bridged between the n-type well region 120 and the p-type well region 130;
a gate oxide region 140 is formed on the silicon surface between the p-type heavily doped region 122 and the p-type heavily doped region 123, and the gate oxide region 140 is connected to the anode through the polysilicon thereon.
The SCR device is composed ofA parasitic PNP transistor, a parasitic NPN transistor and a parasitic P-channel MOSFET device. Wherein, the p-type heavily doped region 122, the n-type well region 120, the p-type well region 130 and the p-type heavily doped region 132 form a PNP transistor; the heavily doped n-type region 131, the p-type well region 130, the n-type well region 120 and the heavily doped n-type region 121 form an NPN transistor; the P-type heavily doped region 122, the P-type heavily doped region 123 and the gate oxide layer 140 form a P-channel MOSFET; rNWIs the n-type well region 120 resistance; rPWIs the p-type well region 130 resistance. When an ESD event occurs, the drain-source P-n junction of the parasitic P-channel MOSFET is reversely biased. When the ESD voltage is so large that avalanche breakdown occurs in the P-n junction, a large number of electron-hole pairs are generated near the source region of the P-channel MOSFET device, holes enter the P-type well region 130 through the P-type heavily doped region 123 to form current, and the current flows in the R-type well region 130PWThereby generating a voltage drop to forward bias the p-n junction formed by the p-type well region 130 and the n-type heavily doped region 131, i.e. forward bias the emitter junction of the parasitic NPN transistor. At the same time, the electron current flows through the n-type well region 120 and the resistor RNWThe p-n junction formed by the p-type heavily doped region 122 and the n-type well region 120 is forward biased, i.e. the emitter junction in the PNP transistor is forward biased, so that the PNP transistor is turned on. And then, the collector current of the NPN tube provides base current for the PNP tube, the collector current of the PNP tube provides base current for the NPN tube, positive feedback is formed between the parasitic NPN tube and the PNP tube, and the SCR is conducted. Thus, the trigger voltage of LVTSCR devices is driven by the drain-source breakdown voltage BV of P-channel MOSFET devicesDSDetermining; the trigger voltage is still too large for low voltage processes.
Disclosure of Invention
The invention aims to provide a novel low trigger voltage SCR structure based on floating well triggering, which is used for further reducing the trigger voltage of an LVTSCR device. According to the structure, through the internal structure design, a floating well structure is introduced into the device, and based on floating well triggering, the triggering voltage of the SCR device is effectively reduced and can be modulated.
In order to achieve the purpose, the invention adopts the technical scheme that:
a floating well triggering-based low trigger voltage SCR structure comprising:
a first conductivity type silicon substrate;
a second conductive type deep well region formed on the first conductive type silicon substrate;
the second conductive type well region and the first conductive type well region are formed on the second conductive type deep well region in an adjacent mode, a second conductive type heavily doped region and a first conductive type heavily doped region which are connected with an anode are arranged in the second conductive type well region, a second conductive type heavily doped region and a first conductive type heavily doped region which are connected with a cathode are arranged in the first conductive type well region, a first conductive type heavily doped region is bridged between the second conductive type well region and the first conductive type well region, a gate oxide region is arranged on the silicon surface between the bridged first conductive type heavily doped region and the second conductive type heavily doped region in the first conductive type well region, and polycrystalline silicon covers the gate oxide region;
the second conductive type deep well region is formed with another first conductive type well region and is adjacent to the other side of the second conductive type well region, the first conductive type well region is provided with a first conductive type heavily doped region, and the first conductive type heavily doped region is connected with the polysilicon through a metal layer.
Furthermore, in the SCR structure, the second conductivity type well region, the first conductivity type well region, and the layout of the first conductivity type heavily doped region and the second conductivity type heavily doped region in the well region are all distributed in a stripe shape, and the layout of the gate oxide region is distributed in a stripe shape or divided in proportion.
The invention has the beneficial effects that:
the invention provides a low trigger voltage SCR structure based on floating well triggering, which is characterized in that a floating well structure is introduced into a device through an internal structure design; the floating well structure is equivalent to a diode structure, the anode of the floating well structure is connected with the polysilicon grid of the PMOS, and the cathode of the floating well structure is connected with the anode of the SCR; when the ESD pulse arrives, the potential of the floating trap is lower relative to the anode potential of the SCR device, and when the potential difference between the floating trap and the SCR device is smallerEnough to turn on the PMOS; after the P channel MOSFET (PMOS) is started, a parasitic NPN transistor in the SCR device is triggered to be started, further a parasitic PNP transistor is triggered to be started, and finally the SCR device is started to discharge ESD current. Compared with the breakdown voltage BV from drain to sourceDSThe conventional LVTSCR was determined to use floating well triggered SCR to get the gate of the P-channel MOSFET to a lower potential to turn it on at a lower trigger voltage. Meanwhile, the layout parameters of the device can be adjusted according to application conditions to realize modulation of trigger voltage, for example, in fig. 2, the transverse width of the p-type heavily doped region 151 is changed and the division ratio of the gate oxide layer 160 is adjusted. Therefore, the trigger voltage of the SCR structure is determined by the floating well structure and the gate-source capacitance of the parasitic P-channel MOSFET, so that the purpose of reducing the trigger voltage of the SCR device can be realized, and the trigger voltage can be modulated.
Drawings
Fig. 1 is a schematic diagram of a low trigger voltage SCR structure based on floating well triggering and an equivalent circuit thereof.
Fig. 2 is a layout schematic diagram of a low trigger voltage SCR structure based on floating well triggering according to the present invention.
Fig. 3 is a schematic structural diagram of a conventional LVTSCR and an equivalent circuit.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
The present embodiment provides a floating well triggering-based low trigger voltage SCR structure, as shown in fig. 1, the structure includes:
a p-type silicon substrate 110;
an n-type deep well region 140 is formed on the substrate 110;
an n-type well region 120 and a p-type well region 130 which are adjacent are formed on the n-type deep well region 140;
an n-type heavily doped region 121 and a p-type heavily doped region 122 are arranged in the n-type well region 120, and the region 121 and the region 122 are connected with an anode;
an n-type heavily doped region 131 and a p-type heavily doped region 132 are arranged in the p-type well region 130, and the region 131 and the region 132 are connected with a cathode;
a p-type heavily doped region 123 is bridged between the n-type well region 120 and the p-type well region 130;
a gate oxide region 160 is arranged on the silicon surface between the p-type heavily doped region 122 and the p-type heavily doped region 123, and the surface of the gate oxide region 160 is covered by a polysilicon layer;
another p-type well region 150 adjacent to the other side of the n-type well region 120 is further formed on the n-type deep well region 140, a p-type heavily doped region 151 is disposed in the p-type well region 150, and the p-type heavily doped region 151 is connected to the polysilicon layer on the gate oxide region 160 through a metal layer.
An equivalent circuit diagram of the floating well triggering-based low trigger voltage SCR structure is shown in fig. 1, and the SCR device is composed of a parasitic PNP transistor, a parasitic NPN transistor, a parasitic P-channel MOSFET device (PMOS), and a floating well structure. Wherein, the p-type heavily doped region 122, the n-type well region 120, the p-type well region 130 and the p-type heavily doped region 132 form a PNP transistor; the heavily doped n-type region 131, the p-type well region 130, the n-type well region 120 and the heavily doped n-type region 121 form an NPN transistor; the P-type heavily doped region 122, the P-type heavily doped region 123 and the gate oxide region 160 form a P-channel MOSFET; the p-type well region 150 and the p-type heavily doped region 151 form a floating well structure; rNWIs the well resistance between the region of the n-type well region 120 starting from the heavily n-doped region 121 to where the n-well 120 adjoins the p-well 130; rPWResistance of p-type well region 130; the p-well 150 is a floating well and can be regarded as a diode structure, the anode of the diode is connected to the polysilicon gate plate 160 of the PMOS, and the cathode is connected to the anode of the SCR. When an ESD event occurs, due to the change of voltage along with time, the potential of the floating empty well is lower than the anode voltage of the SCR device, so that the gate voltage of the P-channel MOSFET is lower than the anode voltage, and the P-channel MOSFET is turned on. When the P-channel MOSFET device is turned on, holes enter the P-channel MOSFET channel region through the heavily doped P-type region 122 and then flow into the P-type well 130 through the heavily doped P-type region 123, forming a hole current path. The current is at RPWVoltage drop is generated, so that a p-n junction formed by the p-type well region 130 and the n-type heavily doped region 131 is forward biased, namely, an emitter junction of a parasitic NPN tube is forward biased, and the NPN tube is conducted. At the same time, parasitizeCollector current of NPN tube flows through n-type well region 120 resistor RNWThe p-n junction formed by the p-type heavily doped region 122 and the n-type well region 120 is forward biased, i.e. the emitter junction in the PNP transistor is forward biased, so that the PNP transistor is turned on. And then, the collector current of the NPN tube provides base current for the PNP tube, the collector current of the PNP tube provides base current for the NPN tube, positive feedback is formed between the parasitic NPN tube and the PNP tube, and the SCR is conducted. Therefore, the trigger voltage of the device is determined by the floating well structure and the gate-source capacitance of the parasitic P-channel MOSFET, the purpose of reducing the trigger voltage of the SCR device can be realized, and the trigger voltage can be modulated.
FIG. 2 is a schematic diagram of a layout of an SCR device embodying the present invention;
the layout 100 shows a layout of a strip-shaped SCR device, in which the layouts of a deep n-type well region 140, a p-type well region 150, an n-type well region 120, a p-type well region 130, a p-type heavily doped region 151, an n-type heavily doped region 121, a p-type heavily doped region 122, and a p-type heavily doped region 123, an n-type heavily doped region 131, and a p-type heavily doped region 132 are all distributed in a strip shape, and the layout of a gate oxide region 160 is also distributed in a strip shape.
The layout 200 shows a layout of a strip-shaped SCR device, in which the layouts of the deep n-well region 140, the p-type well region 150, the n-type well region 120, the p-type well region 130, the p-type heavily doped region 151, the n-type heavily doped region 121, the p-type heavily doped region 122, and the p-type heavily doped region 123, the n-type heavily doped region 131, and the p-type heavily doped region 132 are all distributed in a strip shape, and the layout of the gate oxide region 160 is distributed in a divided manner according to a certain proportion. The purpose of adjusting the size of the gate-source capacitor of the parasitic P-channel MOSFET device can be achieved by adjusting the division ratio of the layout, so that the trigger voltage of the SCR device can be adjusted.
While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.
Claims (2)
1. A floating well triggering-based low trigger voltage SCR structure comprising:
a first conductivity type silicon substrate;
a second conductive type deep well region formed on the first conductive type silicon substrate;
the second conductive type well region and the first conductive type well region are formed on the second conductive type deep well region in an adjacent mode, a second conductive type heavily doped region and a first conductive type heavily doped region which are connected with an anode are arranged in the second conductive type well region, a second conductive type heavily doped region and a first conductive type heavily doped region which are connected with a cathode are arranged in the first conductive type well region, a first conductive type heavily doped region is bridged between the second conductive type well region and the first conductive type well region, a gate oxide region is arranged on the silicon surface between the first conductive type heavily doped region and the first conductive type heavily doped region in the bridged first conductive type well region, and polycrystalline silicon covers the gate oxide region;
wherein another well region of the first conductivity type is formed over the deep well region of the second conductivity type, the another well region of the first conductivity type is adjacent to the other side of the well region of the second conductivity type, a heavily doped region of the first conductivity type is disposed in the well region of the first conductivity type, and the heavily doped region of the first conductivity type is connected to the polysilicon through a metal layer.
2. The floating well triggering-based low trigger voltage SCR structure of claim 1, wherein in the SCR structure, the well region of the second conductivity type, the well region of the first conductivity type, and the layout of the heavily doped region of the first conductivity type and the heavily doped region of the second conductivity type in the well region are all distributed in a stripe shape, and the layout of the gate oxide region is distributed in a stripe shape or divided in proportion.
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| CN107833884B (en) * | 2017-11-02 | 2023-06-23 | 杰华特微电子股份有限公司 | Silicon controlled rectifier circuit for electrostatic protection and device structure thereof |
| CN107680965B (en) * | 2017-11-10 | 2023-07-25 | 江南大学 | ESD protection device based on SCR structure and triggered in double MOS assistance |
| US10504886B1 (en) * | 2018-09-05 | 2019-12-10 | Hong Kong Applied Science and Technology Research Institute Company, Limited | Low-capacitance electro-static-discharge (ESD) protection structure with two floating wells |
| CN109314131B (en) * | 2018-09-05 | 2021-06-08 | 香港应用科技研究院有限公司 | Low capacitance electrostatic discharge (ESD) protection structure with double floating-connected wells |
| CN110571214B (en) * | 2019-08-28 | 2021-08-06 | 电子科技大学 | Silicon controlled rectifier structure with multiple trigger channels |
| TWI710096B (en) * | 2019-09-04 | 2020-11-11 | 智原科技股份有限公司 | Electrostatic discharge protection apparatus |
| CN112071834B (en) * | 2020-09-25 | 2024-05-17 | 上海华力微电子有限公司 | Grid-constrained silicon controlled rectifier and implementation method thereof |
| CN112071835B (en) * | 2020-09-25 | 2024-03-15 | 上海华力微电子有限公司 | Grid-constrained silicon controlled rectifier and implementation method thereof |
| CN113380786B (en) * | 2021-08-11 | 2021-11-16 | 江苏应能微电子有限公司 | Thyristor transient voltage suppression protection device structure integrated with reverse conducting diode |
| CN113793865A (en) * | 2021-08-24 | 2021-12-14 | 上海华力微电子有限公司 | Gate-constrained silicon controlled rectifier and manufacturing method thereof |
| CN113571513B (en) * | 2021-09-23 | 2022-01-04 | 四川上特科技有限公司 | Low-trigger high-robustness SCR device and protection circuit for transient suppressor |
| US11837600B2 (en) | 2021-11-15 | 2023-12-05 | Macronix International Co., Ltd. | Electrostatic discharge protection apparatus and its operating method |
| TWI791325B (en) * | 2021-11-15 | 2023-02-01 | 旺宏電子股份有限公司 | Electrostatic discharge protection apparatus and its operating method |
| CN117673072A (en) * | 2022-08-24 | 2024-03-08 | 无锡华润上华科技有限公司 | Thyristor and ESD protection device |
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| CN105374817A (en) * | 2015-12-23 | 2016-03-02 | 电子科技大学 | SCR device based on germanium-silicon heterojunction process |
| CN105633071A (en) * | 2014-11-07 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and electronic device |
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| TW419808B (en) * | 1999-07-31 | 2001-01-21 | Winbond Electronics Corp | Electrostatic discharge device capable of avoiding latch up effect |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105633071A (en) * | 2014-11-07 | 2016-06-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and electronic device |
| CN105374817A (en) * | 2015-12-23 | 2016-03-02 | 电子科技大学 | SCR device based on germanium-silicon heterojunction process |
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