CN105374817A - SCR device based on germanium-silicon heterojunction process - Google Patents
SCR device based on germanium-silicon heterojunction process Download PDFInfo
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- CN105374817A CN105374817A CN201510980245.XA CN201510980245A CN105374817A CN 105374817 A CN105374817 A CN 105374817A CN 201510980245 A CN201510980245 A CN 201510980245A CN 105374817 A CN105374817 A CN 105374817A
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- well region
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- 238000000034 method Methods 0.000 title claims abstract description 17
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 title claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 238000005516 engineering process Methods 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 description 11
- 230000003068 static effect Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000009024 positive feedback mechanism Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000010892 electric spark Methods 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
Abstract
The invention belongs to the technical field of electrostatic discharge protection of an integrated circuit, and provides an SCR device, which is used to reduce a trigger voltage of an SCR device, based on germanium-silicon heterojunction process. The SCR device based on the germanium-silicon heterojunction technology comprises a first-kind conductive-type silicon substrate, a second-kind conductive-type well region and a first-kind conductive-type well region which are adjacently connected are formed on the silicon substrate, a second-kind conductive-type heavily doped region and a first-kind conductive-type heavily doped region are disposed in the second-kind conductive-type well region, a second-kind conductive-type heavily doped region and a first-kind conductive-type heavily doped region are disposed in the first-kind conductive-type well region, a non-device structure region on a silicon surface of the second-kind conductive-type well region is further provided with a first-kind conductive-type germanium-silicon layer, a second-kind conductive-type heavily doped polycrystalline silicon layer is disposed on the first-kind conductive-type germanium-silicon layer, and the second-kind conductive-type heavily doped polycrystalline silicon layer is connected with a cathode. An SCR structure and an HBT structure are combined together, the trigger voltage of the SCR device is effectively reduced, and the SCR device of the invention can adjust the trigger voltage of the SCR device through the HBT structure.
Description
Technical field
The invention belongs to static discharge (ESD) the resist technology field of integrated circuit, relate to a kind of esd protection structure device, be specifically related to a kind of SCR device based on Ge-Si heterojunction technique.
Background technology
Static discharge (ElectrostaticDischarge, be called for short ESD) is the very general phenomenon of occurring in nature, is the Charger transfer occurring moment between two electrified bodies.All can make electrostatic charge on object band by friction or electrostatic induction, when two objects with different electromotive force are close to each other or directly contact, all static discharge phenomenon can occur, often be attended by visible electric spark.Static discharge can produce the voltage up to volt up to ten thousand, and so large electrostatic potential will form huge threat to integrated circuit (IC).In the whole life cycle of integrated circuit (IC) products, from manufacture, encapsulation, test, transport, use in complete IC product, all the moment is faced with the threat that static discharge is formed.In order to head it off; manufacturer arranges a protective circuit usually between internal circuit and I/O pin; this protective circuit must be opened in advance before the pulse of static discharge does not arrive internal circuit, with ESD big current of releasing rapidly, and then the destruction that minimizing ESD phenomenon causes.
Conventional ESD protective device has diode, insulated-gate type field effect transistor (MOSFET), bipolar transistor (BJT), thyristor (SCR); Wherein, SCR device can make full use of trap and substrate as current drain path, and this makes device can bear larger ESD immediate current, compares other ESD protective device, and the unit are esd protection ability of SCR device is the strongest.But the shortcoming that the SCR device of routine is used to ESD protection is cut-in voltage (V
t1) too large, and be greater than the grid oxygen puncture voltage of MOSFET; But along with constantly the reducing of characteristic size of device, the thickness of gate oxide is also constantly thinning; Under this trend, it is the problem that those skilled in the art constantly study that development low pressure triggers SCR device.
At present, as shown in Figure 1, this device architecture comprises for basic SCR device structure and equivalent electric circuit thereof:
P-type silicon substrate 110;
Described substrate 110 forms well region, and described well region comprises a N-shaped well region 120 and a p-type well region 130, and described well region 120 adjoins described well region 130;
Be provided with N-shaped heavily doped region 121 and p-type heavily doped region 122 in described N-shaped well region 120, and described region 121 is connected with anode with region 122;
Be provided with N-shaped heavily doped region 131 and p-type heavily doped region 132 in described p-type well region 130, and region 131 is connected with negative electrode with region 132.
The equivalent circuit diagram of above-mentioned SCR device can be seen, this SCR device is made up of a parasitic pnp transistor and a parasitic npn transistor.Wherein, p-type heavily doped region 122, N-shaped well region 120, p-type well region 130 and p-type heavily doped region 132 form a pnp transistor, N-shaped heavily doped region 131, p-type well region 130, N-shaped well region 120 and N-shaped heavily doped region 121 form a npn transistor, R_nw is N-shaped well region 120 resistance, and R_pw is p-type well region 130 resistance.When esd event comes interim, the collector junction of parasitic npn pipe is reverse-biased.When this reversed bias voltage is greater than the avalanche breakdown voltage of this pn knot, this pn ties and produces a large amount of electron hole pair formation electric currents, wherein, electronic current flows through N-shaped well region 120 and produce pressure drop on R_nw, the pn that p-type heavily doped region 122 and N-shaped well region 120 are formed ties positively biased, the i.e. emitter junction positively biased of parasitic pnp pipe, pnp pipe is opened.Meanwhile, hole current flows through p-type well region 130 resistance R_pw, and the pn that N-shaped heavily doped region 131 and p-type well region 130 are formed ties positively biased, and the emitter junction positively biased namely in npn pipe, makes npn pipe open.Afterwards, the collector current of pnp pipe provides base current for npn pipe, and the collector current of npn pipe provides base current for pnp pipe, between parasitic pnp pipe with npn pipe, produce positive feedback mechanism, SCR conducting.Therefore, the trigger voltage of this basic SCR device is that the avalanche breakdown voltage of the pn knot formed by N-shaped well region 120 and p-type well region 130 determines, and this voltage is often greater than the puncture voltage of the gate oxide of this technique in common process; Therefore this device directly can not be used in the esd protection circuit of integrated circuit, and needs increase safe secondary protection circuit to use, and will increase the chip area of esd protection circuit like this.
Based on this, the invention provides the SCR device that a kind of new E SD protects, reduce the trigger voltage of SCR device further.
Summary of the invention
The object of the present invention is to provide a kind of SCR device based on Ge-Si heterojunction technique, for reducing the trigger voltage of SCR device.The technical solution used in the present invention is:
A kind of SCR device based on Ge-Si heterojunction technique, comprise the first conduction type silicon substrate, silicon substrate is formed adjacent the second conduction type well region and the first conduction type well region, the second conduction type heavily doped region and the first conduction type heavily doped region that are connected with anode is provided with in described the second conduction type well region, the second conduction type heavily doped region and the first conduction type heavily doped region that are connected with negative electrode is provided with in the first conduction type well region described, it is characterized in that, the silicon face of described the second conduction type well region is also provided with the first conduction type germanium silicon layer without device architecture region, the first conduction type germanium silicon layer described is provided with the second conduction type heavily doped polysilicon layer, and the second conduction type heavily doped polysilicon layer is connected with negative electrode.
Further, the first conduction type germanium silicon layer described is connected by external resistance with the second conduction type heavily doped polysilicon layer.
The invention provides a kind of SCR device based on Ge-Si heterojunction technique, this device architecture is on existing SCR device architecture basics, SCR structure and HBT structure are combined, when esd event arrives, HBT structure is On current first, this electric current is trigger current triggering SCR device unlatching further again, effectively can be reduced the trigger voltage of SCR device, and SCR device of the present invention can regulate the trigger voltage of SCR device by HBT structure by Novel SCR provided by the invention.In addition, be embedded in SCR structure in the present invention by HBT structure, the chip area that SCR device can be avoided to take increases.
Accompanying drawing explanation
The existing basic SCR device structure of Fig. 1 and schematic equivalent circuit.
Fig. 2 embodiment 1 is based on the Novel SCR device architecture of Ge-Si heterojunction technique and schematic equivalent circuit.
Fig. 3 embodiment 2 is based on the Novel SCR device architecture of Ge-Si heterojunction technique and schematic equivalent circuit.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Embodiment 1
In the present embodiment based on the Novel SCR device architecture of Ge-Si heterojunction technique and equivalent electric circuit as shown in Figure 2, this SCR device structure comprises:
P-type silicon substrate 110;
Described p-type silicon substrate 110 forms well region, and described well region comprises a N-shaped well region 190 and a p-type well region 130, and described N-shaped well region 190 adjoins described p-type well region 130;
Be provided with the first N-shaped heavily doped region 121 and the first p-type heavily doped region 122 in described N-shaped well region 190, and described first N-shaped heavily doped region 121 is connected with anode with the first p-type heavily doped region 122;
Be provided with the second N-shaped heavily doped region 131 and the second p-type heavily doped region 132 in described p-type well region 130, and described second N-shaped heavily doped region 131 is connected with negative electrode with the second p-type heavily doped region 132;
The silicon face of described N-shaped well region 190 is formed pXing Zhe silicon layer district 170, described pXing Zhe silicon layer district 170 is positioned at the first p-type heavily doped region 122 near the side of N-shaped well region 190 with p-type well region 130 adjoiner;
Described pXing Zhe silicon layer district 170 forms N-shaped heavily doped polysilicon layer district 180, and described N-shaped heavily doped polysilicon layer district 180 is connected with negative electrode.
Can see from equivalent circuit diagram, above-mentioned SCR device is made up of a parasitic pnp transistor, a parasitic npn transistor and a parasitic HBT; Wherein, p-type heavily doped region 122, N-shaped well region 190, p-type well region 130 and p-type heavily doped region 132 form a pnp transistor; N-shaped heavily doped region 131, p-type well region 130, N-shaped well region 190 and N-shaped heavily doped region 121 form a npn transistor; N-shaped well region 190, p-type germanium silicon area 170 and N-shaped heavily doped polysilicon district 180 form a HBT; R_nw is N-shaped well region 190 resistance, and R_pw is p-type well region 130 resistance.
When esd event comes interim, the anode voltage of SCR device rises, and makes the collector junction of the HBT device be made up of pXing Zhe silicon layer district 170 and N-shaped heavily doped polysilicon layer district 180 reverse-biased; When ESD voltage is greater than the collector junction avalanche breakdown voltage BV of the HBT device of open base
cEOtime, the pn formed in pXing Zhe silicon layer district 170 and N-shaped well region 190 ties near knot face and will produce a large amount of electron hole pairs; Wherein, hole flows to negative electrode, parasitic HBT conducting by the forward biased pn knot formed by N-shaped heavily doped polysilicon district 180 and pXing Zhe silicon layer district 170; And electronics is successively by N-shaped well region 190 and N-shaped heavily doped region 121, finally flow into anode, form current channel; This electronic current flows through N-shaped well region 190 and produce pressure drop on R_nw, and the pn that p-type heavily doped region 122 and N-shaped well region 190 are formed ties positively biased, makes the conducting of parasitic pnp pipe; Meanwhile, the collector current of pnp pipe flows through p-type well region 130 resistance R_pw, and the pn that N-shaped heavily doped region 131 and p-type well region 130 are formed ties positively biased, and npn pipe is opened; Afterwards, the collector current of pnp pipe provides base current for npn pipe, and the collector current of npn pipe provides base current for pnp pipe, between parasitic pnp pipe with npn pipe, produce positive feedback mechanism, SCR conducting.It can thus be appreciated that the trigger voltage of this Novel SCR device is by the collector junction avalanche breakdown voltage (BV of the HBT device of open base
cEO) determine, thus effectively reduce the trigger voltage of SCR device; In addition, this Novel SCR device architecture, except reducing except trigger voltage, also regulate the trigger voltage of SCR device by HBT structure, and HBT structure is embedded in SCR structure, and the chip area that SCR device can be avoided to take increases.
Embodiment 2
In the present embodiment based on the Novel SCR device architecture of Ge-Si heterojunction technique and equivalent electric circuit as shown in Figure 3, described in this SCR device structure, pXing Zhe silicon layer district 170 is connected by external resistance R with N-shaped heavily doped polysilicon layer district 180.
Above-mentioned Novel SCR devices function principle is identical with embodiment 1, the trigger voltage of this Novel SCR device is that the collector junction avalanche breakdown voltage of the HBT device be connected by external resistance with emitter by base stage is determined, and can be controlled the trigger voltage of SCR device by the size adjusting outer meeting resistance.
The above, be only the specific embodiment of the present invention, arbitrary feature disclosed in this specification, unless specifically stated otherwise, all can be replaced by other equivalences or the alternative features with similar object; Step in disclosed all features or all methods or process, except mutually exclusive feature and/or step, all can be combined in any way.
Claims (2)
1. the SCR device based on Ge-Si heterojunction technique, comprise the first conduction type silicon substrate, silicon substrate is formed adjacent the second conduction type well region and the first conduction type well region, the second conduction type heavily doped region and the first conduction type heavily doped region that are connected with anode is provided with in described the second conduction type well region, the second conduction type heavily doped region and the first conduction type heavily doped region that are connected with negative electrode is provided with in the first conduction type well region described, it is characterized in that, the silicon face of described the second conduction type well region is also provided with the first conduction type germanium silicon layer without device architecture region, the first conduction type germanium silicon layer described is provided with the second conduction type heavily doped polysilicon layer, and the second conduction type heavily doped polysilicon layer is connected with negative electrode.
2., by the SCR device based on Ge-Si heterojunction technique described in claim 1, it is characterized in that, the first conduction type germanium silicon layer described is connected by external resistance with the second conduction type heavily doped polysilicon layer.
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| CN201510980245.XA CN105374817B (en) | 2015-12-23 | 2015-12-23 | A kind of SCR device based on Ge-Si heterojunction technique |
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| CN201510980245.XA CN105374817B (en) | 2015-12-23 | 2015-12-23 | A kind of SCR device based on Ge-Si heterojunction technique |
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| CN105374817A true CN105374817A (en) | 2016-03-02 |
| CN105374817B CN105374817B (en) | 2018-12-18 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017248A (en) * | 2017-03-14 | 2017-08-04 | 电子科技大学 | A kind of low trigger voltage SCR structure triggered based on floating trap |
| CN109309129A (en) * | 2018-09-14 | 2019-02-05 | 北京大学 | Gg-NMOS device based on FDSOI |
| CN112466938A (en) * | 2020-11-26 | 2021-03-09 | 中国科学院微电子研究所 | Silicon controlled rectifier device applied to electrostatic protection of deep submicron circuit |
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| CN101840918A (en) * | 2010-04-14 | 2010-09-22 | 电子科技大学 | Silicon controlled rectifier electro-static discharge protective circuit structure triggered by diode |
| US20120153347A1 (en) * | 2010-12-17 | 2012-06-21 | National Semiconductor Corporation | ESD clamp with auto biasing under high injection conditions |
| CN102569288A (en) * | 2010-12-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | Electrostatic protection structure |
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2015
- 2015-12-23 CN CN201510980245.XA patent/CN105374817B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101840918A (en) * | 2010-04-14 | 2010-09-22 | 电子科技大学 | Silicon controlled rectifier electro-static discharge protective circuit structure triggered by diode |
| US20120153347A1 (en) * | 2010-12-17 | 2012-06-21 | National Semiconductor Corporation | ESD clamp with auto biasing under high injection conditions |
| CN102569288A (en) * | 2010-12-17 | 2012-07-11 | 上海华虹Nec电子有限公司 | Electrostatic protection structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017248A (en) * | 2017-03-14 | 2017-08-04 | 电子科技大学 | A kind of low trigger voltage SCR structure triggered based on floating trap |
| CN107017248B (en) * | 2017-03-14 | 2020-03-27 | 电子科技大学 | Low trigger voltage SCR structure based on floating trap triggering |
| CN109309129A (en) * | 2018-09-14 | 2019-02-05 | 北京大学 | Gg-NMOS device based on FDSOI |
| CN112466938A (en) * | 2020-11-26 | 2021-03-09 | 中国科学院微电子研究所 | Silicon controlled rectifier device applied to electrostatic protection of deep submicron circuit |
| CN112466938B (en) * | 2020-11-26 | 2023-11-14 | 中国科学院微电子研究所 | Silicon controlled device applied to deep submicron-level circuit electrostatic protection |
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